Chapter 5

Sequential Logic Circuits

Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah

Sequential logic circuit
A Sequential logic circuit is different from combinational logic circuits. In sequential circuit the output
of the logic device is not only dependent on the present inputs to the device, but also on past outputs.
In other words output of a sequential logic circuit depends on present input as well as previous state of
the circuit.
Unlike combinational circuits, the sequential circuits have memory devices in order to store the past
outputs. In fact sequential digital logic circuits are nothing but combinational circuit with memory.
Latch, flip-flop, registers, counters are some example of Sequential logic circuit.

Figure- block diagram of Sequential circuit

Sequential logic circuits are classified as synchronous and asynchronous circuit.
Clock Driven Circuits or synchronous circuit
These are synchronous logic circuit, where the output state transition takes place only when the input
signal is applied along with clock pulses. Synchronous sequential circuit uses pulsed or clock inputs.
Event Driven Circuits or asynchronous circuits
These are asynchronous logic circuits, where the output state transition takes place even if we don’t
apply the input signal along with the clock pulses. Asynchronous circuit uses pulses of inputs instead of
clock signal.
Difference between combinational Circuit and Sequential circuits
S.n. Combinational Circuit Sequential Circuit
1. In Combinational Circuit, output depends In Sequential Circuit, output depends upon
only upon present input. present as well as past output.
2. Speed is fast. Speed is slow.
3. Its design is easy. Its design is tough as compared to
combinational circuits.
4. There is no feedback between input and There exists a feedback path between input and
output. output.
5. This is time independent. This is time dependent.
6. Elementary building blocks: Logic gates Elementary building blocks: Flip-flops
7. Used for arithmetic as well as Boolean Mainly used for storing data.
operations.
8. Combinational circuits don’t have capability Sequential circuits have capability to store any
to store any state. state or to retain earlier state.
9 As combinational circuits don’t have clock, As sequential circuits are clock dependent they
they don’t require triggering. need triggering.
10. These circuits do not have any memory These circuits have memory element.
element.
11. It is easy to use and handle. It is not easy to use and handle.
Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah
Latch
A Latch is an electronic device that instantly changes its output based on the applied input. We use latch
to store either 0 or 1 at any specified time. The "SET" and "RESET" are two inputs in a latch, and there
are two outputs that are complement to each other. We use latch to store one bit of data and it is a
memory device.

A Latch is a special type of logical circuit. The latches have low and high two stable states. Due to these
states, latches also refer to as bistable-multivibrator. Latches are of two types they are SR latch and D
latch

Flip-Flop
Flip-flop is a digital memory circuit, and with the help of the flip-flop we can store one bit of
information. The fundamental blocks of various sequential circuits are flip-flops. Flip-flop is also called
a bistable multivibrator or one-bit or binary. In a sequential circuit, we use flip-flops as a memory
element.

In a sequential circuit, the output is obtained from the combinational circuit or flip-flop or both. When
the clock pulse is active, then the state of the flip-flop is active, and when the clock pulse is not active,
then the state of the clock pulse remains unaffected. Mainly, in the synchronous sequential circuit, flip
flops function as a memory element, and in asynchronous sequential circuit, the unclocked flip flops or
latches function as a memory element.

Trigger
In the context of flip-flops, the term "trigger" refers to the specific event that causes the flip-flop to
capture or update its state. It determines when the inputs are considered and when the outputs are
changed. There are two common types of triggers used in flip-flops i.e. Level triggering and edge
triggering

Level trigger: It refers to a triggering mechanism where a circuit or flip-flop responds to the continuous
level of an input signal rather than a specific edge transition. In other words, the circuit reacts or changes
its state when the input signal maintains a particular logic level (high or low) for a sustained period of
time.

Positive-Edge Trigger: A positive-edge trigger, also known as a rising-edge trigger or clocked flip-flop,
responds to a transition from a low (logic 0) to a high (logic 1) level on the clock input. When the clock
signal rises from low to high, the flip-flop samples and latches the input values and updates its outputs
based on those values. Positive edge triggered flip-flops are widely used in synchronous digital systems.

Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah

Negative-Edge Trigger: A negative edge trigger, also known as a falling-edge trigger, responds to a
transition from a high (logic 1) to a low (logic 0) level on the clock input. When the clock signal falls
from high to low, the flip-flop captures and stores the input values, updating its outputs accordingly.
Negative edge triggered flip-flops are less commonly used than positive-edge-triggered flip-flops but
still find applications in certain scenarios.

Clock Pulse Transition

The movement of a trigger pulse is always from a 0 to 1 and then 1 to 0 of a signal. Thus it takes two
transitions in a single signal.
When it moves from 0 to 1 it is called a positive transition and
When it moves from 1 to 0 it is called a negative transition.

Difference between Latch and Flip-Flop

S.N. Latch Flip-Flop
1. A Latch is a bistable device, and the state of the Flip-Flop is also a bistable device and there are
latch is represented as 0 and 1. two stable states of Flip-Flop, which are
represented as 0 and 1.
2. A Latch is a level triggered device. Flip-flop is an edge triggered device.
3. Latches cannot be classify Flip-flops are classified as synchronous or
asynchronous flip-flops.
4. To form sequential circuits, latches are To form sequential circuits, Flip-Flop is
constructed from logic gates. constructed from latches along with an additional
clock signal.
5. Latches are fast as compared to the Flip-Flop. Flip-Flops are slow as compared to the latches.
6. Less power is consumed by the Latches. More power is consumed by the Flip-Flop.
7. The latches can be clocked or clockless. For all the time, Flip-Flops are clocked.
8. Only binary inputs can be used to operate the By the clock signal and binary input, the Flip-
latches. Flop works.
9. The latch is sensitive to the input and as long as Flip-Flop is sensitive to the clock signals and until
it is 'On', we can transmit the data. there is a change in the input clock signal, it never
changes the output.
11. The latch is asynchronous because latch does Flip-Flop is synchronous because flip-flop work
not work on the basis of the time signal. on the basis of the clock signal.
12. The latch can be built from the gates. Flip-Flop can be built from the latches.
13. Latches are responsive towards faults on enable Flip-Flops are protected toward fault.
pin.

Types of Latch
There are three types of Latch and they are
• SR Latch
• Gated SR Latch
• Gated D Latch

Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah

SR Latch
SR latch is also called Set-Reset latch, is a fundamental building block in digital electronics. It is a type
of bistable multivibrator, meaning it has two stable states.

The SR latch is a circuit can be made by using two cross-coupled NOR gates or two cross-
coupled NAND gates with two inputs labeled S (for Set) and R (for Reset) and with two complementary
outputs Q and .

Figure – Symbol of RS Latch

SR Latch using Cross Coupled NOR gates

It latch has two useful states.
When output Q =1 and 0, the latch is said to be in the Set state.
When Q = 0 and =1, it is in Reset state.
Normally, outputs Q and both are complement to each other.

S R Q Comment
0 0 Hold Hold No change
0 1 0 1 Reset
1 0 1 0 Set
1 1 0 0 Invalid state
(not used)

Figure – SR Latch using NOR gate Figure – Truth table of SR Latch using NOR gate

Working of SR latch using NOR

Case-I
If S = 0, R = 1 then the output Q = 0 because anyone input is high (1) then the output of NOR gate is
low (0) and the both input of another NOR gate is low (0) then the output = 1.
Now let S = 0, R = 0 then the outputs Q = 0 and = 1. This means it store previous value.
Case-II
If S = 1, R = 0 then the output = 0 because anyone input is high (1) then the output of NOR gate is
low (0) and the both input of another NOR gate is low (0) then the output Q = 1.
Now let S=0, R=0 then the outputs Q = 1 and = 0. This means it store previous value.
Case-III
If S =1, R =1 then Q = 0, = 0. Here both the outputs are low so this is an invalid condition because
both the outputs must be complementary outputs.

Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah

SR Latch using Cross Coupled NAND gate

S R Q Comment
0 0 1 1 Invalid state
(not used)
0 1 1 0 Set
1 0 0 1 Reset
1 1 Hold Hold No change

Figure – SR Flip flop using NAND gate Figure – Truth table of SR Flip flop using NAND gate

Working of SR latch using NOR

Case-I
If S = 0, R =1 then the output Q = 1 because anyone input is low (0) then the output of NAND gate is
high (1) and the both input of another NAND gate is high (1) then the output = 0.
Now let S =1, R =1 then the outputs Q = 1 and = 0. This means it store previous value.

Case – II
If S =1, R = 0 then the output = 1 because anyone input is low (0) then the output of NAND gate is
high (1) and the both input of another NAND gate is high (1) then the output Q = 0.
Now let S =1, R =1 then the outputs Q = 0 and = 1. This means it store previous value.

Case – III
If S = 0, R = 0 then Q = 1 = 1. Here both the outputs are high so this is an invalid condition because
both the outputs must be complementary outputs.

Contact switch bouncing

Contact switch bouncing, also known as switch bounce or mechanical bounce, refers to the rapid and
unintended oscillation of the switch contacts when the switch is pressed or released. This bouncing
phenomenon occurs due to the mechanical movement and imperfect contact between the switch's metal
surfaces. As a result, the switch may make and break the electrical connection multiple times in quick
succession before settling into a stable state.

Elimination of the contact switch bouncing

To eliminate contact switch bouncing a simple RS flip flop de-bouncing circuit is used as shown below:
Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah
 Figure – Switch contact De-bouncing circuit and switch bounce

Here when the is moved to the position H, R=0 and S=1 then the flip flop is set with Q=1 at the first
high level on S. Again when switch bounce losing the contact to the input signal then S=R=0, therefore
the flip flop remains set Q=1. When the switch regain contact R=0 and S=1; this causes an attempt to
again set the flip flop but the flip flop is already set no change occurs at Q. the result is a “clean” low to
high signal at its output.

When the switch is moved to the position L, S =0 and R =1. Bouncing occurs at the R input due to
switch. Here it simply respond to the first high lelvel and ignores all following transition. Th result is a
“clean” low to high signal at its output.

Gated SR Latch
A gated latch requires an enable input, EN. The Gated SR latch circuit has two inputs and two outputs
i.e. a set input (S), a reset input (R), outputs Q and . SR Latch can be constructed by using cross-
coupled NAND and NOR gates. Figure shows the logic circuit diagram, symbols and truth table of gated
SR latch.

Figure – Gated SR Latch (a) using Cross Couple NAND and (b) using Cross Couple NOR

EN S R Q
0 X X Memory state
1 0 0 Memory state
1 0 1 0 1
1 1 0 1 0
1 1 1 Invalid

Figure – Symbol of Gated SR Latch Figure – Truth table of Gated SR Latch

Working of Gated SR latch
Case I:
Now if EN is 0, S and R will be treated as don’t care conditions, then we get Q and in memory state
i.e. holding previous values.
Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah
Case II:
If EN =1 then there will be 4 more cases depending upon the values of S and R.
Case II (a): S = 0 and R = 0 then both input of SR Latch becomes 1 and we get outputs Q and in
holding memory state.
Case II (b): S = 0 and R =1 then we get Q = 0 and = 1, we get both outputs as complement of each
other and the SR latch is in reset state.
Case II (c): S = 1 and R = 0 them we get Q = 1 and = 0. The SR latch is in set state.
Case II (d): S =1 and R =1 then both input of SR Latch becomes 0 and we get Q and in the invalid
state i.e. not used condition.

Gated D Latch
The Gated SR latch circuit has two inputs and two outputs i.e. a set input (S), a reset input (R), outputs
Q and ( Q ) ̅ .
Another type of gated latch is called the D latch. It differs from the S-R latch because it has only one
input in addition to EN. This input is called the D (data) input. It has two outputs Q and . Figure
shows logic diagram, symbol and truth table of a D latch.

Figure – Logic diagram of Gated D Latch Figure – Symbol of Gated D Latch

EN D Q Comment
0 X Hold Hold Memory state
1 0 1 Reset state
1 1 1 0 Set state
Figure – Truth table of Gated D Latch
Working of Gated D Latch
• If EN = 0, D will be treated as don’t care conditions, then we get Q and in memory state i.e.
holding previous values.
• When the D input is HIGH (i.e. D = 1) and the EN input is HIGH, then we get Q =1 and 0
and the latch will be in set state.
• When the D input is LOW (i.e. D = 0) and EN is HIGH, then we get Q =0 and 1 and the
latch will be in set restate.
• The output Q follows the input D when EN is HIGH.

Types of Flip Flops

Flip flops are categories as follows:
• SR Flip-Flop
• D Flip-Flop
• JK Flip-Flop
• T Flip-Flop
• Master slave Flip-Flop
On the basis of edge trigger, each flip flops are of two types i.e. positive edge-triggered and negative-
triggered flip-flop.
Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah
SR Flip-Flop
This is the most common flip-flop among all. This simple flip-flop circuit has two inputs and two
outputs i.e. a set input (S), a reset input (R), outputs Q and . SR flip-flop can be constructed by using
cross-coupled NAND and NOR gates. Since flip-flops are controlled by clock transitions, therefore we
will provide a clock to our SR flip flop circuit. Here we consider a cross-coupled NAND.
CLK S R Q
0 X X Memory state
1 0 0 Memory state
1 0 1 0 1
1 1 0 1 0
1 1 1 Invalid

Figure- S-R Flip-Flop using NAND gate Figure- Truth table of S-R Flip-Flop

Figure- Symbol of S-R Flip-Flop

Working
Consider the SR NAND Flip-flop and it is clear from figure that
S ∗ S. CLK S CLK R∗ R. CLK R CLK
Case I:
Now if CLK is 0 then S*=1 and R*=1 and here S and R will be treated as don’t care conditions, then we
get Q and in memory state i.e. holding previous values.

Case II:
If CLK=1 then S*= S and R*= , now there will be 4 more cases depending upon the values of S and R.

Case II (a): S=0 and R= 0 then S* and R* both becomes 1 and we get outputs Q and in holding
memory state.
Case II (b): S=0 and R=1 then S*=1 and R*= 0 then we get Q = 0 and = 1, we get both outputs as
complement of each other.
Case II (c): S=1 and R=0 then S*=0 and R*=1 them we get Q = 1 and = 0.
Case II (d): S=1 and R=1 then S*=0 and R*=0 then we get Q and in the invalid state i.e. not used
condition.

Positive Edge Triggered SR Flip Flop

A positive edge-triggered RS flip-flop is a specific type of flip-flop that is triggered by the rising edge
(transition from low to high) of the clock signal. It has two inputs: the Set (S) input and the Reset (R)
input. The output of the flip-flop is denoted as Q and .

Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah

 CLK S R Q State
0 X X Memory state No change
0 0 Memory state No change
0 1 0 1 Reset
1 0 1 0 Set
1 1 1 1 Invalid

Figure – Positive Edge-Triggered SR flip-flop Figure – Truth table of Positive Edge-Triggered SR flip-flop

• When the clock pulse is zero, the output is stores the previous value or in memory state.
• When the Positive edge triggered clock pulse encountered, there are four possible output states exist.
If both the inputs (S and R) are zero (low), the output Q stores the previous value.
If both the inputs (S and R) are different, the output Q is in set or reset state depending on the
value of S i.e. if S = 0, the output is in Reset state else the output is in Set state.
If both the inputs (S and R) are 1 (high), the output Q is in indeterminate state or invalid
condition.

Figure – Timing Diagram of Positive Edge Triggered RS flip-flop

Negative edge triggered SR flip flop

A negative-triggered SR flip-flop is a type of flip-flop that responds to the falling edge (transition from
high to low) of the clock signal. It has two inputs: the Set (S) input and the Reset (R) input. The output
of the flip-flop is denoted as Q and .
CLK S R Q State
0 X X Hold Memory state
0 0 Hold Memory state
0 1 0 1 Reset
1 0 1 0 Set
1 1 1 1 Invalid

Figure – Negative edge-triggered SR flip-flop Figure – Truth table of Negative edge-triggered SR flip-flop

Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah

• When the clock pulse is zero, the output is stores the previous value or in memory state.
• When the Negative edge triggered clock pulse encountered, there are four possible output states
exist.
If both the inputs (S and R) are zero (low), the output Q stores the previous value.
If both the inputs (S and R) are different, the output Q is in set or reset state depending on the
value of S i.e. if S = 0, the output is in Reset state else the output is in Set state.
If both the inputs (S and R) are 1 (high), the output Q is in indeterminate state or invalid
condition.

Figure – Timing Diagram of Negative edge-triggered RS flip-flop

Drawback of the SR flip-flop

One significant drawback of the SR flip-flop is that it can enter an invalid state when both the Set (S)
and Reset (R) inputs are high simultaneously (S = 1, R = 1). This condition is known as the "forbidden"
or "indeterminate" state, and it violates the expected behavior of the flip-flop. In this state, the outputs
may oscillate or produce unpredictable results. Therefore, it is essential to avoid applying this input
combination to an SR flip-flop to ensure proper functionality.

D flip-flop
A D Flip Flop (also known as a ‘data’ or ‘delay’ flip-flop) is a type of flip flop that tracks the input,
making transitions with match those of the input D. The D stands for ‘data’; this flip-flop stores the
value that is on the data line. It can be thought of as a basic memory cell.

Figure –Logic diagram of D Flip-flop Figure – Symbol of D Flip-flop

Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah

 CLK D Q Description
0 X Q Memory state
1 0 0 1 Reset
1 1 1 0 Set
Figure – Truth table of D Flip-flop

The input of the D-flip flop directly goes to the input S and its complement goes to the input R. The D-
input is sampled throughout the existence of a CLK pulse. When the clock input is set to 1, the D input
is copied to the output Q and when the clock input is set to 0, then the flip flop switches to a clear state.

Positive Edge Triggered D Flip flop

A positive edge-triggered D flip-flop is a type of flip-flop that is triggered by the rising edge (transition
from low to high) of the clock signal. It has a single input called the Data (D) input and two outputs: the
normal output (Q) and the complement output (Q̅).

CLK D Q Description
0 X Q Memory state
0 0 1 Reset
1 1 0 Set
Figure – Positive Edge-Triggered of D Flip-flop Figure –Truth table Negative Edge-Triggered of D FF

When the clock is zero, the output hold the previous value or in memory state. When the positive edge
trigger clock pulse is encounter then the output Q copies the value of input D i.e. if D = 0 ,Q = 0 (reset
state) and if D = 1 ,Q = 1 (set state).

Figure – Timing diagram of Positive Edge-Triggered D flip flop

Negative edge triggered D Flip flop

A negative edge-triggered D flip-flop is a type of flip-flop that is triggered by the falling edge (transition
from high to low) of the clock signal. It has a single input called the Data (D) input and two outputs: the
normal output (Q) and the complement output (Q̅).

CLK D Q Description
0 X Q Memory state
0 0 1 Reset
1 1 0 Set

Figure –Negative Edge-Triggered of D Flip Flop Figure –Truth table of Negative Edge-Triggered D FF
Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah
When the clock is zero, the output hold the previous value or in memory state. When the negative edge
trigger clock pulse is encounter then the output Q copies the value of input D i.e. if D = 0 , Q = 0 (reset
state) and if D = 1 ,Q = 1 (set state).

Edge triggered JK flip flop

An edge-triggered JK flip-flop is a type of flip-flop that is triggered by the rising or falling edge of the
clock signal. The edge-triggered JK flip-flop is widely used in digital systems for various applications
such as frequency division, data storage, and state machine implementations. It has two inputs: the J
input and the K input, and two outputs: the normal output (Q) and the complement output (Q̅).

Positive Edge triggered JK flip flop

An edge-triggered JK flip-flop is a sequential logic circuit that stores one bit of information (either 0 or
1) and can be used to synchronize and control the flow of data in digital systems. It is called "JK"
because its behavior is determined by the inputs J (set) and K (reset). The flip-flop changes its state (0 to
1 or 1 to 0) based on the rising edge of clock input and the values of J and K.

Figure – Logic circuit of edge triggered JK flip flop Figure – symbol of positive edge
triggered JK flip flop

CLK J K Qn Qn+1 Description CLK J K Qn+1 Description

0 0 0 0 0 Hold
0 0 Qn Hold
0 0 1 1 (Memory state)
0 1 0 0 0 1 0 Reset state
Reset state
0 1 1 0
1 0 0 1 1 0 1 Set state
Set state
1 0 1 1
1 1 0 1 1 1 Toggle
Toggle Qn
1 1 1 0

Figure – Detailed and short Truth table of positive Edge Triggered JK flip flop

When the rising edge of the clock encounter then following conditions occur,
When J = 0 and K = 0, the output Q remains unchanged.
When J = 0 and K = 1, the output Q is reset to 0.
When J = 1 and K = 0, the output Q is set to 1.
When J = 1 and K = 1, the output Q is complemented (toggled).
When the clock signal is low, then irrespective of the value of J and K inputs, the flop-flop retains the
present state.

Timing diagram of positive edge triggered JK flip flop

Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah

 Figure – Timing diagram of Positive Edge Triggered JK flip flop

At the first rising edge of the clock, when J = 0 and K = 1, then output Q becomes 0 and it remains in
that state until next rising edge. In between, even if the input changes, the flip-flop does not responds to
the input changes.
At the second rising edge, since J = 1 and K = 0, the output of the flip-flop becomes 1. And it remains in
that state until next rising edge.
At the third rising edge, since both J and K inputs are 1, the output of the flip-flop toggles and it
becomes 0.

Negative edge triggered JK flip-flop

The negative edge triggered JK flip-flop is similar to the positive edge triggered flip-flop. But it
responds to the inputs only at the falling edge of the clock. The symbol and truth table of negative edge
triggered flip-flop is shown below.
CLK J K Qn+1 Description

0 0 Qn Hold

0 1 0 Reset state

1 0 1 Set state

1 1 Qn Toggle
Figure – Symbol and truth table of Negative Edge Triggered JK flip-flop

Race around Condition in JK Flip-Flop

In the level triggered JK Flip-Flop, when J = K =1, and the ON time of the clock is more than the
propagation delay of the JK Flip-Flop ,then because of the feedback from output to the input, the output
of the flip-flop may toggle continuously between ‘1’ and ‘0’. This condition is known as the Race
Around condition. The below diagram shows the Race around condition in the JK Flip-Flop

Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah

Drawbacks of the JK flip-flop
There are some drawbacks of the JK flip-flop:
Complexity: The JK flip-flop requires more gates and inputs compared to other flip-flops like D or T
flip-flops. It has two control inputs (J and K), which increases circuit complexity.
Race Conditions: The JK flip-flop is susceptible to race conditions, which are timing-related issues that
can occur when the inputs change close to the clock edge.
Power Consumption: Due to the complex internal structure and additional gates, the JK flip-flop
generally consumes more power compared to simpler flip-flops.
Propagation Delay: The JK flip-flop typically has higher propagation delay compared to other flip-
flops. Propagation delay refers to the time taken for the output to change after the inputs
change.

T Flip-flop
A T flip-flop (Toggle Flip-flop) is a simplified version of JK flip-flop. The T flop is obtained by
connecting the J and K inputs together. The flip-flop has one input terminal and clock input. These flip-
flops are said to be T flip-flops because of their ability to toggle the input state. Toggle flip-flops are
mostly used in counters.

Positive Edge triggered T flip Flop

The Positive Edge triggered T flip-flop changes its state (0 to 1 or 1 to 0) based on the rising edge of
clock input and the values of T.

Figure – Symbol of Positive edge triggered T Flip-flop Figure - T Flip Flop Circuit
The operation of the T flip – flop is
When the T input is LOW, then the next state of the T flip flop is same as the present state.
• T = 0 and present state = 0, then the next state = 0
• T = 0 and present state = 1, then the next state = 1
Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah
When the T input is HIGH and during the positive transition of the clock signal, the next state of the T
flip – flop is the complement of the present state.
• T = 1 and present state = 0, then the next state = 1
• T = 1 and present state = 1, then the next state = 0
CLK T Qn Qn+1 Description
0 0 0 Unchanged/hold
0 1 1 Unchanged/hold
1 0 1 Toggle
1 1 0 Toggle
Figure- Truth table of Positive edge triggered T Flip flop

In this truth table, Qn represents the present state and Qn+1 represents the next state of the output.

Negative Edge triggered T flip Flop

The Negative Edge triggered T flip-flop changes its state (1 to 0 or 0 to 1) based on the falling edge of
clock input and the values of T.

CLK T Qn Qn+1 Description

0 0 0 Unchanged/hold
0 1 1 Unchanged/hold
1 0 1 Toggle
1 1 0 Toggle
Figure – Symbol and truth table of Negative Edge Triggered T flip-flop

Master Slave J K Flip flop

The Master-Slave Flip-Flop is basically a combination of two JK flip-flops connected together in a
series configuration. Out of these, one acts as the “master” and the other as a “slave”. The output from
the master flip flop is connected to the two inputs of the slave flip flop whose output is fed back to
inputs of the master flip flop.

In addition to these two flip-flops, the circuit also includes an inverter. The inverter is connected to
clock pulse in such a way that the inverted clock pulse is given to the slave flip-flop.

Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah

 Figure – Circuit diagram of Master slave JK Flip flop

Working of a master slave flip flop –

• When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect the state of the
system. The slave flip-flop is isolated until the CP goes to 0. When the CP goes back to 0,
information is passed from the master flip-flop to the slave and output is obtained.
• Firstly the master flip flop is positive level triggered and the slave flip flop is negative level
triggered, so the master responds before the slave.
• If J = 0 and K = 1, the high output of the master goes to the K input of the slave and the clock
forces the slave to reset, thus the slave copies the master.
• If J = 1 and K = 0, the high Q output of the master goes to the J input of the slave and the
Negative transition of the clock sets the slave, thus the slave copying the master.
• If J = 1 and K = 1, it toggles on the positive transition of the clock and thus the slave toggles on
the negative transition of the clock.
• If J = 0 and K = 0, the flip flop is disabled and Q remains unchanged.

Flip-Flop Timing
Flip-flop timing refers to the characteristics and parameters that determine the behavior and performance
of a flip-flop with respect to the timing of its inputs and clock signal.

Propagation delay time

A propagation delay time is the interval of time required after an input signal has been applied for the
resulting output change to occur. Four categories of propagation delay times are important in the
operation of a flip-flop:
• Propagation delay tPLH as measured from the triggering edge of the clock pulse to the LOW-to-
HIGH transition of the output. This delay is illustrated in Figure (a).
• Propagation delay tPHL as measured from the triggering edge of the clock pulse to the HIGH-to-
LOW transition of the output. This delay is illustrated in Figure (b).

Figure – Propagation delays, clock to output

Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah
 • Propagation delay tPLH as measured from the leading edge of the preset input to the LOW-to-
HIGH transition of the output. This delay is illustrated in Figure (a) for an active-LOW preset
input.
• Propagation delay tPHL as measured from the leading edge of the clear input to the HIGH-to-
LOW transition of the output. This delay is illustrated in Figure (b) for an active-LOW clear
input.

Figure – Propagation delays, preset input to output and clear input to output

Set-up time
The set-up time (ts) is the minimum interval required for the logic levels to be maintained constantly on
the inputs (J and K, or D) prior to the triggering edge of the clock pulse in order for the levels to be
reliably clocked into the flip-flop.

Hold time
The hold time (th) is the minimum interval required for the logic levels to remain on the inputs after the
triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop.

Various Representations of Flip‐Flops

Truth table : Truth table is a tabular representation of all the combinations of values for inputs and their
corresponding outputs.
Characteristics Table: The next state of flip-flop in terms of flip-flop input and current state. The
characteristic table has the control input (D or T) as the first column, the current state as the middle
column, and the next state as the last column. It usually tells how the control bit affects the current state
to produce the next state.
Excitation Table: The flip-flop input variable as function of the current state and next state.
The excitation table has the current state as the first column, the next state as the second column, and the
control bits as the third column. Think of a state you basically have (first column), a desired state
(second column), and you need to set a control bit (third column) to get the desired state.

State Table: A state table lists all possible states of the circuit, along with the inputs and outputs
associated with each state and the next state(s) resulting from a specific input combination. It provides a
systematic representation of the circuit's behavior.

Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah

State Diagram: A state diagram is a pictorial representation of the states, inputs, and outputs of a
sequential circuit.

S R Flip flop
Truth table of S R Flip Flop is given below and with the help of this table we make the characteristics
table and the excitation table.
CLK S R Qn+1 State
0 x x Qn No Change
1 0 0 Qn No Change (Hold the previous Value)
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 1 Invalid

Characteristic Table of SR Flip-Flop:

The characteristics table of SR Flip flop is shown below. This table is observed with clock pulse always
to be high. The characteristics table provides the information about the upcoming state in response to the
specific inputs.

Qn S R Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 X
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 X
The characteristics equation can be calculated by using K-map

Excitation Table of SR Flip-Flop:

The excitation table of SR flip-flop consists of two columns for the present state (Qn) and the next state
(Qn+1) what will be the value of respective inputs S & R.
Qn Qn+1 S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
D Flip Flop
Truth table of D Flip-Flop: Characteristic Table of D Flip-Flop:
CP D Qn+1 Qn D Qn+1
0 X Qn 0 0 0
1 0 0 0 1 1
1 1 1 1 0 0
1 1 1

The characteristics equation can be calculated by using K-map

Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah

Excitation Table of D Flip-Flop:
Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1
J K Flip Flop
Truth table of JK Flip-Flop:
CP J K Qn+1 State
0 x x Qn No Change
1 0 0 Qn No Change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Toggle
Characteristic Table of JK Flip-Flop:
Qn J K Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
The characteristics equation can be calculated by K-map

Excitation Table of JK Flip-Flop:

Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
T Flip Flop
Truth table of T Flip-Flop: Characteristic Table of T Flip-Flop:
CP T Qn Qn T Qn+1
0 X Qn 0 0 0
1 0 No Change 0 1 1
1 1 Toggle 1 0 1
1 1 0
The characteristics equation can be calculated by using K-map

Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah

 ⨁
Excitation Table of T Flip-Flop:
Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0

Flip-Flops as Finite State Machine

In a sequential logic circuit the value of all the memory elements at a given time define the state of that
circuit at that time. Finite State Machine (FSM) concept offers a better alternative to truth table in
understanding progress of sequential logic with time. For a complex circuit a truth table is difficult to
read as its size becomes too large. In FSM, functional behavior of the circuit is explained using finite
number of states. State transition diagram is a very convenient tool to describe an FSM.

Figure – State Diagram of SR Flip Flop Figure –State Diagram of D Flip Flop

Figure – State Diagram of JK Flip Flop Figure – State Diagram of T Flip Flop

Flip-flop conversions
In this section, Different flip-flops can be implemented by using another type flip flop or simply say that
one flip flop is converted into another type of flip flop. There are few steps for conversion of one flip
flop into another.
Step 1: Write the truth table of the required flip-flop
Step 2: Write the excitation table of the given flip-flop
Step 3: Write the conversion table
Step 4: Find the Boolean expressions for the inputs of the given flip-flop
Step 5: Draw the circuit for implementing required flip flop using given flip-flop
Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah
Conversion of SR flip flop into D Flip Flop
Step 1: Write the truth table of the D flip-flop
D QN QN+1
0 0 0
0 1 0
1 0 1
1 1 1
Step 2: Write the excitation table of the S R flip-flop
QN QN+1 S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
Step 3: Write the conversion table
D QN QN+1 S R
0 0 0 0 X
0 1 0 0 1
1 0 1 1 0
1 1 1 X 0
Step 4: write the Boolean expressions for S and R from the conversion table using K-Maps
For S For R

Step 5: Draw the circuit for implementing D flip-flop from SR flip-flop

Conversion of SR flip flop into JK Flip Flop

The truth table of JK flip-flop Excitation table of SR flip-flop
J K QN QN+1 QN QN+1 S R
0 0 0 0 0 0 0 X
0 0 1 1 0 1 1 0
0 1 0 0 1 0 0 1
0 1 1 0 1 1 X 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah

The conversion table
J K QN QN+1 S R
0 0 0 0 0 X
0 0 1 1 X 0
0 1 0 0 0 X
0 1 1 0 0 1
1 0 0 1 1 0
1 0 1 1 X 0
1 1 0 1 1 0
1 1 1 0 0 1

The Boolean expressions for S and R from the conversion table using K-Maps
For S For R

Draw the circuit for implementing JK flip-flop using SR flip-flop

Conversion of SR flip flop into T Flip Flop

The truth table of T flip-flop The excitation table of SR flip-flop
T QN QN+1 QN QN+1 S R
0 0 0 0 0 0 X
0 1 1 0 1 1 0
1 0 1 1 0 0 1
1 1 0 1 1 X 0
The conversion table
T QN QN+1 S R
0 0 0 0 X
0 1 1 X 0
1 0 1 1 0
1 1 0 0 1
Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah
The Boolean expressions for S and R from the conversion table using K-Maps
For S For R

The circuit for implementing T flip-flop from SR flip-flop

Conversion of JK flip flop into RS Flip Flop

The truth table of SR flip-flop The excitation table of JK flip-flop
S R QN QN+1 QN QN+1 J K
0 0 0 0 0 0 0 X
0 0 1 1 0 1 1 X
0 1 0 0 1 0 X 1
0 1 1 0 1 1 X 0
1 0 0 1 The conversion table
1 0 1 1 S R QN QN+1 J K
1 1 0 X 0 0 0 0 0 X
1 1 1 X 0 0 1 1 X 0
0 1 0 0 0 X
0 1 1 0 X 1
1 0 0 1 1 X
1 0 1 1 X 0
1 1 0 X X X
1 1 1 X X X
The Boolean expressions for J and K from the conversion table using K-Maps
For J For K

The circuit for implementing SR flip-flop from JK flip-flop

Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah
Conversion of JK flip flop into D Flip Flop
The truth table of D flip-flop The excitation table of JK flip-flop
D QN QN+1 QN QN+1 J K
0 0 0 0 0 0 X
0 1 0 0 1 1 X
1 0 1 1 0 X 1
1 1 1 1 1 X 0
The conversion table
D QN QN+1 J K
0 0 0 0 X
0 1 0 X 1
1 0 1 1 X
1 1 1 X 0
The Boolean expressions for J and K from the conversion table using K-Maps
For J For K

the circuit for implementing D flip-flop from JK flip-flop

Conversion of JK flip flop into T Flip Flop

The truth table of T flip-flop The excitation table of JK flip-flop
T QN QN+1 QN QN+1 J K
0 0 0 0 0 0 X
0 1 1 0 1 1 X
1 0 1 1 0 X 1
1 1 0 1 1 X 0

Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah

 The conversion table
T QN QN+1 J K
0 0 0 0 X
0 1 1 X 0
1 0 1 1 X
1 1 0 X 1

The Boolean expressions for J and K from the conversion table using K-Maps
For J For K

The circuit for implementing T flip-flop from JK flip-flop

Conversion of D flip flop into SR Flip Flop

The truth table of SR flip-flop The excitation table of D flip-flop
S R QN QN+1
QN QN+1 D
0 0 0 0
0 0 0
0 0 1 1
0 1 1
0 1 0 0
1 0 0
0 1 1 0
1 1 1
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 X
The conversion table
S R QN QN+1 D
0 0 0 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 0 0
1 0 0 1 1
1 0 1 1 1
1 1 0 X X
1 1 1 X X

Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah

The Boolean expressions for D from the conversion table using K-Map
For D

The circuit for implementing SR flip-flop from D flip-flop

Conversion of D flip flop into JK Flip Flop

The truth table of JK flip-flop The conversion table
J K QN QN+1 J K QN QN+1 D
0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 1 1 1
0 1 0 0 0 1 0 0 0
0 1 1 0 0 1 1 0 0
1 0 0 1 1 0 0 1 1
1 0 1 1 1 0 1 1 1
1 1 0 1 1 1 0 1 1
1 1 1 0 1 1 1 0 0
The excitation table of D flip-flop
QN QN+1 D
0 0 0
0 1 1
1 0 0
1 1 1
The Boolean expressions for D from the conversion table using K-Maps
For D

Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah

The circuit for implementing JK flip-flop from D flip-flop

Conversion of D flip flop into T Flip Flop

The truth table of T flip-flop The excitation table of D flip-flop
T QN QN+1 QN QN+1 D
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 1 0 0
1 1 0 1 1 1
The conversion table
T QN QN+1 D
0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 0

The Boolean expression for D from the The circuit for implementing T flip-flop from
conversion table using K-Map D flip-flop
For D

Conversion of T flip flop into SR Flip Flop

The truth table of SR flip-flop The excitation table of T flip-flop
S R QN QN+1 QN QN+1 T
0 0 0 0 0 0 0
0 0 1 1 0 1 1
0 1 0 0 1 0 1
0 1 1 0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 X
Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah
 The conversion table
S R QN QN+1 T
0 0 0 0 0
0 0 1 1 0
0 1 0 0 0
0 1 1 0 1
1 0 0 1 1
1 0 1 1 0
1 1 0 X X
1 1 1 X X

The Boolean expression for T from the conversion table using K-Maps
For T

The circuit for implementing SR flip-flop from T flip-flop

Conversion of T flip flop into JK Flip Flop

The truth table of JK flip-flop The conversion table
J K QN QN+1 J K QN QN+1 T
0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 1 1 0
0 1 0 0 0 1 0 0 0
0 1 1 0 0 1 1 0 1
1 0 0 1 1 0 0 1 1
1 0 1 1 1 0 1 1 0
1 1 0 1 1 1 0 1 1
1 1 1 0 1 1 1 0 1

The excitation table of T flip-flop

QN QN+1 T
0 0 0
0 1 1
1 0 1
1 1 0
Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah
The Boolean expression for T from the conversion table using K-Maps
For T

The circuit for implementing JK flip-flop from T flip-flop

Conversion of T flip flop into D Flip Flop

The truth table of D flip-flop The excitation table of T flip-flop
D QN QN+1 QN QN+1 T
0 0 0 0 0 0
0 1 0 0 1 1
1 0 1 1 0 1
1 1 1 1 1 0
The conversion table
D QN QN+1 T
0 0 0 0
0 1 0 1
1 0 1 1
1 1 1 0

The Boolean expressions for T flip-flop from the conversion table using K-Maps
For T

⨁
The circuit for implementing D flip-flop from T flip-flop

Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah

Flip-flop applications
These are the various types of flip-flops being used in digital electronic circuits and the applications of
Flip-flops are as specified below.
• Counters: The Flip Flops are used in the Counter Circuits for Counting pulse or events.
• Frequency Dividers: The Flip Flops are used in Frequency Dividers to divide the frequency
of a input signal by a specific factor.
• Shift Registers: The Shift registers consist of interconnected flip-flops that shift data
serially.
• Storage Registers: The Storage Resistor uses Flip Flop to store data in binary information.
• Bounce elimination switch: The Flip Flop are used in Bounce elimination switch to
eliminate the contact bounce.
• Data storage: The Flip Flops are used in the Data Storage to store binary data temporarily or
permanently.
• Data transfer: The Flip Flops are used for data transfer in different electronic parts.
• Latch: The Latches are the Sequential circuit which uses Flip Flop for temporary storage of
data
• Registers: The Registers are mode from the array of flip flop which are used to store data
temporarily.
• Memory: The Flip Flops are the main components in the memory unit for data storage.

Digital Logic: Chapter 5: Sequential Logic Circuits By: MB Sah