Course Outcome: ENT352

Upon the completion of this course, you will

demonstrate the ability to:
1. Acquire knowledge about various NMOS, PMOS and
CMOS digital circuits and interconnects
2. Implement digital logic structure of various types
3. Estimate various performance metrics for digital circuits.
4. Analyse memory elements.
5. Analyse performance of moderately sized CMOS circuits
by using modern tools to verify the functionality, timing,
power and parasitics using schematic and/or layout
simulation for a given technology.
 Overview of MOS
• Metal-oxide semiconductor (MOS) integrated
circuits (ICs) have become the dominant technology
in the semiconductor industry
• With MOS, it is possible to have a lot of millions of
transistor on a single chip
• The main reason is that MOS ICs exceed the bipolar
transistors:
– in functional density (the number of functions performed
on a single chip),
– MOS transistors are simpler to fabricate
How can we get understand the device
behavior?
Assumptions??
DO YOU WANT TO PREFER N OVER P?
MOS transistors have three regions of
operation:
 I-V Characteristics

Linear

As shown, at low VDS, the drain current increases almost linearly with VDS, resulting in a
series of straight lines with slopes increasing with VGS. At high VDS, the drain current
saturates and becomes independent of VDS.
 nMOS and pMOS transistors
Each transistor consists of a stack of a conducting gate, an insulating layer of
silicon dioxide and a semiconductor substrate (body or bulk)

nMOS transistor pMOS transistor

Source Gate Drain
Source Gate Drain Polysilicon
Polysilicon
SiO2
SiO2

polysilicon
gate
W
n+ n+ p+ p+
tox
p bulk Si L SiO2 gate oxide n bulk Si
n+ n+ (good insulator, ox = 3.9)
p-type body

Body is typically grounded Body is typically at supply voltage

 The Threshold Voltage (VT)
• Can be defined as the voltage applied between gate and source of the
MOS transistor below which the drain to source current IDS effectively
Drops to zero.
• The threshold voltage can be modeled as

Where
Vt0 is the threshold voltage when the source is at the body potential,

øs is the surface potential and

γ is the body effect coefficient

Can you tell the output of these
circuits?
 Life is not Always Beautiful!

• Reasons?
 Short Channel Effects:
• Channel length modulation (CLM)
• Sub threshold Conduction.
• Fowler–Nordheim tunneling
• Drain Punch-through.
• Hot Electrons – Impact Ionization.
• Body Effect.
• Velocity Saturation & Mobility degradation.
 Channel length modulation
• The equation describing the MOSFET in saturation suggests
that the device acts as a current source.
-ID is constant and independent of VDS.

• The effective channel length is actually modulated by VDS.

– An increase in VDS causes the depletions region at the drain
junction to grow.
– The length of the effective channel is reduced.

• A more accurate equation describing the saturation region

must account for this channel length modulation.
• Lambda is the channel length modulation and is
generally proportional to the inverse of the channel
length.

• Channel length modulation is more pronounced in

short channel devices.

• Short channel devices are prone to velocity saturation.

– Velocity saturation occurs
 Channel length modulation
• One of several short-channel effects in MOSFET scaling, channel
length modulation (CLM) is a shortening of the length of the
inverted channel region with increase in drain bias for large drain
biases.

• The result of CLM is an increase in current with drain bias and a

__________of output resistance.
 Sub-Threshold Conduction
• Ideally at VGS < VT, ID = 0.

• The MOS device is partially conducting for gate voltages

below the threshold voltage. This is termed sub-threshold or
weak inversion conduction.

• In most digital applications the presence of sub-threshold

current is undesirable. Why?
 Fowler–Nordheim tunneling

• When the gate oxide is very thin,a current can

flow from gate to source/drain by electron
tunneling through the gate oxide.

This current is proportional to the area of the

gate of the transistor.
 Drain Punch Through
• Punch through. Punch through in a MOSFET is
an extreme case of channel length modulation
where the depletion layers around
the drain and source regions merge into a
single depletion region. The field underneath
the gate then becomes strongly dependent on
the drain-source voltage, as is
the drain current
Hot Electrons – Impact Ionization.
 Body Effect
• Vt: gate voltage necessary to invert channel
• Vt: Increases if source voltage increases
• Increase in Vt with Vs is called the body effect
 Body Effect Model
Vt  Vt 0  g  fs  Vsb  fs 
 fs = surface potential at threshold
NA
fs  2vT ln
ni
– Depends on doping level NA
– And intrinsic carrier concentration ni
 g = body effect coefficient
tox 2q si N A
g  2q si N A 
 ox Cox

CMOS VLSI Design

Effects?
 Good/Bad ‘0’ or Good/Bad ‘1’
• NMOS is good Zero Conductor.(Bad One)
• PMOS is good One Conductor. (Bad Zero)
The Threshold Voltage (VT) Revisit..
• VT is a function of number of parameters:
 First Component
• The work function difference øGC between the gate and
the channel reflects the built-in potential of the MOS
system, which consists of the p-type substrate, the thin
silicon dioxide layer, and the gate electrode. Depending
on the gate material, the work function difference is

• This first component of the threshold voltage accounts for

part of the voltage drop across the MOS system that is
built-in.
 Second Component
• Now, the externally applied gate voltage must
be changed to achieve surface inversion i.e.,
to change the surface potential.
 Third Component
• Another component of the applied gate
voltage is necessary to offset the depletion
region charge, which is due to the fixed
acceptor ions located in the depletion region
near the surface. We can calculate the
depletion region charge density at surface
inversion as
• Note that if the substrate (body) is biased at a
different voltage level than the source,
which is at ground potential (reference), then
the depletion region charge density can be
expressed as a function of the source-to-
substrate voltage VSB.
• The component that offsets the depletion
region charge is then equal to -QB/COX, where
Cox is the gate oxide capacitance per unit
area.
 Fourth Component
• Finally, we must consider the influence of a
nonideal physical phenomenon which we have
neglected until now. There always exists a fixed
positive charge density Qox at the interface
between the gate oxide and the silicon substrate,
due to impurities and/or lattice imperfections at
the interface. The gate voltage component that is
necessary to offset this positive charge at the
interface is -QOX/Cox.
• For zero substrate bias, the threshold voltage
VT is expressed as follows:

• For nonzero substrate bias:

• The generalized form of the threshold voltage can
also be written as

• Note that in this case, the threshold voltage

differs from VT0 only by an additive term. This
substrate-bias term is a simple function of the
material constants and of the source-to substrate
voltage VSB
• Thus, the most general expression of the
threshold voltage VT can be found as follows :
 Activity
1) If the width of a transistor increases, the current will
increase decrease not change
2) If the length of a transistor increases, the current will
increase decrease not change
3) If the supply voltage of a chip increases, the maximum transistor current
will
increase decrease not change
4) If the width of a transistor increases, its gate capacitance will
increase decrease not change
5) If the length of a transistor increases, its gate capacitance will
increase decrease not change
6) If the supply voltage of a chip increases, the gate capacitance of each
transistor will
increase decrease not change
 Activity
1) If the width of a transistor increases, the current will
increase decrease not change
2) If the length of a transistor increases, the current will
increase decrease not change
3) If the supply voltage of a chip increases, the maximum transistor current
will
increase decrease not change
4) If the width of a transistor increases, its gate capacitance will
increase decrease not change
5) If the length of a transistor increases, its gate capacitance will
increase decrease not change
6) If the supply voltage of a chip increases, the gate capacitance of each
transistor will
increase decrease not change
Capacitances of a MOS Transistor
 Any two conductors separated by an insulator have
capacitance
 Gate to channel capacitor is very important
 Creates channel charge necessary for operation
(intrinsic capacitance)
 Source and drain have capacitance to body (parasitic
capacitance)
 Across reverse-biased diodes
 Called diffusion capacitance because it is
associated with source/drain diffusion
 Gate Capacitance
 When the transistor is off, the channel is not
inverted
Cg = Cgb = oxWL/tox = CoxWL
 Let’s call CoxWL = C0
 When the transistor is on, the channel extends from
the source to the drain (if the transistor is
unsaturated, or to the pinchoff point otherwise)
Cg = Cgb + Cgs + Cgd
Gate Capacitance

In reality the gate overlaps source and

drain. Thus, the gate capacitance should
include not only the intrinsic capacitance
but also parasitic overlap capacitances:
Cgs(overlap) = Cox W LD
Cgs(overlap) = Cox W LD
Detailed Gate Capacitance
Capacitance Cutoff Linear Saturation
Cgb (total) C0 0 0
Cgd (total) CoxWLD C0/2 + CoxWLD CoxWLD
Cgs (total) CoxWLD C0/2 + CoxWLD 2/3 C0+ CoxWLD

Source: M-S Kang, Y. Leblebici,

CMOS Digital ICs, 3/e,
2003, McGraw-Hill
 Diffusion Capacitance
 Csb, Cdb
 Undesired capacitance (parasitic)
 Due to the reverse biased p-n
junctions between source diffusion
and body and drain diffusion and body
 Capacitance depends on area and
perimeter
 Use small diffusion nodes
 Comparable to Cg for
contacted diffusion
 ½ Cg for uncontacted
 Varies with process
Lumped representation of the MOSFET
capacitances
 The CMOS Inverter --DC Response
• DC Response: Vout vs. Vin for a gate
• Ex: Inverter
– When Vin = 0 -> Vout = VDD
– When Vin = VDD -> Vout = 0 VDD
– In between, Vout depends on
Idsp
transistor size and current Vin Vout
– By KCL, must settle such that Idsn
Idsn = |Idsp|
– We could solve equations
– But graphical solution gives more insight
 Transistor Operation
• Current depends on region of transistor
behavior
• For what Vin and Vout are nMOS and pMOS in
– Cutoff?
– Linear?
– Saturation?
 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vgsn > Vgsn >

Vdsn < Vdsn >

VDD

Idsp
Vin Vout
Idsn
 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn

VDD

Idsp
Vin Vout
Idsn
 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn

VDD
Vgsn = Vin
Idsp
Vdsn = Vout Vin Vout
Idsn
 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin - Vtn Vout > Vin - Vtn

VDD
Vgsn = Vin
Idsp
Vdsn = Vout Vin Vout
Idsn
 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vgsp < Vgsp <

Vdsp > Vdsp <

VDD

Idsp
Vin Vout
Idsn
 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp

Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp

VDD

Idsp
Vin Vout
Idsn
 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp

Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp

VDD
Vgsp = Vin - VDD Vtp < 0
Idsp
Vdsp = Vout - VDD Vin Vout
Idsn
 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
Vout > Vin - Vtp Vout < Vin - Vtp

VDD
Vgsp = Vin - VDD Vtp < 0
Idsp
Vdsp = Vout - VDD Vin Vout
Idsn
 I-V Characteristics
• Make pMOS is wider than nMOS such that bn
= bp
 Current vs. Vout, Vin

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout
 Load Line Analysis
• For a given Vin:
– Plot Idsn, Idsp vs. Vout
– Vout must
Vin0 be where |currents| are equal
Vin5 in

Vin1 Vin4
Idsn, |Idsp|
VDD
Vin2 Vin3
Idsp
Vin3 Vin2 Vin Vout
Vin4 Vin1 Idsn

VDD
Vout
 Load Line Analysis
• Vin = 0
Vin0

Idsn, |Idsp|

Vin0
VDD
Vout
 Load Line Analysis
• Vin = 0.2VDD

Vin1
Idsn, |Idsp|

Vin1
VDD
Vout
 Load Line Analysis
• Vin = 0.4VDD

Idsn, |Idsp|

Vin2
Vin2

VDD
Vout
 Load Line Analysis
• Vin = 0.6VDD

Idsn, |Idsp|

Vin3
Vin3

VDD
Vout
 Load Line Analysis
• Vin = 0.8VDD

Vin4
Idsn, |Idsp|

Vin4
VDD
Vout
 Load Line Analysis
• Vin = VDD
Vin0 Vin5

Vin1
Idsn, |Idsp|

Vin2
Vin3
Vin4
VDD
Vout
 Load Line Summary

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout
 DC Transfer Curve
• Transcribe points onto Vin vs. Vout plot

VDD
Vin0 Vin5
A B

Vout
Vin1 Vin4
C

Vin2 Vin3
Vin3 Vin2 D
Vin4 Vin1 E
0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout Vin
 Operating Regions
• Revisit transistor operating regions

Region nMOS pMOS VDD

A B
A
Vout
B C
C
D D
E
0
E Vtn VDD/2 VDD+Vtp
VDD
Vin
 Operating Regions
• Revisit transistor operating regions

Region nMOS pMOS VDD

A B
A Cutoff Linear
Vout
B Saturation Linear C
C Saturation Saturation
D Linear Saturation D
E
0
E Linear Cutoff Vtn VDD/2 VDD+Vtp
VDD
Vin
Can we get the Output Voltage
Analytically ??
 Operating Regions
– By KCL, must settle such that Idsn = |Idsp|

Regio Output Voltage

VDD
n (V0)
A B
A ?
B ? Vout
C ? C

D ?
E ?
D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin
Region A
Region B
Region C
Region D
Region E

Vo=0
• Where do you see most of the power is being
consumed? (Region: A, B, C, D…???)
• Is this inverter capable of providing analog
behavior? (Region: A, B, C, D…???)
 Beta Ratio
• If bp / bn  1, switching point will move from VDD/2
• Called skewed gate
• Other gates: collapse into equivalent inverter
VDD
bp
 10
bn
Vout 2
1
0.5
bp
 0.1
bn

0
VDD
Vin
 Noise Margins
• How much noise can a gate input see before it
does not recognize the input?
Output Characteristics Input Characteristics
VDD
Logical High
Output Range VOH Logical High
Input Range
NMH
VIH
Indeterminate
VIL Region
NML
Logical Low
Logical Low VOL Input Range
Output Range
GND