Problem Solving Session 1
Problem Solving Session 1
a. In the inverter of Fig. 1, the output low level must remain below 100 mV. If (𝑊/𝐿)2 = 3∕0.18 µm,
determine the minimum required width of M1 in case 𝐿1 = 180 nm. Find the static power
consumption of the inverter in case where 𝑉𝑂𝐿 = 100 mV.
VDD
M2
Vout
Vin
M1
b. Using the device sizes found in a., find the voltage transfer characteristic of the inverter.
e-en A
Reg!on
S!Trans!t!on F!nd!neg s
.
I
VsD M
YTr!ode
0 ,g v
ID
MpCox()[(so V!pVsD-Y2Vs]
p
.
1
=
su
,
. p = +
to
Vso-VT = 1 30
:
Id p MpCox(W)[(1 8 12 (1 8-VM)"
#'
.
= .
-
0 1 5) 1 8 Vm)
. -
-
.
0, 9
Ipn
=E unCox() (Vos-V!n)
y saturat!on
=
S ,
ar
Vos!n-TN 0, 5y
IDn
[MnCox()
=
=
(VM-V!r)
,
ID = Ipp =
upCox()[(113)(7 1 3 -
VM) -
1/2 (918-Vm] =
EMnCox(E) (Vn-0 43 ,
,
10 - 6 .
0 67 [(1 3/(113- VM)
. 1
-
0 , 5(1 , 8- Vm)) 5003 NM-0 41 = 1
1 1 69 = 1 , 3Vm-1 1 62 0 . 5 V!+18 Um
-
= SVm + 0 , 48-2, 4 um
0 , 18 v
3 5 Vn-2, 9 Vu + 0 , 41 -
8
-
.
=
Vm 0 1 647v
=
Ver!fy!ng the
operat!ng reg!on :
I
V3v] Tr!ode
The calculat!on holds.
]
-
saturat!on
un - - - - - -
-
-
'
!
Um
2. A large capacitance 𝐶𝐿 = 3 pF is needed to be driven from a minimum size inverter with an input
capacitance 𝐶𝑖𝑛 = 12 fF and propagation delay of 75 ps. In order to drive the capacitance, a two-
staged buffer as shown in Fig. 2 is introduced.
a. Assuming that the input capacitance of an inverter is proportional to its size, determine the sizes of
buffer stages that minimizes the propagation delay.
b. Add any number of stages to achieve minimum delay. How many stages would you insert? What is
the resulting propagation delay?