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Assignment 3

The document outlines an assignment focused on memory design and I/O organization, including tasks such as designing cache structures, DRAM modules, and understanding I/O techniques. It covers various concepts like write policies, DMA, and the differences between isolated and memory-mapped I/O. Additionally, it includes calculations for data transfer times using different methods.

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abdullahahmad78699
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4 views1 page

Assignment 3

The document outlines an assignment focused on memory design and I/O organization, including tasks such as designing cache structures, DRAM modules, and understanding I/O techniques. It covers various concepts like write policies, DMA, and the differences between isolated and memory-mapped I/O. Additionally, it includes calculations for data transfer times using different methods.

Uploaded by

abdullahahmad78699
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Assignment 3

Memory Design

1. Design the physical structure of an 8 KB two-way set associative cache for 32-bit
microprocessor (32-bit address bus), given the block size of 8 bytes. Show the format
of main memory address and clearly indicate the width of address lines at all
connections.
2. Using 512 X 512 X 1 DRAM cell arrays as basic component design a 256 KB (256K
X 8 bit) asynchronous DRAM module having multiplexed row and column addresses.
Using these 256 KB modules design 1 MB memory. Use multiplexers, decoders, etc.
wherever required.
3. Design a direct mapped cache structure having a capacity of 512 KB with a block size
of 16 bytes for a CPU linked to byte addressable external memory via a 32-bit address
but and a 64-bit bidirectional data bus.
4. A set associative cache consists of 64 lines, divided into four-line sets. Main memory
contains 4K blocks of 128 words each. Show the format of main memory address.
5. Why there is requirement of write policy for cache memory. Discuss various techniques
to implement write policies briefly.
6. Construct a 4K DRAM using 2K X 1 bit arrays with multiplexed ( or non-multiplexed)
addressing scheme. What is the length of the addresses?
7. How many seconds will a SDRAM, operating at 143MHz with an input-output word
size of 16 bits, will take to transfer 1144M bytes of data from the memory controller.

I/O Organization

1. What is the difference between isolated I/O and memory mapped I/O? What are the
advantages of each?
2. Define: cycle stealing and daisy chain technique.
3. What is the function of STATUS and CONTROL registers in I/O interface?
4. Explain with the help of suitable diagram how the I/O request is processed by the DMA
controller.
5. Draw the block diagram of I/O interface and briefly explain the function of each of its
components.
6. Illustrate the Interrupt I/O mode with the help of flowchart.
7. Draw the typical DMA block diagram and briefly write the steps of DMA transfer.
8. Explain and evaluate the operational differences between interrupt-driven I/O and
DMA with respect to CPU involvement, efficiency, and data transfer methods. In which
scenarios is DMA more advantageous than interrupt-driven I/O, and why?
9. A system uses DMA to transfer 50 MB of data from memory to a peripheral device at
a rate of 10 MB/s. Calculate the time required for this transfer. If the same transfer is
done using programmed I/O and the CPU handles data at 200 KB/s, how much time
would it take? Compare both approaches in terms of transfer time.

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