486 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO.

1, FEBRUARY 2007

Modified SVPWM Algorithm for Three Level VSI

With Synchronized and Symmetrical Waveforms
Abdul Rahiman Beig, Member, IEEE, G. Narayanan, Member, IEEE, and V. T. Ranganathan, Senior Member, IEEE

Abstract—The objective of the present work is to improve the ratio of to the fundamental frequency is low. Under
the output waveform of three level inverters used in high-power such circumstances, the output voltage of the inverter will be
applications, where the switching frequency is very low. This is rich in harmonics [2]–[6]. The output voltage must be synchro-
achieved by maintaining the synchronization, half-wave sym-
nized with its fundamental component in order to eliminate sub-
metry, quarter-wave symmetry, and three-phase symmetry in
the pulsewidth modulation (PWM) waveforms. The principles harmonics. Like two level sine-triangle pulsewidth modulation
of achieving synchronization and symmetries in terms of space (SPWM), in three level SPWM, with equal to the odd integer
vectors for three level inverters are presented. A novel synchro- multiple of three, the inverter output waveforms will be syn-
nized space vector pulsewidth modulation (SVPWM) algorithms chronized with half-wave symmetry (HWS), quarter-wave sym-
is proposed and verified experimentally. The experimental wave- metry (QWS), three phase symmetry (TPS) [3], [4]. The three
forms of the inverter output voltage and motor no load current level space vector pulsewidth modulation (SVPWM) algorithms
for different operating conditions of the drive are presented. The
performance measure in terms of the weighted total harmonic for high-power applications use this feature to achieve synchro-
distortion (THD) of the line voltage is computed for the linear nization and waveform symmetry [5]. In this conventional three
modulation region of the drive for the proposed algorithm and level SVPWM scheme, can take only values The
compared with that of synchronized SVPWM and synchronized major drawback of this scheme is that varies over a wide
sine-triangle pulsewidth modulation (SPWM) technique. The range with in variable speed drives.
comparative results show that consideration of synchronization In the case of conventional two level inverters, it is shown
and symmetry results in improved THD. Another significant
feature of the proposed algorithm is that the symmetry and syn- that the flexibility in selecting the space vectors results in design
chronization leads to self-balancing of the direct current (dc) bus of SVPWM sequences which generate synchronized output
capacitor voltages over every one third cycle of the fundamental. waveforms with HWS, QWS, and TPS for any odd integer
Index Terms—Harmonic distortion, induction motor drives,
values of [6]. The objective of this paper is to exploit sim-
pulsewidth modulated inverters, pulsewidth modulation. ilar features of three level space vectors and design SVPWM
sequences for three level inverter resulting in synchronized
PWM outputs waveforms with HWS, QWS, and TPS. No such
I. INTRODUCTION attempt is made in the literature in this direction and for the first
time a novel synchronized three level SVPWM algorithm with
T HREE level inverters have certain advantages over conven-
tional two level inverters [1].
• Three level inverters can synthesize double the
waveform symmetries is proposed for low-switching frequency
applications. Even though three level SVPWM is an active area
voltage levels using the devices of similar voltage rating. of research, most of the work is focussed on specific issues
Hence, the power handling capacity can be doubled. related to conventional symmetrical SVPWM algorithm like
• For a given switching frequency, three level voltage can simplifying the algorithm [7], implementation issues [8]–[11],
have double the bandwidth. reducing the switching losses [12], neutral point voltage bal-
• Three level inverters have improved total harmonic distor- ancing [13]–[18], or reducing common mode voltage [19].
tion (THD) compared to two level inverters. The computational complexity of three level SVPWM can
Because of these features, three level inverters are finding appli- be reduced to that of two level SVPWM, as shown in [7] and
cation especially in medium voltage high-power drives. is applied to conventional SVPWM algorithm. In the present
In order to reduce the switching losses, the switching fre- work, the simplified method given in [7] is further modified
quency ( ) of the high-power inverters is limited to low values so that computation of synchronized SVPWM sequences and
(350 Hz to 1 KHz). Hence, the pulse number ( ), defined as implementation on digital controller using assembly program
is simple and modular. In Section II, this modified simple ap-
proach to SVPWM is explained.
Manuscript received December 6, 2004; revised June 20, 2006. Abstract pub-
lished on the Internet November 30, 2006. This work was published in part in
The design of the three level SVPWM sequences require
the following: A. R. Beig, G. Narayanan, and V. T. Ranganathan, “Space vector different approach compared to two level SVPWM techniques
based synchronized PWM algorithm for three level voltage source inverters: as there are additional redundancies in space vectors, zero
Principles and applications to v=f drives,” Proc. 28th IEEE Int. Conf. Ind. Elec- vector is no longer the common vector for all the regions of
tron., IECON’02, pp. 1249–1254, Seville, Spain, November 9–14, 2002.
A. R. Beig is with the Department of Electrical and Electronics Engg. Na- space vector space and direct current (dc) bus balancing has to
tional Institute of Technology Suratkal Srinivasnagar, 575025, Karnataka, India be maintained. The basic principle of the space vector approach
(e-mail: [email protected]). to synchronization and symmetry and design of sequences is
G. Narayanan and V. T. Ranganathan are with the Department of Electrical
Engineering, Indian Institute of Science, Bangalore 560012, Karnataka, India.
detailed in Section III. The present work shows that by proper
(e-mail: [email protected]; [email protected]). design of SVPWM sequences it is possible to get synchro-
Digital Object Identifier 10.1109/TIE.2006.888801 nization and various waveform symmetries for any integer
0278-0046/$25.00 © 2007 IEEE

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BEIG et al.: MODIFIED SVPWM ALGORITHM FOR THREE LEVEL VSI 487

TABLE I
DIODE CLAMP INVERTER: SWITCH STATUS AND
DEFINITION OF STATE FOR POLE R

Fig. 1. Three level diode clamp inverter.

values of . The proposed PWM technique is implemented

on TMS320F240 fixed point DSP controller. The proposed
PWM technique is verified experimentally on three level diode
clamp voltage source inverter fed induction motor drive.
The implementation details and typical experimental results are
presented in Section IV.
The performance of the proposed technique is studied over
the entire linear modulation region of the drive. A comparison in
terms of the weighted THD of the output line voltage ( )
for the proposed synchronized SVPWM technique with wave-
form symmetries and conventional synchronized SVPWM tech-
nique shows that consideration of symmetry results in improved
THD. Similarly, a comparison of of proposed syn-
chronized SVPWM with waveform symmetries and synchro-
nized SPWM technique with waveform symmetries proves the
superiority of the present method over synchronized SPWM Fig. 2. Space vectors of three level inverter with sector and subsector definition.
technique. Also the variation of as a function of
is studied and this result can be used for the optimal design of
PWM technique in order to achieve minimum THD. II. SIMPLIFIED APPROACH TO SVPWM
A major requirement of three level PWM sequences is that
Fig. 1 shows the circuit diagram of a three level diode clamp
the dc bus capacitor voltages must be balanced. It is shown that
inverter. The states are defined in Table I. The space vectors
the proposed technique ensures the dc link capacitor voltage bal-
associated with the three level inverters on plane are shown
ancing over (1/3)rd cycle of the fundamental. This is an impor-
tant result because the proposed method is simple, do not re- in Fig. 2. In the space vector approach to PWM, the reference
quire any additional computation or feed back signal compared vector is sampled at regular interval . The sampled reference
to other methods presented in the literature [13]–[18]. The pro- vector is approximated by time averaging the nearest three
posed method also results in minimum common mode voltage. vectors, , , and according to (1) and (2)
Compared to the other three level SVPWM algortihms, the
present work has a unique feature that it addresses all the major (1)
issues related to the three level PWM techniques such as com- (2)
putational complexity, synchronization, THD, dc bus voltage
balancing, and common mode voltage. Hence, the proposed where , , and are the dwell times of , , and ,
SVPWM method will be suitable for high-power applications respectively.
as it eliminates subharmonics by maintaining synchronization, Unlike two level inverters, the zero vector is no longer
improves THD through various waveform symmetries, results common for all the regions. So solution to (1) and (2) involves
in balanced dc bus voltage, and low common mode voltage. solving three simultaneous equations. In order to simplify

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488 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 1, FEBRUARY 2007

TABLE II
PIVOT VECTORS AND INVERTER STATES

The vector forms the origin and its magnitude is always

zero and for a given sector this vector is similar to the zero vector
of two level inverters. The three nearest vectors can be identified
as , , and as shown in Fig. 3. Now the solution to (1)
is similar to that of two level inverters, as in (4)

(4a)
(4b)
(4c)

Thus, the computational complexity of three level inverters is

reduced to that of two level inverters. Implementation of above
method is simple as it requires only the computation of and is
explained in Section IV. With the sector definition given above,
all the sectors are symmetric and a modular approach can be
used in implementation.
Conventional SVPWM sequences will have switching se-
quences . The interval
is equally derived between pivot vectors and . The
Fig. 3. (a) Vectors of sector 1. (b) Mapping of vectors of sector 1 to fictitious pivot vectors and are defined in Table II. State is
vectors. defined as the state of obtained by switching only one phase
of the inverter from state . Similarly state is defined as
the state of obtained by switching only one phase of the
the above equations, a simple approach based on the method inverter from state . These sequences ensure that in each
given in [7] is adopted, in which the symmetry of the space sampling interval, each of the phases is switched at least once.
vectors is exploited. The space vector plane is divided in to six Also these sequences satisfy following two conditions for
sectors, each of 60 , as shown in Fig. 2. Each sector , where minimum switching frequency.
, is associated with one pivot vector and • Condition 1: Only one switch is switched during state tran-
six other vectors. The pivot vector and other six vectors sition. That is transition from state 1 to state and vice
of sector 1 are redrawn in Fig. 3(a). The vectors of the other versa is not allowed.
sectors are phase displaced by radians. All the six sectors • Condition 2: The final state of present sample will be the
exhibit symmetry. All the vectors associated with the given initial state of next sample.
sector , can be mapped to a set of seven fictitious vectors with In the next section, these SVPWM sequences are modified to
as the center as defined by (3). This is illustrated in Fig. 3(b) achieve synchronized output waveforms with HWS and TPS.
In the present method, the sector decides the angle through
which the reference vector is to be rotated to get the fictitious
reference vector whereas in the simplified method given in
[7], the offset values to be subtracted from to obtain has
to be stored in the form of lookup table or programmed accord-
ingly. This slight modification helps in developing subroutines
(3) to generate switching sequence and helps in implementing in
DSP assembly program which is clear from the implementation
The fictitious vectors are similar to those of two level inverters. details given in Section IV.

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BEIG et al.: MODIFIED SVPWM ALGORITHM FOR THREE LEVEL VSI 489

III. SPACE VECTOR APPROACH TO SYNCHRONIZATION TABLE III

AND SYMMETRY CONDITIONS OF SYNCHRONIZATION, HWS, AND
TPS IN TERMS OF POLE VOLTAGES
In this section, the principles of obtaining synchronization
and various symmetry in terms of space vectors is derived.

A. Need for Synchronization and Symmetry

• Synchronization: At low switching frequencies, it is neces-
sary to maintain perfect synchronization of inverter output
voltage with respect to its own fundamental to avoid sub-
harmonics. This is possible if and only if the PWM output
pole voltage waveform satisfies the condition given below
TABLE IV
CONDITIONS OF SYNCHRONIZATION, HWS, AND
TPS IN TERMS OF INVERTER STATES

where is any arbitrary angle measured from the refer-

ence axis. This can be achieved if the same inverter state
is switched at and and the dwell time of these
states must be equal. This demands the to be sampled
at and , which is possible only if there are inte-
gral number of samples per cycle of the fundamental.
• TPS: At low switching frequency, lower order harmonics
are dominant. The PWM sequences should be designed to and symmetry at the line and pole voltages are given in Table IV.
eliminate some of these harmonics. The three-phase sym- In Tables III and IV, the states with a prime ( ) indicate the com-
metry will ensure that all the harmonics and the funda- plementary states. Complementary state of 1 is state and vice
mental of all the three phases will be perfectly balanced. versa and complementary state of 0 is state 0 itself. The condi-
So the triplen harmonics will be cancelled from the line tions of HWS and TPS given in column 2 and 3 of Table IV,
voltage. For a phase sequence of R-Y-B, the TPS can be relate the inverter states over an interval of 60 . So the inverter
achieved if the inverter output voltages of three phases sat- states of each sector are related by (5)
isfy the following condition:

The above condition can be met if the switch position of (5)

pole at , the switch position of pole at , and
the switch position of pole at are same. For So one of the requirements of synchronization and symmetry
example, if the inverter state at is (101), then at is that, there should be integral number of samples ( ) per
the state (110) must be used and at state (011) sector and these samples should be placed at identical positions
must be used to achieve TPS and dwell time of these states in each sector. Under these conditions, the sampled reference
must be equal. voltages satisfy the conditions given in Table IV. Hence, for a
• HWS: The half wave symmetry will ensure elimination of given sample , where , the dwell times ,
even harmonics from the output voltage. In order to achieve and of nearest three vectors will be equal in all the sectors.
HWS, the pole voltage at and should have oppo-
site polarity that is B. Number of Samples per Sector, Pulse Number and
Switching Sequence
1) Odd Values of : For odd values of , there will be
samples within the sector placed at an equal distance
of and one sample on the sector boundary. Depending
on how the change of is accomplished, there are two
In order to achieve this, the switch position of a given phase possibilities.
at and must be opposite. If at the switch position • TYPE 1: All the samples except the sample on sector
of a given phase is “1,” then at it must be “ ” and boundary will have sequences
vice versa. But if the switch position of a given phase is .
“0” at , then the switch position of the same phase must The sample which falls on the sector boundary will
be “0” at . have the sequence,
The conditions of waveform symmetry for a given sample . The last state , of the th
are summarized in Table III. The necessary and sufficient con- sample of the present sector will be the starting state ,
ditions in terms of the inverter states to achieve synchronization in the first sample of the next sector. So the sample

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490 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 1, FEBRUARY 2007

will have the sequence, .

There will not be any switching from one sample to another
sample during sector change over. The pulse number is
given by .
• TYPE 2: All the samples will have sequences
.
The sequence of the last sample in a sector will always end
with state and the first sample in a sector will start with
state . This type of sequences will cause an additional
switching during sector change over. The pulse number is
given by .
2) Even Values of : For even values of , all the samples
will be within the sector placed at an equal distance of .
All the samples except and will have sequences
.
The sample and will have the sequences
and
. Fig. 4. Experimental waveforms: ch1: v (Scale:200 V/div) ch2: v
In these samples, one of the phases will be switched twice (Scale:500 V/div) ch3: i (Scale:11.1 A/div) for F = 40 Hz, N = 7,
and another phase will be clamped. The pulse number will be P = 10.
. Combining all the three cases, it can be seen that
synchronization, HWS and TPS can be achieved for any integral explained in step 1 above except that and are replace
value of . by and , respectively.
It can be seen that these sequences also exhibit the condi-
tions of QWS given in (6) in addition to the conditions of syn- 3) Computation of switching intervals , , and : From
chronization, HWS and TPS, even though the sequences are de- sector , subsector, , and , the , and can be
signed without considering conditions of QWS computed using (4).
4) Identification of switching sequence: The and will
decide the value of . A sector and subsector combination and
will uniquely define the switching sequence and this can be
(6) programmed in the form of subroutines.

where , , and are the instants at which the R, Y and This can be implemented in another way also. The switching
B phase fundamental waveforms have their positive or negative sequences of all the six subsectors of sector 1 are stored in the
peaks. So the output voltages will also have QWS. form of a look up table. Using this the switching sequence of
other sectors are computed using (5).

IV. EXPERIMENTAL IMPLEMENTATION AND RESULTS The above algorithm is implemented in TMS320F240 based
The conventional space vector modulation algorithm ex- controller. The event manager is programmed in compare
plained in Section II can be modified to incorporate the mode. Depending on the value of sector and subsector, the
conditions of synchronization and symmetry. So the modified corresponding subroutine is executed and the counters are
algorithm is as follows: loaded with proper values. Thus, the switching pulses are
generated. The exact sampling time interval is maintained
1) Identification of sector : From the normalized values of using end of period interrupt of event manager module. The
and , the sector is identified as follows. event manager module can generate six independent signals.
The complementary signals and the dead time between these
If and , then, if , then signals are generated in the external circuit. This SVPWM
, else, . algorithm is applied to open loop induction motor drive.
If and , then, if , then The experimental drive consists of a 400 V, 10 HP, three phase,
, else, . 50 Hz, induction motor powered from a 30 KVA, insulated gate
bipolar transistor (IGBT) based three phase three level diode
If and , then, if , then clamp inverter. The dc bus voltage is set at 510 V. The typical
, else, . experiential results for is shown in Fig. 4. The
If and , then, if , then harmonic spectra of , and , computed from the
, else, . experimental data is given in Fig. 5.
It can be seen from harmonic spectra of experimental wave-
2) Identification of subsectors: Map to fictitious vector forms (Fig. 5) that, the output voltage has no sub harmonics and
using the expression . From even harmonics. Hence, the modified SVPWM guaranties syn-
the and components of , determine the sub-sector. chronization and half-wave symmetry. The harmonic spectra
Determination of subsector is similar to identifying sectors as shows that the triplen harmonics which are present in phase

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BEIG et al.: MODIFIED SVPWM ALGORITHM FOR THREE LEVEL VSI 491

The drive is run at no load at different values of in the

linear modulation range (i.e., , where modulation
index, is defined as the ratio between the magnitude of
reference vector to the dc bus voltage ). In each case, the
motor current waveform is stored using high bandwidth digital
storage scope (LeCroy make, 200 MHz, 40 000 points per
channel). From this data, exactly one cycle data of the no load
current is taken. The frequency components are computed using
MATLAB-FFT function. From the harmonic components, the
of motor no load current is computed using (7) and its
variation is shown in Fig. 6.
Fig. 7 give the plot of of line voltage with respect to
for different switching frequencies. This result can be used
for the optimal selection of switching frequency to minimize
THD. The graph with * mark shows the variation of
for a given switching frequency. In this case, the is varied
from 380 to 420 Hz.
Fig. 8 shows the comparison of of the proposed
Fig. 5. Harmonic spectrum of v , v , and i at F = 40 Hz, N = 7, synchronized SVPWM with HWS and TPS and conventional
P = 10. synchronized SVPWM without HWS and TPS. In both the
cases, synchronization is maintained. The proposed synchro-
voltage are absent from line voltage and motor current. This nized SVPWM with symmetry will result in better THD.
proves that the SVPWM preserves three phase symmetry. Fig. 9 shows the comparison of of proposed syn-
chronized SVPWM and synchronized SPWM. In both the cases,
V. PERFORMANCE ANALYSIS is selected such that synchronization , HWS and TPS is main-
tained. In the case of SPWM, in order to maintain synchroniza-
The performance of the proposed synchronized SVPWM se-
tion, HWS and TPS, should be odd integral multiple of three.
quences is studied in terms of the THD of output waveforms, ef-
These results show that the proposed synchronized SVPWM se-
fect of PWM on dc bus midpoint voltage variation and common
quences result in improved THD. Since the proposed SVPWM
mode voltage. Some of these results are presented in this section. guaranties synchronization and symmetry for all integer values
of , the overall variation of switching frequency throughout
A. THD
the linear range of modulation is low compared to that of syn-
In high-power drives, the THD of the motor no load current, chronized SPWM.
, which is a function of voltage spectra and motor pa-
rameters is a suitable performance index at low switching fre- B. Self Balancing of DC Bus Capacitor Voltage
quencies [2]. is defined in (7)
In symmetrical SVPWM, in every sample the voltage imbal-
(7) ance during the interval is cancelled by the voltage imbal-
ance in interval . In addition to this, because of the synchro-
nization and symmetry considerations, the timing intervals of a
where is the RMS value of the fundamental component of
given sample will be equal in all the sectors. Hence, it can be
the motor no load current.
shown that for a given sample , the variation of dc bus mid-
Measuring experimentally is a difficult process. So
point voltage in a sector is equal but opposite to in
another quantity which is proportional to and easy to
compute, is the weighted THD of the line voltage ( ) next sector.
[6]. is defined in (8) As an example for a balanced three phase load such as three
phase induction motor load, with phase sequence R-Y-B, power
factor of and dc bus capacitor C, the dc bus mid point voltage
imbalance at interval 1 of sample 1 in sector 1, is given by
(8)

The gives the measure of as these are related

as follows:

(9)

where is the magnetizing inductance and is the total where is the peak value of the load current, is the dwell
leakage inductance. Therefore, can be used as the time of the interval 1 of sample 1 and is the dc bus midpoint
measure of . current at interval 1 of sample 1 of sector 1.

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492 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 1, FEBRUARY 2007

Fig. 6. Experimental results: I v/s F .

Fig. 8. V (%)
v/s M plot. (a) SVPWM (synchronized but no sym-
Fig. 7. V (%) v/s M plot.
metry). (b) SVPWM (synchronized with HWS and TPS).

where is the dc bus midpoint current at interval 1 of sample

Similarly dc mid point voltage imbalance at interval 1 of 1 of sector 2 From above
sample 1 in sector 2, is given by

This is true for all values of .

The dc bus capacitor voltage imbalance in one sector will be
equal and opposite to that in next sector. Hence, because of sym-
metry and synchronized approach, the dc bus capacitor voltages
are balanced over every radians. This is illustrated by the

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BEIG et al.: MODIFIED SVPWM ALGORITHM FOR THREE LEVEL VSI 493

Fig. 11. Experimental waveforms:1V at no load. (Scale: 1 V/div), F =

40 Hz, N = 7, P = 10 , V = 510 V.
Fig. 9. V (%) v/s M plot. (a) SPWM. (b) SVPWM.

Fig. 12. v at F = 40 Hz. Ch1: v (Scale: 200 V/div), Ch2: v (Scale:

Fig. 10. Simulation results: v and dc bus midpoint voltage v at no load, 200 V/div).
F = 40 Hz ,N = 7 = 10
,P ,V = 500 V .

Also the change in is limited to . The experi-

simulation result given in Fig. 10 and verified experimentally, mental waveforms of the variation of common mode voltage at
as shown in Fig. 11. This is an important result. Imbalance in dc is given in Fig. 12.
bus capacitor voltages will result in loss of HWS, thereby even
harmonics in motor, even if the sequences are designed to have
VI. CONCLUSION
HWS [13]. Perfect balancing of dc bus capacitor voltages helps
in preserving HWS and thus even harmonics in the motor are The theory of the space vector based synchronized PWM
eliminated. Compare to the other methods [13]–[18], the pro- method with HWS and TPS is explained. The experimental re-
posed SVPWM algorithm is simple, does not require any addi- sults are presented. The proposed algorithm is simple to imple-
tional feedback signal as in [13] and [14] or0 additional compu- ment on digital controllers and does not add to any computa-
tation as in [16]–[18], and neutral point voltage balance is built tional complexity. It is shown that the proposed PWM technique
in to the algorithm. will result in balanced dc link capacitor voltages. The perfor-
mance results show that the of the proposed method is
C. Common Mode Voltage better compared to that of synchronized SPWM technique and
synchronized SVPWM technique without symmetries. The ex-
The proposed SVPWM techniques make use of only V0(000) perimental waveforms show HWS and TPS for any integer value
state; therefore, the maximum value of the voltage between dc of pulse number. The absence of triplen harmonics from the
bus midpoint ( ) and motor neutral point ( ) ( ), which con- line voltage shows that the inverter output voltages have three-
tributes for the common mode voltage is limited to . phase symmetry. Even though the focus is on low switching

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494 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 1, FEBRUARY 2007

frequency applications, the proposed technique can be used for [19] H. Zhang, A. Von Jouanne, S. Dai, A. K. Wallace, and F. Wang, “Mul-
high switching frequency applications also. tilevel inverter modulation schemes to eliminate common-mode volt-
ages,” IEEE Trans. Ind. Appl., vol. 36, no. 6, pp. 1645–1653, Nov.-Dec.
2000.
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[7] J. H. Seo, C. H. Choi, and D. S. Hyun, “A new simplified space-vector group. His research interests include ac drives, multilevel inverters.
PWM method for three level inverters,” IEEE Trans. Power Electron., Dr. Beig received the Innovative Student Project Award for his Ph.D. work
vol. 16, no. 4, pp. 545–550, Jul. 2001. from the Indian National Academy of Engineering in 2005 and L&T- ISTE
[8] S. Chen and G. Joos, “Symemtrical SVPWM pattern generator using National Award for the his M.E. thesis from the Indian Society for Technical
field programmable gate array implementation,” in Proc. IEEE Appl. Education in 1998.
Power Electron. Conf., 2002, vol. 2, pp. 1004–1010.
[9] S. Wei, B. Wu, and Q. Wang, “An improved space vector PWM control
algorithm for multilevel inverters,” in Proc. Int. Power Electron. Motion
Control Conf., Aug. 14–16, 2004, vol. 3, pp. 1124–1129.
[10] C. Wang, B. K. Bose, V. Oleschuk, S. Mondal, and J. O. P. Pinto, G. Narayanan (S’99-M’01) received the B.E.
“Neural-network-based space-vector PWM of a three level inverter degree from Anna University, Madras, in 1992,
covering overmodulation region and performance evaluation on in- and the M.Tech. degree from the Indian Institute of
duction motor drive,” in Proc. IECON ’03 Conf., Nov. 2–6, 2003, vol. Technology, Kharagpur, in 1994. He received the
1, pp. 1–6. Ph.D. degree from the Indian Institute of Science,
[11] M.-C. Wong, Z.-Y. Zhao, Y.-D. Han, and L.-B. Zhao, “Three-dimen- Bangalore, in 2000.
sional pulse-width modulation technique in three level power inverters He is currently an Assistant Professor in the
for three-phase four-wired system,” IEEE Trans. Power Electron., vol. Department of Electrical Engineering, Indian Insti-
16, no. 3, pp. 418–427, May 2001. tute of Science, Bangalore. His research interests
[12] T. Bruckner and D. G. Holmes, “Optimal pulse-width modulation for include ac drives, pulsewidth modulation, multilevel
three level inverters,” IEEE Trans. Power Electron., vol. 20, no. 1, pp. inverters, and protection of power devices.
82–89, Jan. 2005. Dr. Narayanan received the Innovative Student Project Award for his Ph.D.
[13] N. Celanovic and D. Borojevic, “A comprehensive study of neutral- work from the Indian National Academy of Engineering in 2000 and the Young
point voltage balancing problem in three level neutral point clamped Scientist Award from the Indian National Science Academy in 2003.
voltage source PWM inverters,” IEEE Trans. Power Electron., vol. 15,
no. 2, pp. 242–249, Mar. 2002.
[14] K. Yamanaka, A. M. Hava, H. Kirino, Y. Tanaka, N. Koga, and T.
Kume, “A novel neutral point potential stabilization technique using V. T. Ranganathan (SM’84) received the B.E. and
the information of output current polarities and voltage vector,” IEEE M.E. degrees in electrical engineering from the In-
Trans. Ind. Appl., vol. 38, no. 6, pp. 1572–1580, Nov./Dec. 2002. dian Institute of Science (I.I.Sc.), Bangalore, and the
[15] M. Botao, L. Congwei, Z. Yang, and L. Fahai, “New SVPWM control Ph.D. degree from Concordia University, Montreal,
scheme for three-phase diode clamping multilevel inverter with bal- QC, Canada.
anced dc voltages,” in IEEE IECON 2002 Conf., vol. 1, pp. 903–907. He joined the Electrical Engineering Department,
[16] H. L. Liu, N. S. Choi, and G. H. Cho, “DSP based space vector PWM I.I.Sc., in 1984, where he is currently a Professor. His
for three level inverter with DC-link voltage balancing,” in Proc. IEEE research interests are in the area of power electronics
IECON 1991 Conf., vol. 2, pp. 197–203. and motor drives. He has published several papers in
[17] S. Busquets-Monge, S. Somavilla, J. Bordonau, and D. Boroyevich, the areas of vector control of ac drives, PWM tech-
“A novel modulation for the comprehensive neutral-point balancing niques, split phase induction motor drives, and rotor
in the three level NPC inverter with minimum output switching-fre- side control of slip ring induction motors. He is also a consultant to industry in
quency ripple,” in Proc. IEEE—PESC Conf., Jun. 20–25, 2004, vol. 6, the above areas and has participated in a number of projects.
pp. 4226–4232. Dr. Ranganathan received the Prize Paper Award of the IEEE-IAS Static
[18] J. H. Seo and C. H. Choi, “Compensation for the neutral-point poten- Power Converter Committee and the Tata Rao Prize of the Institution of Engi-
tial variation in three level space vector PWM,” in Proc. IEEE–APEC neers, India. He is a Fellow of the Institution of Engineers, India and the Indian
Conf., 2001, vol. 2, pp. 1135–1140. National Academy of Engineering.

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