IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO.

5, MAY 2008 1933

Multilevel Multiphase Space Vector PWM Algorithm

Óscar López, Member, IEEE, Jacobo Álvarez, Jesús Doval-Gandoy, Member, IEEE, and
Francisco D. Freijedo, Member, IEEE

Abstract—In the last few years, interest in multiphase con- Multilevel converter technology is based on the synthesis of a
verter technology has increased due to the benefits of using more voltage waveform from several dc voltage levels. As the number
than three phases in drive applications. Besides, multilevel con- of levels increases, the synthesized output voltage gets more
verter technology permits the achievement of high power ratings
with voltage limited devices. Multilevel multiphase technology steps and produces a waveform which approaches the reference
combines the benefits of both technologies, but new modulation more accurately. The major advantages of using multilevel
techniques must be developed in order to take advantage of inverters are [8], [9]:
multilevel multiphase converters. In this paper, a novel space
vector pulsewidth modulation (SVPWM) algorithm for multilevel 1) high voltage capability with voltage limited devices;
multiphase voltage source converters is presented. This algorithm 2) low harmonic distortion;
is the result of the two main contributions of this paper: the 3) reduced switching losses;
demonstration that a multilevel multiphase modulator can be real-
4) increased efficiency;
ized from a two-level multiphase modulator, and the development
of a new two-level multiphase SVPWM algorithm. The multiphase 5) good electromagnetic compatibility.
SVPWM algorithm presented in this paper can be applied to most
multilevel topologies; it has low computational complexity and it is Multilevel converters have been extensively studied in a
suitable for hardware implementations. Finally, the algorithm was wide variety of applications. Recent industrial applications
implemented in a low-cost field-programmable gate array and it of multilevel inverters include induction machine drives [10],
was tested in a laboratory with a real prototype using a five-level active rectifiers [11], interface of renewable energy sources to
five-phase inverter. the utility grid [12] and static synchronous compensators [13].
Index Terms—Field-programmable gate array (FPGA), mod- Recently, an initial attempt to integrate a multilevel inverter
ulation algorithm, multilevel multiphase converter, space vector with a multiphase machine was carried out which demonstrated
pulsewidth modulation (SVPWM). the advantages of combining both technologies [14].
The space vector pulsewidth modulation (SVPWM) tech-
I. I NTRODUCTION nique offers significant performance benefits and has proved
to be very popular in three-phase systems [15]. In [16], a
M OST OF the variable-speed electric drives use three-
phase machines. Nevertheless, since variable-speed ac
drives include a power electronic converter, the number of
simple SVPWM algorithm for multilevel three-phase topolo-
gies was presented. The method introduced in [17], for three-
phase inverters with neutral, was later extended to four-wire
machine phases can be higher than three. Major advantages of
topologies in [18]. Recently, in [19], a new SVPWM method
using a multiphase machine instead of a standard three-phase
for single-phase converters has been presented. With regard
one are [1], [2]:
to multilevel multiphase SVPWM, an algorithm for a neutral
1) improved reliability and increased fault tolerance; clamped five-phase inverter was proposed in [20]. However,
2) greater efficiency; it does not address the extension of the method for a higher
3) higher torque density and reduced torque pulsations; number of levels or phases or its application to other multilevel
4) lower per phase power handling requirements; topologies. In this paper, a generic algorithm to perform the
5) enhanced modularity; SVPWM for multiphase inverters is presented. This algorithm,
6) improved noise characteristics. which is valid for the typical multilevel topologies, is the result
Some recent applications of multiphase systems include high- of the two main contributions of this paper: the demonstration
torque low-speed brushless machines applied to electric vehicle that a multilevel multiphase modulator can be realized from a
propulsion [3], permanent-magnet motor drives for ship propul- two-level multiphase modulator and the development of a new
sion [4], permanent-magnet motors with low torque pulsation two-level multiphase SVPWM algorithm.
[5], and series-connected two-motor drives with a single in- Some researchers [21]–[25] have proposed multilevel modu-
verter supply [6], [7]. lation by using the two-level concept for three phase inverters.
A new method for the switching time calculation, where the
three-level space vector diagram is divided into six two-level
Manuscript received February 26, 2007; revised December 11, 2007. This space vector diagrams, is introduced in [21]. However, this
work was supported by the Spanish Ministry of Science and Technology under
Project ENE2006-02930. paper does not include the extension of the method for a number
The authors are with the Department of Electronic Technology, University of levels higher than three. In [22], a similar scheme is also pre-
of Vigo, 36310 Vigo, Spain. sented for a three-level inverter. This scheme cannot be directly
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. applied to a multilevel inverter; nevertheless the principle ex-
Digital Object Identifier 10.1109/TIE.2008.918466 plained in this paper permits making an N -level SVPWM from
0278-0046/$25.00 © 2008 IEEE

Authorized licensed use limited to: University of Obuda. Downloaded on November 16,2022 at 14:38:48 UTC from IEEE Xplore. Restrictions apply.
1934 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 5, MAY 2008

six (N − 1)-level SVPWM. Therefore, that implies that as the treatment, the new multilevel multiphase SVPWM algorithm
number of levels increases, both complexity and computation is obtained. Section III addresses the practical implementation
cost increase exponentially. In [23], the multilevel space vector of the algorithm in an FPGA. In Section IV, the implementa-
diagram is divided into all possible two-level space vector tion is verified by comparing experimental measurements with
hexagons. After that, a linear transformation is used to find the simulation results. Some experimental results are also given to
center of one of those hexagons to calculate the switching times. evaluate the real performance of the implemented modulation
In [24], a general solution is presented to adapt an existing two- algorithm. Section V includes the conclusions of this paper.
level modulator to a multilevel inverter. This technique requires
the storage of switching states with a memory requirement that
grows exponentially with the number of inverter levels. A new II. A LGORITHM D EVELOPMENT
expression for the duty cycle calculation in two-level inverters A. Algorithm Formulation
is proposed in [25]. The method is also extended to multilevel
inverters by adding an offset in the duty-cycle expression. The Since the switching states of any power converter topology
technique presented in this paper for implementing a multilevel stay at discrete states, the SVPWM is used to approximate a
modulator using a two-level modulator can be applied to any reference voltage vector Vr by means of a sequence of space
number of phases or levels. It has a very low computational vectors Sl = {Vs1 , Vs2 , . . . , Vsl } during each modulation cy-
cost, which is independent of the number of levels, and it does cle. To achieve a proper synthesis of the reference vector, each
not require lookup tables. switching vector Vsj must be applied during an interval Tj in
Most of the two-level SVPWM algorithms [26]–[30] for accordance with the following modulation law:
multiphase voltage converters use a decomposition of voltage
1

l
vectors in multiple dq planes instead of using original co- Vr = Vsj Tj (1)
ordinates in the nontransformed space. Although the decom- T j=1
position offers interesting information about producing-torque
and nonproducing-torque components of the voltage [31], the where the sum of the intervals Tj must be equal to the modula-
change of the reference frame implies additional calculations. tion period T
Besides, this representation of the switching vectors in many
different planes is complex and difficult to handle in hardware

l
implementations. Although the vector space decomposition Tj = T. (2)
approach is valid, it was shown in [32] that SVPWM in mul- j=1
tiphase converters is inherently a multidimensional problem
and that the vector selection can be formulated directly in a The reference vector summarizes the voltage reference for each
multidimensional space. The new two-level SVPWM algorithm phase of the system, whereas each switching vector summarizes
presented in this paper is formulated in the nontransformed the switching state of each phase of the converter
multidimensional space for a generic number of phases. The  T
computational cost of the proposed method is low, it does not Vr = Vr1 , Vr2 , . . . , VrP ∈ RP (3)
use trigonometric functions or lookup tables, and it is well  T
Vsj = Vsj1 , Vsj2 , . . . , VsjP ∈ RP . (4)
suited for real-time hardware implementations.
The proposed multilevel multiphase SVPWM algorithm is
Therefore, the reference vector and the switching vectors be-
the result of combining the new two-level multiphase SVPWM
long to the multidimensional space RP , where P is the number
algorithm with the introduced technique to carry out the multi-
of phases of the converter.
level modulation by using a two-level modulator. Consequently,
In most common multilevel topologies such as flying capac-
it is also valid for any number of phases, it has a low computa-
itor, diode-clamped, cascaded full-bridge or hybrid converters,
tional cost, and it is well suited for hardware implementations.
the output level of every phase Vs is an integer multiple of a
Moreover, it can be used with a wide variety of multilevel
fixed voltage step Vdc [9], [33]
topologies with any number of levels.
The multilevel multiphase SVPWM algorithm was im- Vs = nVdc , n ∈ Z. (5)
plemented for a five-level five-phase inverter in a low-cost
field-programmable gate array (FPGA). The model of the Therefore, vectors and switching times can be normalized by
proposed hardware implementation was verified by simulation using the voltage step and the switching period, respectively, to
with Simulink. Finally, the real performance of the modulator nondimensionalize (1) and (2)
was evaluated in the laboratory using a cascaded full-bridge
inverter supplying an inductive and resistive load. Vr
This paper is organized as follows. Section II describes the vr = ∈ RP (6)
Vdc
mathematical justification of the SVPWM algorithm in depth.
Vsj
This includes the problem formulation, the demonstration of vsj = ∈ ZP (7)
multilevel modulation in multiphase systems by using the two- Vdc
level concept and the development of the new two-level mul- Tj
tj = . (8)
tiphase SVPWM algorithm. Additionally, from mathematical T

Authorized licensed use limited to: University of Obuda. Downloaded on November 16,2022 at 14:38:48 UTC from IEEE Xplore. Restrictions apply.
LÓPEZ et al.: MULTILEVEL MULTIPHASE SPACE VECTOR PWM ALGORITHM 1935

It is important to remark that new normalized switching vec-

tors vsj now belong to the multidimensional space of integer
numbers ZP . If the above expressions are substituted in (1) and
(2), the modulation law can be rewritten in terms of the new
normalized variables as

l
vr = vsj tj (9)
j=1
Fig. 1. Example of decomposition in the 2-D problem.


l
tj = 1. (10)
If those vectors are expressed as
j=1
 T
If the reference and the switching normalized vectors are vi = vi 1 , vi 2 , . . . , vi P (16)
expressed as follows:  T
vf = vf 1 , vf 2 , . . . , vf P (17)
 T
vr = vr 1 , vr 2 , . . . , vr P (11)  T
vdj = vd 1j , vd 2j , . . . , vd P
j (18)
 T
vsj = vsj 1 , vsj 2 , . . . , vsj P (12)
and if (15) is substituted in (13), the new expression for the
then (9) and (10) can be rewritten in matrix format as modulation law is obtained
   1       1 1 ... 1  
1 1 ... 1   1 0
t t
 vr 1   vs 11 vs 12 ... vs 1l  1  vr   vi   vd 1 vd 2 . . . vd 1l  1
1 1 1 1

 2   2   t2   2  2  2 2   t2 
 vr  =  vs 1 vs 22 ... vs 2l  . .  vr = vi + vd 1 vd 2 . . . vd l   .  . (19)
2

 .   .  .  (13)  .   .   . ..   . 
 ..   . .. .. ..  .  ..   ..   . .. ..
.  .
. . . . . . .
tl tl
vr P vs P vs P ... vs P vr P vi P vd P1 vd P2 . . . vd Pl
1 2 l

The above system of linear equations constitutes the modula- Finally, if (14) is written as
tion law, which must be solved by the multilevel multiphase      1 
SVPWM algorithm. The problem solving includes three main 1 0
 vr 1   vi 1   vf 1 
steps:  2   2   2 
 vr  =  vi  +  vf  (20)
1) searching a set of integer coefficients for the matrix that  .   .   . 
 ..   ..   . 
permits solving the linear system; .
2) solving the system of linear equations to calculate the vr P vi P vf P
switching times;
3) extracting the switching vector sequence from the coeffi- and if (19) and (20) are compared, the following relationship
cient matrix. between the fractional part of the reference and the displaced
switching vectors is obtained:
The multilevel multiphase SVPWM problem can be simpli-
fied if it is decomposed into the sum of a displacement plus a  1   1 
1 ... 1  
two-level SVPWM problem with the same number of phases. t
 vf 1   vd 11 vd 12 ... vd 1l  1
 2   2   t2 
 vf  =  vd 1 vd 22 ... vd 2l  . . (21)
 .   .  . 
B. Algorithm Decomposition  .   . .. ..
.
..  .
. . . .
tl
The reference vector can be decomposed into the sum of its vf P vd P
1 vd P
2 ... vd P
l
integer and fractional parts
This new system of linear equations presents the same form
v r = vi + v f , vi = integ(vr ) ∈ Z . P
(14) as the general modulation law (13). However, in this case, the
components of vector vf are bounded in the interval [0, 1).
Components of the new vector vi are integer numbers, and Therefore, only the subset of displaced vectors with compo-
therefore it belongs to the same space ZP of the switching nents zero or one is enough to carry out the reference approxi-
vectors and it could be directly synthesized with one of them. mation. Consequently, this new equation represents a two-level
The fractional part vr still belongs to the space RP and it cannot modulator where the reference vector is vf and the array of
be directly synthesized by means of a single switching vector. switching vectors are the displaced set of switching vectors vdj .
It has to be approximated with a sequence of switching vectors. Switching times are the same in the multilevel and the two-level
Besides, a new set of switching vectors is obtained by dis- modulators. Fig. 1 shows a 2-D example of the decomposition
placing all switching vectors the distance given by vi where vector vi coincides with a switching vector and the
subset {[0, 0], [1, 0], [0, 1], [1, 1]} of displaced vectors is enough
vdj = vsj − vi . (15) to synthesize the fractional part of the reference vf .

Authorized licensed use limited to: University of Obuda. Downloaded on November 16,2022 at 14:38:48 UTC from IEEE Xplore. Restrictions apply.
1936 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 5, MAY 2008

where

1 > v̂f 1 ≥ · · · ≥ v̂f k−1 ≥ v̂f k ≥ · · · ≥ v̂f P ≥ 0 (26)

and multiplying both sides of (24) by this permutation matrix

P, we obtain the following equation:

1
= D̂t (27)
v̂f
Fig. 2. Block diagram of the multilevel multiphase SVPWM.
where
In summary, (19) demonstrates that a multilevel multiphase
D̂ = PD. (28)
modulator can be realized from a displacement plus a two-level
modulator with the same number of phases. Fig. 2 shows a One coefficient matrix D̂ with adjacent consecutive columns
block diagram of the proposed technique. that makes this new system of linear equations exactly deter-
mined is the following upper triangular matrix:
C. Two-Level Multiphase SVPWM Algorithm  
1 1 1 ... 1
Once the multilevel problem has been decomposed, the two-  1 1 ... 1
 .
level modulation law (21) has to be solved. To obtain an exactly  .. ..
. .. 
D̂ =  . . (29)
determined system of linear equations, the coefficient matrix of  .. 
 . 1 
that modulation law must be a square matrix. Hence, the length
0 1
of the switching vector sequence Sl must be
As it will be shown below, the switching times obtained with
l =P +1 (22) this coefficient matrix are always positive.
A permutation matrix is an orthogonal matrix so P is invert-
and the particular linear system, which has to be solved, is
ible and
 1   1 
1 ... 1  
t1 P−1 = PT . (30)
 vf 1    vd 1 vd 2 . . . vd P +1 
1 1 1

 2   v 2 v 2 . . . v 2   t2 
 vf  =  d 1 d2 d P +1   .  . (23)
 .   . ..   .. 
Therefore, the coefficient matrix D of the two-level modulation
 .   . .. ..
. . . . .  t law can be obtained by solving (28) as
P +1
vf P vd P1 v d2
P
. . . v P
d P +1
D = PT D̂. (31)
The objective of the two-level modulation algorithm is to find a
switching vector sequence, that is, the coefficient matrix of the The permutation matrix P applies a set of elementary row-
system (23) should be filled with zeros and ones, thus allowing switching transformations to the column vector vf . In the same
a subsequent system solution. Moreover, the coefficient selec- manner, the inverse set of elementary row-switching transfor-
tion must be carried out taking into account that the switching mations is applied to the matrix D̂ by the matrix PT and,
times must be always positive after the system solution. consequently, the number of ones and zeros in each column
There are many different possibilities to fill the coefficient does not change. Hence, the switching number is minimized
matrix. Nevertheless, the whole power system performance because consecutive vectors of the sequence are still adjacent
depends on the method employed for calculating the coefficient after the transformation.
matrix. In this way, switching losses are minimized if coeffi- Due to the fact that the solution t is the same for both linear
cients are selected in such a way that consecutive switching systems, (24) and (27), it can be calculated by using either of
vectors of the switching sequence are adjacent. In other words, them. The second option seems the best choice because, in this
only one coefficient is different in two consecutive matrix case, the solution is trivial as shown below
columns. One possible method for calculating such a matrix is 
 1 − v̂f ,
 1
if j = 1
detailed below. j−1
Equation (23) can be written in a shorter form as tj = v̂f − v̂f j , if 2 ≤ j ≤ P (32)

 v̂ P ,
f if j = P + 1.
1
= Dt. (24) All intervals calculated by means of the above expression will
vf
always be positive numbers because the coordinates of the
Finding a permutation matrix P that puts the elements of the vector v̂f obey (26).
reference vector vf in descending order In summary, matrix D permits solving the two-level mod-
ulation law getting positive switching times and minimizing
1 1 switching number. The two-level switching sequence can be
P = (25)
vf v̂f directly extracted from the columns of that matrix. Fig. 3

Authorized licensed use limited to: University of Obuda. Downloaded on November 16,2022 at 14:38:48 UTC from IEEE Xplore. Restrictions apply.
LÓPEZ et al.: MULTILEVEL MULTIPHASE SPACE VECTOR PWM ALGORITHM 1937

Fig. 3. Block diagram of the two-level multiphase SVPWM.

Fig. 5. Five-level five-phase cascaded full-bridge inverter.

the expression (23). The final switching vectors vsj must be

calculated by adding the integer part of the reference vi to the
displaced switching vectors vdj according to expression (15).
The time corresponding to each switching vector is calculated
directly from components of v̂f by using (32). Finally, trigger
signals have to be generated from the switching vectors and
the switching times. The relationship between switching states
and the particular trigger signals of transistors depends on the
multilevel topology.
The simplicity of the algorithm is here shown by means of
an example in which the steps of the previous flow chart are
followed. Let us consider a multiphase drive where the voltage
reference for each phase k is purely sinusoidal
 
k−1
Vr k = A sin wt + 2π , k = 1, . . . , P. (33)
P

If a voltage amplitude A = 32 V and a speed w = 2π 50 rd/s

is considered, the instantaneous reference for a five-phase drive
when t = 3.51 ms is

Fig. 4. Algorithm flow chart. Vr = [28.6, 22.6, −14.6, −31.6, −5.0]T V. (34)

shows the block diagram of the proposed two-level multiphase If (22) is taken into account, the switching sequence will
SVPWM. have six switching vectors: vs1 , vs2 , vs3 , vs4 , vs5 , and vs6 .
From (6), if voltage step of the converter is Vdc = 20 V, then
D. Multilevel Multiphase SVPWM Algorithm normalized voltage reference is

The proposed multilevel multiphase PWM algorithm is de- Vr

rived from the previous mathematical treatment. The steps of vr = = [1.43, 1.13, −0.73, −1.58, −0.25]T . (35)
Vdc
this algorithm are summarized in the flow chart in Fig. 4.
First, the normalized reference vr must be calculated from By means of (14), this vector is decomposed into an integer and
the reference voltage vector using the expression (7). Second, a fractional part
the normalized reference has to be decomposed into the sum
of its integer part vi and its fractional part vf by using the vi = integ(vr ) = [1, 1, −1, −2, −1]T (36)
expression in (14). After that, the elements of the fractional
part of the reference have to be sorted out in descending order vf = vr − vi = [0.43, 0.13, 0.27, 0.42, 0.75]T . (37)
to obtain the vector vf . Information about the tasks done in
the sorting process (summarized in the permutation matrix If the elements of the vector vf are sorted out in descending
P) will be used to rearrange the rows of the matrix D̂ to order, the following vector is obtained:
obtain the matrix D. The next step is to extract the displaced
switching vectors vdj from the matrix D by taking into account v̂f = [0.75, 0.43, 0.42, 0.27, 0.13]T . (38)

Authorized licensed use limited to: University of Obuda. Downloaded on November 16,2022 at 14:38:48 UTC from IEEE Xplore. Restrictions apply.
1938 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 5, MAY 2008

Fig. 6. Simulink model of the hardware implementation of the SVPWM algorithm.

In accordance with (25), the permutation matrix that carries out TABLE I
RESOURCES SUMMARY
the above sorting operation is
 
1 0 0 0 0 0
0 0 0 0 0 1
 
0 1 0 0 0 0
P= . (39)
0 0 0 0 1 0
 
0 0 0 1 0 0
0 0 1 0 0 0

The coefficient matrix D is calculated using the expression in

(31) as
 
1 1 1 1 1 1
0 0 1 1 1 1 From (15), the final switching sequence can be calculated by
 
0 0 0 0 0 1 adding the shifting vector vi to those vectors
D = PT D̂ =  . (40)
0 0 0 0 1 1
 
0 0 0 1 1 1 vs1 = vi + vd1 = [1, 1, −1, −2, −1]T
0 1 1 1 1 1
vs2 = vi + vd2 = [1, 1, −1, −2, 0]T
The displaced switching vectors can be extracted from this
matrix by means of the expression in (23) vs3 = vi + vd3 = [2, 1, −1, −2, 0]T
vd1 = [0, 0, 0, 0, 0]T vs4 = vi + vd4 = [2, 1, −1, −1, 0]T
T
vd2 = [0, 0, 0, 0, 1]
vs5 = vi + vd5 = [2, 1, 0, −1, 0]T
vd3 = [1, 0, 0, 0, 1]T
vd4 = [1, 0, 0, 1, 1]T vs6 = vi + vd6 = [2, 2, 0, −1, 0]T . (42)
vd5 = [1, 0, 1, 1, 1]T
As expected, consecutive vectors of the sequence are adjacent.
vd6 = [1, 1, 1, 1, 1]T . (41) Therefore, the number of switchings is minimized.

Authorized licensed use limited to: University of Obuda. Downloaded on November 16,2022 at 14:38:48 UTC from IEEE Xplore. Restrictions apply.
LÓPEZ et al.: MULTILEVEL MULTIPHASE SPACE VECTOR PWM ALGORITHM 1939

If the modulation index m is defined as the ratio of the peak

fundamental of the output voltage to the dc voltage step

Vfund
m= (44)
Vdc
and if harmonic injection is not considered, the modulation
index has a range of

N −1
0≤m≤ . (45)
2

III. A LGORITHM H ARDWARE I MPLEMENTATION

The Digilent S3 board was used to implement the new
SVPWM algorithm for the five-level five-phase cascaded full
bridge inverter in Fig. 5. This board hosts a XC3S200 FPGA
from Xilinx which has 4.320 logic cells each constituted by
two 16 × 1 lookup tables and two flip-flops. Before the VHDL
description was carried out, the model of the hardware imple-
mentation was first tested by simulation using the Simulink
model in Fig. 6. The algorithm implementation follows the
flow chart in Fig. 4. The integer part of the reference vi is
calculated by the block Data Type Conversion. The fractional
Fig. 7. Experimental test setup. (a) Diagram. (b) Photograph.
part of the reference vf feeds the block SVPWM 2L 5P. This
Finally, the switching times are calculated from the ordered block is a two-level five-phase modulator that provides the
reference vector v̂f by means of the equation in (32) displaced switching vectors vdj and the switching times t.
Switching vectors vsj that form the final switching sequence
t1 = 1 − v̂f a = 0.25 are calculated by adding the integer part of the reference to each
displaced switching vector. Switching times are simply those
t2 = v̂f a − v̂f b = 0.32 ones provided by the two-level modulator block.
t3 = v̂f b − v̂f c = 0.01 Although the matrix approximation of the two-level problem
is useful for the algorithm demonstration, it is inefficient in the
t4 = v̂f c − v̂f d = 0.15
hardware implementation to calculate the permutation matrix
t5 = v̂f d − v̂f e = 0.14 and the matrix operations. Therefore, the P calculation and the
t6 = v̂f e = 0.13. (43) operations made with it were replaced by sorting algorithms
that provide the same result. In addition, the first row of matri-
ces D̂ and D, which are also useful in the algorithm demonstra-
tion, was not taken into account in the implementation because
E. Algorithm Features
these rows are always constant and they are not needed for
The computational cost of the presented SVPWM algorithm extracting the switching vectors vd . The implementation of the
is low and it is independent of the number of levels. However, it block SVPWM 2L 5P is detailed at the bottom of Fig. 6 where the
grows slightly with the number of phases because the vector vf block Sort calculates the ordered vector v̂f and the vector of
includes more components which must be sorted out. Besides, indices Idx that summarizes the permutations carried out in the
lookup tables, trigonometric functions or memories to store sorting process of vf . The vector v̂f is required to calculate
predefined switching sequences are not needed. Hence, the the switching times. The indices Idx are used by the block
algorithm is well suited for real-time implementation in low- Sort (inverse) to select the rows of the matrix D̂ (without
cost devices. the first row) provided by the block Triangular matrix. The
Several previous two-level multiphase SVPWM algorithms output of the Selector block is the two-level switching vector
only use a subset of the space vectors [34] for practical reasons sequence.
because of the high number (2P ) of available space vectors in Finally, the algorithm was described in VHDL by following
multiphase systems. Nevertheless, in the proposed modulation the block diagram of Simulink. An extra block was added
technique, even with the higher number (N P ) of available to translate the switching vectors into the trigger signals for
space vectors in multilevel multiphase converters, all space controlling the five-level cascaded full-bridge inverter. Table I
vectors are handled by the algorithm without discarding any shows the summary of resources used by the implementation.
of them. In addition, the provided switching vector sequence is It is important to remark that block RAMs and multipliers
so that it minimizes the number of switchings. Hence, no extra available in the FPGA were not used because the algorithm does
effort is needed to achieve this significant goal. not need data storage or multiplication operations.

Authorized licensed use limited to: University of Obuda. Downloaded on November 16,2022 at 14:38:48 UTC from IEEE Xplore. Restrictions apply.
1940 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 5, MAY 2008

Fig. 8. Comparison of experimental measurements with simulation results.

IV. E XPERIMENTAL R ESULTS

tion results with experimental measurements. A low switching
The SVPWM algorithm was tested by using a low-power frequency (2 kHz) was selected to make the comparison easier.
laboratory prototype. Fig. 7 shows the block diagram and a To observe the behavior of the modulator with a generic input, a
photograph of the experimental setup that includes the FPGA, 50 Hz unbalanced reference with a fifth harmonic was consid-
a dSPACE platform, the inverter and the load. The dSPACE ered. Fig. 8 shows a good agreement between the simulation
DS1103 PPC Controller Board provides the reference vectors to model and the experimental setup. Measurements of voltage
the FPGA. The trigger signals generated by the FPGA control across load resistances and inverter output are very similar to
the transistors of the multilevel inverter. The five-level five- simulation results, except for some lost switching pulses due
phase cascaded full-bridge inverter shown in Fig. 5, with 3125 to the dead time included in trigger signals which was not
different switching states, was used in the experiments. The considered in the simulation model. To test the performance of
dc source voltage of all full-bridge cells is 20 V; therefore the the proposed SVPWM algorithm, the case of sinusoidal output
inverter voltage step Vdc is 20 V as well. A 100 Ω resistive load voltage with harmonic injection, typically used in concentrated
with a series connected 15 mH inductance was used in tests. winding ac machines for torque enhancement, was considered.
The simulation model of the experimental setup was done in In all the tests made, the voltage reference had a 50 Hz
Simulink and it includes the algorithm implementation previ- fundamental frequency and the output switching frequency was
ously shown in Fig. 6. The inverter and the load were modeled 10 kHz. Four cases were considered in tests: two cases with
using the SimPowerSystem toolbox. Fig. 8 compares simula- purely sinusoidal output voltage with normalized amplitudes

Authorized licensed use limited to: University of Obuda. Downloaded on November 16,2022 at 14:38:48 UTC from IEEE Xplore. Restrictions apply.
LÓPEZ et al.: MULTILEVEL MULTIPHASE SPACE VECTOR PWM ALGORITHM 1941

Fig. 10. Trajectories of the voltage and the current vectors in stationary dq
axes with m1 = 1.8 and m3 = 0. (a) Inverter output voltage. (b) Output
current.

cases of Fig. 9(b) and (d), the amplitude of the third harmonic
is nearly the sixth part of the fundamental, and the high THD
obtained corresponds to the injected third harmonic.
Fig. 10 shows the trajectories of the inverter output voltage
and the load current vectors in stationary dq frames [28] with a
balanced sinusoidal reference. Both vectors move, at constant
speed, along a circular trajectory in the dq1 plane. No third
harmonic was injected; hence, as expected, vectors in the dq3
plane stay close to the origin.

V. C ONCLUSION
In this paper, a new multilevel multiphase SVPWM algo-
rithm is presented. This algorithm is based on a displacement
Fig. 9. Phase a experimental results. Ch1: inverter output voltage; Ch2: fil-
tered inverter output voltage; Ch3: phase current. (a) m1 = 1.80, m3 = 0.00. plus a two-level multiphase SVPWM modulator. It is valid
(b) m1 = 1.80, m3 = 0.30. (c) m1 = 0.80, m3 = 0.00. (d) m1 = 0.80, for any number of phases or levels and it can be used with
m3 = 0.13. the standard multilevel topologies. The presented modulation
technique handles all switching states of the inverter and it
m1 = 1.8 and m1 = 0.8 and two additional cases where a third provides a sorted switching vector sequence that minimizes the
harmonic with magnitude m3 = m1 /6 has been injected. number of switchings. In addition, the proposed SVPWM al-
Fig. 9 shows the inverter voltage and phase current wave- gorithm proves suitable for real-time implementation due to its
forms, besides the low-order voltage harmonics of the inverter low computational complexity. Finally, a five-level five-phase
output. The first channel of the oscilloscope shows the inver- version was implemented in a low-cost FPGA and successfully
ter output waveform, the second channel shows the filtered tested by using a laboratory prototype.
inverter output waveform, and the third one shows the phase
current. In Fig. 9(a) and (b), the modulation index is high and R EFERENCES
the modulation algorithm takes advantage of all five levels of [1] G. K. Singh, “Multi-phase induction machine drive research—A survey,”
the inverter. Nevertheless, in Fig. 9(c) and (d), the modulation Electr. Power Syst. Res., vol. 61, no. 2, pp. 139–147, Mar. 28, 2002.
index is low and the output voltage is a three-level waveform. In [2] J. Apsley, S. Williamson, A. Smith, and M. Barnes, “Induction mo-
tor performance as a function of phase number,” Proc. Inst. Electr.
Fig. 9(a) and (c), with purely sinusoidal output when the modu- Eng.—Electric Power Applications, vol. 153, no. 6, pp. 898–904,
lation index is high, the low-order harmonics are negligible and Nov. 2006.
the total harmonic distortion (THD) is 3.8%. If the modulation [3] M. Simoes and J. Petronio Vieira, “A high-torque low-speed mul-
tiphase brushless machine—A perspective application for electric
index is low, then the low-order harmonics grow because of the vehicles,” IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 1154–1164,
three-level output and the THD increases up to 6.4%. In the Oct. 2002.

Authorized licensed use limited to: University of Obuda. Downloaded on November 16,2022 at 14:38:48 UTC from IEEE Xplore. Restrictions apply.
1942 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 5, MAY 2008

[4] L. Parsa and H. Toliyat, “Five-phase permanent magnet motor drives for [27] S. Xue and X. Wen, “Simulation analysis of two novel multi-
ship propulsion applications,” in Proc. IEEE Elect. Ship Technol. Symp., phase SVPWM strategies,” in Proc. IEEE ICIT, Dec. 14–17, 2005,
Jul. 25–27, 2005, pp. 371–378. pp. 1337–1342.
[5] L. Parsa, H. A. Toliyat, and A. Goodarzi, “Five-phase interior permanent- [28] H.-M. Ryu, J.-H. Kim, and S.-K. Sul, “Analysis of multiphase space
magnet motors with low torque pulsation,” IEEE Trans. Ind. Appl., vector pulse-width modulation based on multiple d − q spaces concept,”
vol. 43, no. 1, pp. 40–46, Jan./Feb. 2007. IEEE Trans. Power Electron., vol. 20, no. 6, pp. 1364–1371, Nov. 2005.
[6] E. Levi, M. Jones, S. N. Vukosavic, A. Iqbal, and H. A. Toliyat, “Mod- [29] S. Xue, X. Wen, and Z. Feng, “Multiphase permanent magnet motor drive
eling, control, and experimental investigation of a five-phase series- system based on a novel multiphase SVPWM,” in Proc. CES/IEEE 5th
connected two-motor drive with single inverter supply,” IEEE Trans. Ind. IPEMC, Aug. 2006, vol. 1, pp. 1–5.
Electron., vol. 54, no. 3, pp. 1504–1516, Jun. 2007. [30] G. Grandi, G. Serra, and A. Tani, “Space vector modulation of a seven-
[7] K. Mohapatra, R. Kanchan, M. Baiju, P. Tekwani, and K. Gopakumar, phase voltage source inverter,” in Proc. Int. SPEEDAM, May 23–26, 2006,
“Independent field-oriented control of two split-phase induction motors pp. 1149–1156.
from a single six-phase inverter,” IEEE Trans. Ind. Electron., vol. 52, [31] E. Levi, M. Jones, S. Vukosavic, and H. Toliyat, “Operating principles
no. 5, pp. 1372–1382, Oct. 2005. of a novel multiphase multimotor vector-controlled drive,” IEEE Trans.
[8] R. Teodorescu, F. Blaabjerg, J. K. Pedersen, E. Cengelci, S. U. Sulstijo, Energy Convers., vol. 19, no. 3, pp. 508–517, Sep. 2004.
B. O. Woo, and P. Enjeti, “Multilevel converters—A survey,” in Proc. [32] M. J. Duran and E. Levi, “Multi-dimensional approach to multi-phase
EPE, 1999, pp. 408–418. space vector pulse width modulation,” in Proc. 33rd Annu. Conf. IEEE
[9] J. Rodriguez, J. Lai, and F. Z. Peng, “Multilevel inverters: A survey IECON, Paris, France, Nov. 7–10, 2006, pp. 2103–2108.
of topologies, controls, and applications,” IEEE Trans. Ind. Electron., [33] K. Corzine and S. Lu, “Comparison of hybrid propulsion drive schemes,”
vol. 49, no. 4, pp. 724–738, Aug. 2002. in Proc. IEEE Elect. Ship Technol. Symp., Jul. 25–27, 2005, pp. 355–362.
[10] P. Correa, M. Pacas, and J. Rodriguez, “Predictive torque control for [34] A. Iqbal and E. Levi, “Space vector modulation schemes for a five-
inverter-fed induction machines,” IEEE Trans. Ind. Electron., vol. 54, phase voltage source inverter,” in Proc. Eur. Conf. Power Elect. Appl.,
no. 2, pp. 1073–1079, Apr. 2007. Sep. 11–14, 2005, p. 12.
[11] J. Rodriguez, J. Dixon, J. Espinoza, J. Pontt, and P. Lezana, “PWM re-
generative rectifiers: State of the art,” IEEE Trans. Ind. Electron., vol. 52,
no. 1, pp. 5–22, Feb. 2005.
[12] J. Carrasco, L. Franquelo, J. Bialasiewicz, E. Galvan, R. Portillo Guisado, Óscar López (M’05) was born in Spain, in 1975.
M. Prats, J. Leon, and N. Moreno-Alfonso, “Power-electronic systems for He received the M.Sc. degree from the University
the grid integration of renewable energy sources: A survey,” IEEE Trans. of Vigo, Vigo, Spain, in 2001, where he is currently
Ind. Electron., vol. 53, no. 4, pp. 1002–1016, Jun. 2006. working toward the Ph.D. degree with the Depart-
[13] Y. Cheng, C. Qian, M. Crow, S. Pekarek, and S. Atcitty, “A comparison of ment of Electronic Technology, since 2004.
diode-clamped and cascaded multilevel converters for a STATCOM with He is currently an Assistant Professor with the
energy storage,” IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 1512–1521, University of Vigo. His research interest is in the
Oct. 2006. areas of power switching converters technology.
[14] S. Lu and K. Corzine, “Multilevel multi-phase propulsion drives,” in Proc.
IEEE Elect. Ship Technol. Symp., Jul. 25–27, 2005, pp. 363–370.
[15] S. R. Bowes and D. Holliday, “Optimal regular-sampled PWM inverter
control techniques,” IEEE Trans. Ind. Electron., vol. 54, no. 3, pp. 1547–
1559, Jun. 2007.
[16] N. Celanovic and D. Boroyevich, “A fast space-vector modulation al- Jacobo Álvarez was born in Vigo, Spain, in 1967.
gorithm for multilevel three-phase converters,” IEEE Trans. Ind. Appl., He received the Ph.D. degree in electronics from the
vol. 37, no. 2, pp. 637–641, Mar. 2001. University of Vigo, Vigo, in 1995.
[17] M. M. Prats, L. G. Franquelo, J. I. Leon, R. Portillo, E. Galvan, and In 1991, he was an Engineer at the University
J. M. Carrasco, “A 3-D space vector modulation generalized algorithm for of Vigo and has been a Full Professor with the
multilevel converters,” IEEE Power Electron. Lett., vol. 1, no. 4, pp. 110– University of Vigo since 1997. His main topics of
114, Dec. 2003. interest are programmable logic devices and field
[18] L. Franquelo, M. Prats, R. Portillo, J. Galvan, M. Perales, J. Carrasco, programmable gate arrays architectures and design
E. Diez, and J. Jimenez, “Three-dimensional space-vector modulation methods, applied to industrial control problems.
algorithm for four-leg multilevel converters using abc coordinates,” IEEE
Trans. Ind. Electron., vol. 53, no. 2, pp. 458–466, Apr. 2006.
[19] J. I. Leon, R. C. Portillo, L. G. Franquelo, S. Vazquez, J. M. Carrasco,
and E. Dominguez, “New space vector modulation technique for single-
phase multilevel converters,” in Proc. IEEE Int. Symp. Ind. Electron.,
Vigo, Spain, Jun. 4–7, 2007, pp. 617–622. Jesús Doval-Gandoy (M’99) received the M.Sc. de-
[20] Q. Song, X. Zhang, F. Yu, and C. Zhang, “Research on space vector PWM gree from Polytechnic University of Madrid, Madrid,
of five-phase three-level inverter,” in Proc. 8th ICEMS, Sep. 27–29, 2005, Spain, in 1991, and the Ph.D. degree from the Uni-
vol. 2, pp. 1418–1421. versity of Vigo, Vigo, Spain, in 1999.
[21] H. Zhang, A. Von Jouanne, S. Dai, A. Wallace, and F. Wang, “Multilevel From 1991 to 1994, he worked at industry. He is
inverter modulation schemes to eliminate common-mode voltages,” IEEE currently an Associate Professor with the University
Trans. Ind. Appl., vol. 36, no. 6, pp. 1645–1653, Nov./Dec. 2000. of Vigo. His research interest is in the area of ac
[22] J. H. Seo, C. H. Choi, and D. S. Hyun, “A new simplified space-vector power conversion.
PWM method for three-level inverters,” IEEE Trans. Power Electron.,
vol. 16, no. 4, pp. 545–550, Jul. 2001.
[23] P. C. Loh and D. Holmes, “Flux modulation for multilevel inverters,”
IEEE Trans. Ind. Appl., vol. 38, no. 5, pp. 1389–1399, Sep./Oct. 2002.
[24] A. Gupta and A. Khambadkone, “A space vector PWM scheme for multi-
level inverters based on two-level space vector PWM,” IEEE Trans. Ind. Francisco D. Freijedo (M’07) was born in Spain,
Electron., vol. 53, no. 5, pp. 1631–1639, Oct. 2006. in 1978. He received the M.Sc. degree in physics
[25] A. Cataliotti, F. Genduso, A. Raciti, and G. R. Galluzzo, “Gener- from the University of Santiago de Compostela,
alized PWMVSI control algorithm based on a universal duty-cycle Santiago de Compostela, Spain, in 2002. Since 2003,
expression: Theoretical analysis, simulation results, and experimental he has been working toward the Ph.D. degree with
validations,” IEEE Trans. Ind. Electron., vol. 54, no. 3, pp. 1569–1580, the Department of Electronic Technology, University
Jun. 2007. of Vigo, Vigo, Spain.
[26] P. de Silva, J. Fletcher, and B. Williams, “Development of space vector Since 2005, he has been an Assistant Professor at
modulation strategies for five phase voltage source inverters,” in Proc. the University of Vigo. His research interests include
2nd Int. Conf. PEMD (Conf. Publ. No. 498), Mar. 31–Apr. 2 2004, vol. 2, power quality problems, grid connected switching
pp. 650–655. converters, ac power conversion, and FACTS.

Authorized licensed use limited to: University of Obuda. Downloaded on November 16,2022 at 14:38:48 UTC from IEEE Xplore. Restrictions apply.