Computer Architecture
Lecture 6
Instruction Set Architecture (ISA)
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Instructions
⚫ Instructions are the “words” of a computer
⚫ Instruction set architecture (ISA) is its
vocabulary
⚫ This defines most of the interface to the
processor.
Instruction Set Design
software
instruction set
hardware
◼ Multiple Implementations: 8086 → Pentium 4
◼ ISAs evolve: MIPS-I, MIPS-II, MIPS-II, MIPS-IV,
MIPS,MDMX, MIPS-32, MIPS-64
Basics
◼ C statement
f = (g + h) – (i + j)
◼ MIPS instructions
add t0, g, h
add t1, i, j
sub f, t0, t1
◼ Opcode/mnemonic, operands, source/destination
Basics
◼ Opcode: specifies the kind of operation (mnemonic)
◼ Operands: input and output data (source/destination)
◼ Operands t0 & t1 are temporaries
◼ One operation, two inputs, one output
◼ Multiple instructions for one C statement
Processor Execution Cycle
Instruction Obtain instruction from program storage
Fetch
Instruction Determine required actions and instruction size
Decode
Operand Locate and obtain operand data
Fetch
Execute Compute result value or status
Result Deposit results in register or storage for later use
Store
Next Determine successor instruction
Instruction
Memory Addressing
Memory Addressing
◼ Since 1980, almost every machine uses addresses to
level of 8-bits (byte)
◼ Two questions for design of ISA:
❑ Since could read a 32-but word as four loads of bytes
from sequential byte address of as one load word
from a single byte address, how do byte addresses
map onto words?
❑ Can a word be placed on any byte boundary?
Addressing Modes
Addressing Modes
◼ Addressing modes are an aspect of the instruction set
architecture in most central processing unit (CPU) designs.
◼ The various addressing modes that are defined in a given
instruction set architecture define how machine
language instructions in that architecture identify
the operand (or operands) of each instruction.
◼ An addressing mode specifies how to calculate the
effective memory address of an operand by using information
held in registers and/or constants contained within a machine
instruction or elsewhere.
Addressing Modes
◼ Immediate
◼ Direct
◼ Indirect
◼ Register
◼ Register Indirect
◼ Displacement (Indexed)
◼ Stack
Immediate Addressing
◼ Operand is a part of instruction
◼ Operand = address field
◼ e.g. ADD 5
❑ Add 5 to contents of accumulator
❑ 5 is operand
◼ No memory reference to fetch data
◼ Fast
◼ Limited range
Immediate Addressing Diagram
Instruction
Opcode Operand
Direct Addressing
◼ Address field contains address of operand
◼ Effective address (EA) = address field (A)
◼ e.g. ADD A
❑ Add contents of cell A to accumulator
❑ Look in memory at address A for operand
◼ Single memory reference to access data
◼ No additional calculations to work out effective address
◼ Limited address space
Direct Addressing Diagram
Instruction
Opcode Address A
Memory
Operand
Indirect Addressing (1)
◼ Memory cell pointed to by address field contains the
address of (pointer to) the operand.
◼ EA = (A)
❑ Look in A, find address (A) and look there for operand
◼ e.g. ADD (A)
❑ Add contents of cell pointed to by contents of A to
accumulator
Indirect Addressing Diagram
Instruction
Opcode Address A
Memory
Pointer to operand
Operand
Indirect Addressing (2)
◼ Large address space: 2n where n = word length
◼ May be nested, multilevel, cascaded
❑ e.g. EA = (((A)))
◼ Multiple memory accesses to find operand
◼ Hence slower
Register Addressing (1)
◼ Operand is held in register named in address filed
◼ EA = R
◼ Limited number of registers
◼ Very small address field needed
❑ Shorter instructions
❑ Faster instruction fetch
Register Addressing Diagram
Instruction
Opcode Register Address R
Registers
Operand
Register Addressing (2)
◼ No memory access
◼ Very fast execution
◼ Very limited address space
◼ Multiple registers helps performance
❑ Requires good assembly programming or compiler writing
Register Indirect Addressing
◼ C.f. indirect addressing
◼ EA = (R)
◼ Operand is in memory cell pointed to by contents of
register R
◼ Large address space (2n)
◼ One fewer memory access than indirect addressing
Register Indirect Addressing Diagram
Instruction
Opcode Register Address R
Memory
Registers
Pointer to Operand Operand
Displacement Addressing
◼ EA = A + (R)
◼ Address field hold two values
❑ A = base value
❑ R = register that holds displacement
Displacement Addressing Diagram
Instruction
Opcode Register R Address A
Memory
Registers
Pointer to Operand + Operand
Relative Addressing
◼ A version of displacement addressing
◼ R = Program counter, PC
◼ EA = A + (PC)
◼ i.e. get operand from A cells from current location
pointed to by PC
◼ c.f locality of reference & cache usage
Indexed Addressing
◼ A = base
◼ R = displacement
◼ EA = A + R
◼ Good for accessing arrays
❑ EA = A + R
❑ R++
Stack Addressing
Accumulator Addressing
Register-Set Architectures
Register-to-Register: Load-Store
Architectures
Register-to-Memory Architectures
Memory-to-Memory Architectures
Addressing Modes Summary
Addressing Summary
◼ Data Addressing modes that are important:
❑ Displacement, Immediate, Register Indirect
◼ Displacement size should be 12 to 16 bits
◼ Immediate size should be 8 to 16 bits
Instruction Formats
Instruction Formats
◼ Layout of bits in an instruction
◼ Includes opcode
◼ Includes (implicit or explicit) operand(s)
◼ Usually more than one instruction format in an
instruction set
Instruction Length
◼ Affected by:
❑ Memory size
❑ Memory organization
❑ Bus structure
❑ CPU complexity
❑ CPU speed
◼ Trade off between powerful instruction repertoire
and saving space
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Instruction and Data Memory: Unified or Separate
Programmer's View Computer
Program
ADD 01010 (Instructions)
SUBTRACT 01110
AND 10011 CPU
OR 10001 Memory
COMPARE 11010
. .
. . I/O
. .
Computer's View
Princeton (Von Neumann) Architecture Harvard Architecture
--- Data and Instructions mixed in same --- Data & Instructions in
unified memory separate memories
--- Program as data --- Has advantages in certain
high performance
--- Storage utilization implementations
--- Single memory interface --- Can optimize each memory
Instruction Sequencing
◼ The next instruction to be executed is typically implied
❑ Instructions execute sequentially
❑ Instruction sequencing increments a Program Counter
Instruction 1 Instruction 1
Instruction 2 Instruction 2
Instruction 3 Conditional Branch
Instruction 4
◼ Sequencing flow is disrupted conditionally and
unconditionally
❑ The ability of computers to test results and conditionally
instructions is one of the reasons computers have become
so useful
Branch instructions are ~20% of all
instructions executed
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Basic Instruction
◼ Add: add two numbers
◼ Mul: multiply two numbers
◼ Move: move data between two places
◼ Load: load data from memory to register
◼ Store: store data from registers to memory
◼ Push and Pop for stack operations
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Register Types: Assume 16-bit registers
◼ Accumulator register (ACC)
◼ Instruction register (IR)
◼ Program Counter (PC)
◼ Address register (AR)
◼ General purpose registers (R0 t0 R6)
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Write an assembly language program
◼ To write a program using ISA we should know the
addressing mode of the processor.
◼ The operands fetch operation will be different based on the
addressing mode.
◼ Steps for write an assembly program:
1. Specify the addressing mode type.
2. Convert the statement to assembly language.
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Example
◼ Write an assembly code for execute the following
statements using accumulator addressing mode,
register addressing mode, indirect mode, stack
mode and register indirect and store the result in
memory which has the address stored in AR:
➢ F=A+B+5
➢ X=A+(B*4)
➢ Z=A*B*C+7
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F=A+B+5
Using Accumulator addressing mode
◼ Load ACC, A
◼ Add B
◼ Add 5
◼ Store M[AR]
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F=A+B+5
Using Register addressing mode
◼ Load R0, A
◼ Load R1, B
◼ Load R2, 5
◼ Add R0,R1
◼ Add R0,R2
◼ Move M[AR],R0
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