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LAB 2: Sequential Logic – Counters and Timers

Name: Tran Van Quoc Dat

Ha Phuoc Khanh

Nguyen Van Cong Toan

1. Design description

1.1 bcd_counter module

module bcd_counter( input clk, input

reset_n, input
enable, output reg [3:0]
digit0, // units digit output
reg [3:0] digit1, // tens digit output reg [3:0] digit2 // hundreds digit

);

always @(posedge clk or negedge reset_n) begin if (!reset_n) begin digit0 <= 0; digit1
<= 0; digit2 <= 0; end else if (enable)
begin // count units if
(digit0 == 9) begin
digit0 <= 0;

// count tens if (digit1 == 9)

begin digit1 <= 0;

// count hundreds if (digit2 ==

9) digit2 <= 0; else digit2 <=
digit2 + 1; end else
begin
digit1 <= digit1 + 1;

end
end else begin digit0 <=
digit0 + 1;
end
end
end
end module

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1.2 Clock_divider Module

module clock_divider( input clk,
input reset_n, // CLOCK_50
output reg enable // KEY[0] push button (active low)
// 1Hz trigger pulse
);

reg [25:0] count;

always @(posedge clk or negedge reset_n) begin if (!reset_n) begin count <=
26'd0; enable <= 0; end else
begin if (count ==
26'd49_999_999)
begin

count <= 0; enable

<= 1; // pulse to high level in 1 clock cycle end else begin count <= count + 1; enable <= 0;

end
end
end
end module

1.3 Module hex_decoder

module hex_decoder ( input [3:0]
bcd, output reg [6:0] seg //
7 segments: seg[6]=a, ..., seg[0]=g
);
always @(*) begin case
(bcd) 4'd0: seg
= 7'b1000000; // 0 4'd1: seg = 7'b1111001; // 1
4'd2: seg = 7'b0100100; // 2 4'd3: seg =
7'b0110000; // 3 4'd4: seg = 7'b0011001; // 4
4'd5: seg = 7'b0010010; // 5 4'd6: seg =
7'b0000010; // 6 4'd7: seg = 7'b1111000; // 7
4'd8: seg = 7'b0000000; // 8 4'd9: seg =
7'b0010000; // 9 default: seg = 7'b1111111; //
Turn all off

end case
end
endmodule

1.4 Module top

module top( input
CLOCK_50, input [0:0] // 50MHz clock from DE2 // reset button
KEY, output [6:0] HEX0, (KEY[0])
output [6:0] HEX1, output // 7-segment LED unit row
[6:0] HEX2 // 7-segment LED tens
// 7-segment LED hundreds

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);

wire reset_n = KEY[0]; // reset active-low // pulse 1Hz wire enable_1Hz;

d2; // BCD digits wire [3:0] d0, d1,

// Clock divider (generates 1Hz enable pulse) clock_divider

clkdiv( .clk(CLOCK_50), .reset_n(reset_n), .enable(enable_1Hz)

);

// BCD counter
bcd_counter

counter( .clk(CLOCK_50), .reset_n(reset_n), .enable(enable_1Hz), .digit0(d0), .digit1(d1), .digit2(d2)

);

// HEX display
hex_decoder h0(.bcd(d0), .seg(HEX0)); hex_decoder
h1(.bcd(d1), .seg(HEX1)); hex_decoder h2(.bcd(d2), .seg(HEX2));

end module

1.5 Assignment pin-out DE2 board

2. Answer the question

2.1 Distinguish between blocking (=) and non-blocking (<=) in Verilog?

“Blocking” executes in order, “non-blocking” allows parallel simulation.

In always @(posedge clk) blocks, <= should be used to describe the register behavior.

(avoid wrong order of value update).

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2.2 Describe how you design the BCD counting logic? Does it detect
when a digit reaches 9?
Yes. When the digit reaches 9, reset to 0 and activate the next digit.

Verilog code in module bcd_counter.v

if (digit0 == 9) begin digit0 <= 0;

// count tens if (digit1 == 9)

begin digit1 <= 0;

// count hundreds if (digit2 ==

9) digit2 <= 0; else digit2 <=
digit2 + 1; end else
begin
digit1 <= digit1 + 1;

end
end else begin digit0 <=
digit0 + 1;
end

2.3 What is the purpose of the enable signal in bcd_counter?

Make sure to count only when the enable signal (1Hz from clock_divider) is active.

2.4 Output from Quartus II compile report: How many flip-flops are there?
used?
Based on the compilation report from Quartus II, the total number of flip-flops (registers)

used is 2, including:

• clock_divider: 1 flip-flop

• bcd_counter: 1 flip-flop

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2.5 What is Metastability? Why should we care when using discordant signals?
set like reset?

a. What is Metastability?

Metastability is a phenomenon that occurs when a flip-flop receives an input signal that

changes too close to the clock edge, causing the flip-flop to not be able to stabilize in time at the

logic 0 or 1. Instead, it falls into an intermediate (undefined) state for a short period of

time, causing an undefined result or logic error.

This is especially serious when dealing with asynchronous signals, such as reset
buttons, signals from peripheral devices, etc. These signals are not synchronized with the

system clock and can easily cause metastability when fed directly to the flip-flop.

flop operates by clock.

b. Why care?

• Causes unpredictable logic errors in digital systems.

• Causes the circuit to operate unstable or hang (glitch).

• Difficult to detect and reproduce errors in simulation or reality.

c. Solution:

• Use a synchronizer: usually 2 flip-flops in series operating with a clock to filter

metastability.

• Use edge detector or debounce circuit to process the signal

asynchronous like push button.

• Introduce asynchronous signals into the clock domain through intermediate processing mechanisms.