0% found this document useful (0 votes)
3 views2 pages

AMCS42 Computer Architecture 1

This document is an examination paper for the BSc (CBCS) Degree in Computer Science, specifically for the Computer Architecture course. It consists of multiple-choice questions, short answer questions, and detailed essay questions covering various topics in computer architecture. The exam is structured into three parts: Part A with 10 multiple-choice questions, Part B with 5 short answer questions, and Part C with 5 detailed essay questions.

Uploaded by

cocojoy32
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
0% found this document useful (0 votes)
3 views2 pages

AMCS42 Computer Architecture 1

This document is an examination paper for the BSc (CBCS) Degree in Computer Science, specifically for the Computer Architecture course. It consists of multiple-choice questions, short answer questions, and detailed essay questions covering various topics in computer architecture. The exam is structured into three parts: Part A with 10 multiple-choice questions, Part B with 5 short answer questions, and Part C with 5 detailed essay questions.

Uploaded by

cocojoy32
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
You are on page 1/ 2
G pages) Code No. : 20330 E ‘Time : Three hours Reg. No. Sub. Code : AMCS 42 BSc, (CBCS) DEGREE EXAMINATION, NOVEMBER 2023. Fourth Semester Computer Science — Core COMPUTER ARCHITECTURE. or those who joined in July 2020 only) 5 marks ‘Maximum : PART A— (10 x 1 = 10 marks) Answer ALL questions, Choose the correct answer : ‘The decoded instruction is stored in_. @ IR ® PC © Registers @ or Subtraction in computers is carried out by (@) 1's complement (©) 2s complement (© 8's complement @ Ys complement Which of the following memory unit communicates directly with the CPU? (@) . Auxiliary memory () Main memory © Secondary memory @ None of the above Interrupts initiated by an instruction is called as (@) Internal o © Hardware External @ Software method is used to map logical addresses of Variable length onto physical memory. (@) Paging (b) Overlays © Segmentation @ Paging with segmentation Page3 Code No. : 20330 E 10. ML. 2 18, A source program is usitally in (9) Assembly language (®) Machine level language © High-level language (@) Natural language The ALU makes use of intermediate results. to store the (@) Accumulators ©) Registers © Heap @ Stack ‘The addressing mode which makes use of in- direction pointers is (0) Indirect addressing mode () «Index addressing mode (©) Relative addressing mode (@) Offset addressing mode Booth's Algorithm is applied on__-__. (@) decimal numbers ©) binary numbers © hexadecimal numbers @ octal numbers Page2 Code No. : 20330 E ‘The DMA controller has registers, @ 4 &® 2 © 3 @a PART B— (5 x 5 = 25 marks) Answer ALL questions choosing either (a) or (b) Bach answer should not exceed 250 words, (@) Explain the phases, involved in Instruction cycle with the help of necessary timing diagrams? Or () Describe the Common Bus system. (@) Wlustrate the Basie computer instruction formats with a neat sketch. Or ©) Write about control word. (@ @ Add 11011 and 10101 Add 1111 and 0101. Or (®) Write note on floating point arithmetic with example. Paget Code No. : 20330 E P70) M4. 15. 16. 17, 18, @ © ) w Sketch and express about DMA. Or How Parallel Priority Interrupt works? Describe. Discuss the Memory Hierarchy in computer system. Or How Cache memory works? Explain PART C— (5x 8=40 marks) Answor ALL questions choosing either (a) or (b) Bach answer should not exceed 600 words, @) o @) w @ © Express in detail about computer registers. Or Sketch and explain about control unit of basic computer. Draw and explain General register organization. Or Mlustrate addressing modes. Write and explain the flowchart for division. Or Explain in detail about booth multiplication algorithm with an example? Page 5 Code No. : 20330 E 19, 20. @ ) @) © Draw the block diagram for VO Bus and interface modules. Or How data transfer from 10 device to CPU takes place in a computer? Explain about main momory arid its types. Or Brief out the hardware organization of Associative memory with diagrams.

You might also like