2016 International Conference on Circuit, Power and Computing Technologies [ICCPCT]

Implementation of Image Edge Detection on FPGA

using XSG
G. Bharadwaja Reddy K. Anusudha
Dept. of Electronics Engineering Dept. of Electronics Engineering
Pondicherry University Pondicherry University
Pondicherry, India Pondicherry, India
[email protected] [email protected]

Abstract—Image edge detection plays a vital role in image II. SYSTEM REQUIREMENTS FOR THE PROPOSED APPROACH
processing. Edges are the pre-dominant features of an image A compatible MATLAB and Xilinx ISE softwares are
which is mainly used to analyze the images and to process that required to design the proposed approach using XSG.
image. Hardware implementation of image edge detection is
Simulink is used as a developing tool for XSG. XSG provides
essential for real time applications to increase the speed of
operation. This paper proposes a method that uses a graphical a library of simulink blocks, memories and DSP functions. It
user interface that combines MATLAB, Simulink and Xilinx also includes code generator which generates VHDL/Verilog
System Generator(XSG) to generate a code which is hardware code automatically from the created model. The code
implemented onto Spartan-3E Field Programmable Gate Array generated in VHDL/Verilog can be synthesized and
(FPGA).This Paper also provides an image edge detection using implemented in FPGAs. The blocks used in Xilinx System
Robert, Prewitt, Sobel and Laplacian of Gaussian (LoG) Generator also called as Xilinx Blocks [5] operate with
operators and implemented on FPGA. Boolean values in fixed point, as they are used to design in
hardware whereas Simulink Blocks [8] can operate in
Keywords—Image Edge Detection, Robert, Prewitt, Sobel, LoG,
continuous time and floating point format. Gateway Blocks
Xilinx System Generator, Spartan-3E FPGA.
are used for connection between Simulink blocks and Xilinx
I. INTRODUCTION AND MOTIVATION blocks. In addition to generating a user constraint file (UCF),
An edge is a point of sharp change in an image, a region test bench and test vectors among other things.
where pixel locations have abrupt luminance change i.e. a III. SCHEMATIC OF IMAGE PROCESSING TECHNIQUE
discontinuity in gray level values. The edge detection in image
processing, particularly in the areas of feature extraction aims The image processing techniques using Simulink and
at identifying points at which the image brightness changes MATLAB entirely goes through three phases [3] as shown in
sharply [1]. To process the image in real time, leads to Fig.1.
implement them in hardware, which significantly reduces the
processing time by parallelism [4]. FPGAs are used in digital
image processing to meet the real time applications [2,3] Any image Image post
Image pre
because of their programmability, it means modifying the Processing
Processing Processing
device function in lab or the working site where device is technique using
Blocks Blocks
installed. Writing thousands of code lines using high level Xilinx blocks
language for image processing is impractical and time
consuming. So, a tool called Xilinx System Generator (XSG)
[5-7] with graphical interfacing MATLAB-Simulink [8]is Fig.1 Basic block diagram
used to produce software environment for hardware A. Image pre processing blocks:
description.
As an image is two dimensional (2D) array size with R*C
The rest of the paper is organized as follows. Section II
where R,C represent the row and column of an image
discusses the requirements for the proposed approach and the
respectievly. For image processing, image must be converted
different types of blocks used in the design. Section III
to one dimensional (1D) vector. Image pre processing blocks
discusses the basic block diagram of image processing
are used to convert 2D image data to 1D array which is shown
technique. Section IV discusses the design of the various
in Fig.2.block which converts this frame to scalar output
image edge detection techniques implemented in this paper
samples at a higher sampling rate.
using Xilinx blocks. Section V discusses the hardware
implementation of edge detection on FPGA. Section VI
discusses the results of all techniques and section VII
discusses the conclusion.

978-1-5090-1277-0/16/$31.00 ©2016 IEEE

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 2016 International Conference on Circuit, Power and Computing Technologies [ICCPCT]

Fig.2 Image pre processing block

B. Any image processing technique using XSG:

All Xilinx blocks are connected between Gateway In and Fig.6 Implementation of image edge detection
Gateway Out and any image processing technique is applied
between those two blocks as shown in Fig.3. Since, Xilinx The image which has to be processed is taken from file
blocks process on fixed point but the real world signal process and fed to the pre processing block as shown in Fig.2. The
on floating point so to convert fixed point to floating point, horizontal and vertical gradient blocks shown in Fig.6 can be
Gateway In and Gateway Out blocks acts as translators for implemented by using the model shown in Fig.7. The
converting the real world signal into the desired manner. corresponding mask value should be kept into the FIR
compiler 5.0 in the Fig.7 to perform particular edge detection.
The absolute value block shown in Fig.7 can be implemented
by using design shown in Fig.8. The thresholding block shown
in Fig.6 can be implemented by using the design shown in
Fig.9.
Fig.3 Xilinx Blocks

C. Image post processing:

The image post processing blocks are used to convert back
to floating point type as shown in Fig.4. It also includes a
buffer block which converts scalar samples to frame output at
lower sampling rate, followed by convert 1-D to 2-D,
transpose blocks.

Fig.7 Horizontal/Vertical gradient

Fig.4 Image post processing blocks

IV. IMAGE PROCESSING TECHNIQUES USING XILINX BLOCKS

In this section the image processing techniques based on
image edge detection using Robert, Prewitt, Sobel and
Laplacian of Gaussian (LoG) operator masks are implemented
using Xilinx blocks and then they are implemented on Spartan
3E FPGA.
To perform the image edge detection the input image is
convolved with any of the above mentioned filter masks. The Fig.8 Absolute
design methodology of edge detection using Xilinx System
Generator is shown in Fig.5. Implementation of image edge
detection using Xilinx blocks is shown in Fig.6.

Fig.9 Thresholding

The Edges of an image can be detected by convolving the

input image with their respective filter masks. There are
Fig.5 Design methodology of edge detection

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 2016 International Conference on Circuit, Power and Computing Technologies [ICCPCT]
different basic operators [9] which develops filter masks to -1 -1 -1
convolve with input image and is shown below.
-1 8 -1
A. Edge Detection based on Robert operator:
It is proposed by Lawrence Roberts in 1963 and used in image -1 -1 -1
processing and computer vision for edge detection. It is a
Gx
differential operator that approximates the gradient of an
image through discrete differentiation which is achieved by Fig.13 Laplacian of Gaussian operator
computing the sum of the squares of the differences between The above all kernels undergo maximally to edges running
diagonally adjacent pixels implemented by two 2x2 mask as vertically and horizontally relative to pixel grid. The gradient
shown in Fig.10. magnitude is given as eq.1:

0 1 -1 0 |G| = |Gx| + |Gy| (1)

-1 0 0 1 Thresholding is subjected to identify the edge pixels. If

gradient is greater than threshold then that pixel is kept as
GxGy edge pixel.
Fig.10 Robert operator
V. HARDWARE IMPLEMENTATION
B. Edge Detection based on Prewitt operator:
The Prewitt operator is based on the idea of central difference The above explained designs are implemented in software
and is much better than Roberts’s operator. It is based on simulation level. To implement this design on to FPGA board
convolving the image with a small, separable, and integer the entire design should be converted to FPGA synthesizable
valued filter in horizontal and vertical direction as shown in one. Using System generator token the entire main module for
Fig.11. Prewitt’s operator is less vulnerable to noise. any edge detection is converted for JTAG hardware co-
simulation. A new window will open by clicking on system
-1 -1 -1 -1 0 1 generator token as shown in Fig.14. This block is configured
according to the target platform and a bit stream(*.bit) file is
0 0 0 -1 0 1 generated. After the generation of bit stream file, hardware co-
simulation target is selected and for board level
1 1 1 -1 0 1
implementation Spartan 3E starter kit (XC3S500E-FG320) is
GxGy
used. By clicking the generate button in system generator
Fig.11 Prewitt operator token a hardware co-simulation block will be generated. The
generated block is added in the design and thereby FPGA and
C. Edge Detection based on sobel operator: XSG/software outputs at a time are depicted at a time. The
The Sobel operator is also based on central difference with entire design with the hardware and software co-simulation
more weights to the central pixels where averaging as given modules for the edge detection is shown in Fig.15.
by the mask shown in Fig.12. It has improved noise
suppression than Prewitt’s operator.
-1 -2 -1 -1 0 1

0 0 0 -2 0 2

1 2 1 -1 0 1
GxGy
Fig.12 Sobel operator

D. Laplacian of Gaussian operator:

The Laplacian of an image highlights regions of rapid
intensity change and is therefore often used for edge
detection.The Laplacian is often applied to an image that has
been smoothed first with something approximating a Gaussian
Smoothing filter in order to reduce its sensitivity to noise.The
operator normally takes a single gray levelimage as input and
produces another gray level image as output [10]. The kernels
used to detect edges of an image is shown in Fig.13. Fig.14 System generator token

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 2016 International Conference on Circuit, Power and Computing Technologies [ICCPCT]
corresponding software output and the FPGA/Hardware
output are shown in Fig.18 (b), (c) respectively. The PSNR
value obtained is 22.05. Similarly different sized images of
424X749 and 300X420 are given as input and are observed
that as the size of image increases, PSNR values are
decreasing. The Verilog code generated for edge detection
consists of 38075 lines.

(a) (b) (c)

Fig.15 Hardware software Co-simulation for the edge detection Fig.18. (a) input image (b) software output (c) FPGA output

D. Results for edge detection based on LoG operator:

VI. RESULTS AND DISCUSSION
The image shown in Fig.19 (a) of size 512X512 is given as
Peak Signal to Noise Ratio (PSNR) is used to measure the input to the design shown in Fig.6 and the corresponding
similarity between Hardware/FPGA output and software output and the FPGA/Hardware output are shown in
MATLAB/simulink output for a given image. As the PSNR Fig.19 (b), (c) respectively. The PSNR value obtained is
value is high, the quality of image is good. Here, the PSNR 23.23. Similarly different sized images of 424X749 and
value is calculated between the MATLAB/simulink output and 300X420 are given as input and are observed that as the size
FPGA output. of image increases, PSNR values are decreasing. The Verilog
A. Results for edge detection based on Robert operator: code generated for edge detection consists of 42886 lines.
The image shown in Fig.16 (a) of size 512X512 is given as
input to the design shown in Fig.6 and the corresponding
software output and the FPGA/Hardware output are shown in
Fig.16 (b), (c) respectively. The PSNR value obtained is
20.89. Similarly different sized images of 424X749 and
(a) (b) (c)
300X420 are given as input and are observed that as the size Fig.19. (a) input image (b) software output (c) FPGA output
of image increases, PSNR values are decreasing. The Verilog
code generated for edge detection consists of 14650 lines. E. Device utilization summary
In the design along with system generator token, resource
estimator is added to calculate the amount of resources utilized
after simulating the design in the FPGA. The amount of
resources utilized for the image edge detection which are
implemented in this paper are tabulated in the Table I.
(a) (b) (c)
Fig.16. (a) input (b) software output (c) FPGA output TABLE I. DEVICE UTILIZATION SUMMARY

B. Results for edge detection based on Prewitt operator: Image Processing Technique Slices FFs LUTs IOBs

The image shown in Fig.17 (a) of size 512X512 is Robert operator edge detection 768 1237 1209 32
given as input to the design shown in Fig.6 and the
corresponding software output and the FPGA/Hardware
Prewitt operator edge detection 943 1357 1479 32
output are shown in Fig.17 (b), (c) respectively. The PSNR
value obtained is 21.23.Similarly different sized images of
424X749 and 300X420 are given as input and are observed Sobel operator edge detection 945 1357 1604 32
that as the size of image increases, PSNR values are
Laplacian of Gaussian operator
decreasing. The Verilog code generated for edge detection edge detection
991 1632 1625 36
consists of 19110 lines.

VII. CONCLUSION
In this paper, various image processing techniques based
on image edge detection like Robert, Prewitt, Sobel and
(a) (b) (c) Laplacian of Gaussian are designed and implemented on
Fig.17. (a) input (b) software output (c) FPGA output Spartan 3E FPGA using Xilinx System Generator. It is simpler
to generate a stream of bit files rather than writing thousands
C. Results for edge detection based on Sobel operator: of code lines for implementing of image processing techniques
The image shown in Fig.18 (a) of size 512X512 is on FPGA. The PSNR value decreases as the number of pixels
given as input to the design shown in Fig.6 and the of input image increases. Among all the edge detectors

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 2016 International Conference on Circuit, Power and Computing Technologies [ICCPCT]
Laplacian of Gaussian operator achieves the best PSNR value
and also detects edges better than other operators. This work
can be further extended to implement for medical and video
processing applications on FPGA.
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