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Experiment_4

The document contains several Verilog modules for different types of shift registers, including Right Shift, Left Shift, PIPO Shift, and Bidirectional Shift registers. Each module is defined with parameters for size, input, and output, and includes functionality for resetting and shifting data based on clock signals. The document also includes sections for RTL and TTL viewers, as well as simulation placeholders.

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Kamal Ranni
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Experiment_4

The document contains several Verilog modules for different types of shift registers, including Right Shift, Left Shift, PIPO Shift, and Bidirectional Shift registers. Each module is defined with parameters for size, input, and output, and includes functionality for resetting and shifting data based on clock signals. The document also includes sections for RTL and TTL viewers, as well as simulation placeholders.

Uploaded by

Kamal Ranni
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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FPGA

Experiment_4
Name: Kashyap Joshi
Class: 4BECB1
Roll No:23BEC084
 Right Shi Register

module USR #(parameter size=4)(input Reset,input CLK,input Data_in,output reg


Data_out);

reg [size:0] shi _reg;

always @(posedge CLK) begin

if (Reset)

shi _reg<= 4'b0000; //Resets the register

else begin

Data_out<=shi _reg[0];

shi _reg<={Data_in,shi _reg[3:1]};

end

end

endmodule
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 Le Shi Register
module USR #(parameter size=4)(input Reset,input CLK,input Data_in,output reg
[size-1:0]Data_out);

reg [size-1:0] shi _reg;

always @(posedge CLK) begin

if (Reset)

shi _reg<= 4'b0000; //Resets the register

else begin

Data_out<=shi _reg[3];

Data_out<={shi _reg[2:0],Data_in};

end

end

endmodule

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 PIPO Shi Register


module USR #(parameter size=4)(input Reset,input CLK,input [3:0]Data_in,output reg
[size-1:0]Data_out);

always @(posedge CLK) begin

if (Reset)

Data_out=4'b0000;

else

Data_out=Data_in;

end

endmodule
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 Bidirec onal Shi Register


module USR #(parameter size=4)(input Reset,input CLK,input [size:0] parallel_input,input
serial_input_le ,input serial_input_right,input [1:0]control_line,output reg
[size:0]Data_out);

always @(posedge CLK) begin

if (Reset)

Data_out=4'b0;

else begin

case(control_line)

2'b00:Data_out<=Data_out; //No change

2'b01:Data_out<={serial_input_right,Data_out[size-1:1]}; //Right
Shi

2'b10:Data_out<={Data_out[size-2:0],serial_input_le }; // Le
Shi

2'b11:Data_out<=parallel_input; //Parallel Loading

endcase

end

end

endmodule
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