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Design Rule Checks and

FSiC 2019

Layout to Netlist Tool

Matthias Köfferlein, klayout.org
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 Introduction
This chapter will tell you ...

ly a bo ut the
The basic idea
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Brie f
of D RC an d LV S theory of DRC
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About other he
Briefly about t
applications of
R C f e at ur e theory of LVS
th e D

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 Basic Idea of DRC & LVS

● Design Rule Check (DRC) verifies that ...

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– Devices and interconnect structures can be

manufactured with good yield
– Good yield is important because a small
likelihood of single-point fails adds to a
FSiC 2019

high risk
● Layout vs. Schematic (LVS) verifies that ...
– The layout represents the schematic

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 DRC Theory in a Nutshell

● The design manual lists the constraints of the manufacturing

process as design rules
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– Basic rules include

● Min space, width, enclosure, separation
● Min area
– Advanced rules
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● Width dependent spacing

● Antenna rules
● Max/min density or density variation
● Arbitrary layout constraints
● The DRC engine provides features to implement these checks
● DRC scripts execute the checks to verify conformity
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 Basic DRC Rules
Space Separation
≥d ≥d
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Width Notch
≥d
≥d
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Enclosure

≥d

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 Layout Analysis and
Preselection
● DRC rules often don’t apply to raw mask
data, but on
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– Combined masks → Boolean operations

– Certain configurations → selection,
interacting, …
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● DRC scripts allow computing temporary

“layers” (= polygon sets) to represent
intermediate geometry
● Edge layers allow representing parts of
polygon borders
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 Some Polygon Layer
Derivation Functions
Boolean NOT Boolean AND Boolean XOR
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Negative sizing Positive sizing

Interacting (undersize) (oversize)
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d d

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 More Applications of the
DRC Features
● The output of DRC can be send to a new
layout or back to the original layout
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● → Manipulation of layout
– Derive mask data from drawing
– Apply technology bias (sizing)
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– Add computed content to drawn layout

● → Comparison of layouts
– Using the XOR function
– Apply post-XOR filter through sizing, ...
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 LVS Theory in a Nutshell

● The design manual describes the devices in terms of basic

geometry and layer combinations
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– The LVS identifies the devices from their characteristic

geometry
– The LVS identifies their connection points (“terminals”)
● The design manual describes the metal stack and further
conductive layers
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– The LVS uses this information to derive the device

connections from the wiring
– The connection graph renders the netlist
● The netlist derived from the layout is compared against the
design netlist to verify conformity

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 LVS Flow

● Preparation step
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– Derive device recognition and connecting layers

● Device recognition
– Isolate devices
– Identify and mark terminals
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● Connectivity evaluation Layout-to-netlist

● Netlist generation stage

● Netlist vs. netlist compare

Work in progress
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 Good Practice:
Bottom-up Verification
● Blocks shall be LVS and DRC clean before
being put together
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– Low risk of introducing new errors during

combination of blocks
● Golden rule of physical implementation
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 DRC Hands-On
This chapter will tell you ...

How to write a
nd How to debug
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n D RC s c ript s them
ru
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About the About layer

elements of a types and basic
DRC script functions

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 Example Technology

● Repo at
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https://github.com/klayoutmatthias/si4all
● Clone with git
git clone https://github.com/klayoutmatthias/si4all.git

● Or download as zip
FSiC 2019

https://github.com/klayoutmatthias/si4all/archive/master.zip
● Design manual link
https://github.com/klayoutmatthias/si4all/blob/master/dm.pdf

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 Example Design Manual
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 DRC scripts in KLayout
DRC scripts are written, tested and debugged in the Macro
Development IDE (Tools / Macro Developmen IDE)
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Includes another directory

Run the script here
for more scripts

Edit the script here

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Creates a new script

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 How to use the Examples

● Unpack zip or clone the git repo

In KLayout use Tools / Macro Development IDE
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● Chose the DRC tab

● Right-click into the script list
● Chose “Add location”
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● In the file browser navigate to the “drc” folder in

the sample you unpacked / cloned. Click “Ok”
● Double-click on the “drc” script to open it

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 DRC Script Elements:
Preamble
Implementation
Asks KLayout to create
report("DRC report") a marker database

# Drawing layers Reads the layer from

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the original layout

nwell = input(1, 0) from GDS layer 1,
diff = input(2, 0) datatype 0
pplus = input(3, 0)
nplus = input(4, 0)
poly = input(5, 0)
thickox = input(6, 0)
polyres = input(7, 0)
contact = input(8, 0)
metal1 = input(9, 0)
FSiC 2019

via = input(10, 0)
metal2 = input(11, 0)
pad = input(12, 0)
border = input(13, 0)

all_drawing = [
:nwell, :diff, :pplus, :nplus, :poly,
:thickox, :polyres,
:contact, :metal1, :via, :metal2, :pad
]

A list of variable names holding all drawing layers -

needed later
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 DRC Script Concepts

● A DRC script is written in Ruby using special methods (a DSL)

● The basic data type is a layer
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● Methods on layers
– Manipulate layers
– Derive new layers
● There are different types of layers:
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– Polygon layers for “filled” shapes. All original layers are polygon
layers.
– Edge layers holding edges (lines connecting two points). Edges
may, but do not need to be connected.
– Edge pair layers holding error markers (pairs of edges)
● Operations are executed in-flight, so their results can be used in
conditions (if) or loops (while)
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 Basic Geometric Checks
Example
with_area
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width
Implementation
# ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­
space # DIFF_S

min_diff_s = 600.nm
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r_diff_s = diff.space(min_diff_s)
r_diff_s.output("DIFF_S: diff space < 0.6µm”)
separation
# ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­
# DIFF_W

min_diff_w = 500.nm

r_diff_w = diff.width(min_diff_w)
enclosing r_diff_w.output("DIFF_W: diff width < 0.5 µm")

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 Check Anatomy

● min_diff_s = 600.nm
– Stores the check target value in a variable so it can be
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changed easier later

– Note the unit: 600.nm (with a dot!). Equivalent specs are:
0.6.um, 0.0006.mm. Always use units!
● r_diff_s = diff.space(min_diff_s)
“diff” is the original diffusion layer. “space” is the spacing
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–
check method. The space threshold is in the argument.
– The result is an edge pair error layer that is assigned to
the “r_diff_s” variable
● r_diff_s.output("DIFF_S: diff space < 0.6µm”)
– Sends the error layer to the marker DB into this category

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 Metrics
forbidden area

Example

euclidian metrics
(default)
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square metrics
Implementation (default)
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# ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­
# CONT_S

min_cont_s = 360.nm

r_cont_s = contact.space(square, min_cont_s)

r_cont_s.output("CONT_S: contact space < 0.36 µm”)

projecting metrics

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 Boolean Operations and
Selectors
Example
How this works:
● “contact” are the original
contact polygons. Same for
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“diff” and “poly”.

● “contact.inside(diff)” selects
all contacts which are
entirely inside diff. Same for
“contact.inside(poly)”.
Implementation “+” combines both results
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# ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­
into one layer (boolean OR)
# CONT_X
● “-” is the boolean NOT
r_cont_x = contact ­
(contact.inside(diff) + contact.inside(poly))
r_cont_x.output("CONT_X: contact not entirely
● So the result layer contains
inside diff or poly")
all contacts which are not
entirely inside diff or poly.
Those are the error markers.

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 More Operations
● Booleans: ● Selectors:
– “a + b” (OR) – a.interacting(b)
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– “a & b” (AND) – a.not_interacting(b)

– “a – b” (NOT) – a.inside(b)
– “a ^ b” (XOR) – a.outside(b)
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– a.overlapping(b)
● Sizing (bias): – a.touching(b)
– a.sized(d) – a.not_inside(b)
– a.sized(dx, dy) – a.not_outside(b)
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 Edge Operations
Example
How this works:
● “poly” are the original
polygons.
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● “edges” will dissolve the

polygons into connecting
lines.
● “with_length(0,L)” selects all
edges with length between 0
Implementation and L (L itself is excluded!).
FSiC 2019

min_poly_edge_length = 70.nm ● Such edges are used as error

r_poly_x1 = poly.edges.with_length(0, markers to flag short edges.
min_poly_edge_length)
r_poly_x1.output("POLY_X1: edge length < 0.07 µm")

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 More Edge Operations
● Booleans: ● Selectors:
– “a + b” (OR) – a.interacting(b)
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– “a & b” (AND) – a.not_interacting(b)

– “a – b” (NOT)
– “a ^ b” (XOR) ● Polygonization
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– a.extended
For some operations, the b
operand may also be a
– a.extended_in
polygon layer! – a.extended_out

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 Combined Operations I
Example How this works:
● poly edges are decomposed
into edges crossing diff (gate
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edges) and other edges.

● The other edges are checked
against diff with “separation”
with the POLY_X2 limit. From
these edge pairs the poly edges
are selected. poly is first
argument to the edge-wise
Implementation separation: poly is in
FSiC 2019

min_poly_ext_over_diff = 250.nm
first_edges.

poly_edges = poly.edges ● All such edges which directly

poly_gate_edges = poly_edges.interacting(diff) connect to gate edges indicate
other_poly_edges = poly_edges.not_interacting(diff)
a violation of this condition.
# ope_cd = “other poly edges close to diff”
ope_cd = other_poly_edges.separation(diff.edges,
min_poly_ext_over_diff, projection).first_edges

r_poly_x2 = ope_cd.interacting(poly_gate_edges)
r_poly_x2.output("POLY_X2: poly extension over gate < 0.25 µm")

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 Combined Operations II
Example How this works:
● A “width” measurement creates
markers for narrow metal.
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“projection” ensures the

markers are well-formed
(perpendicular to the original
Implementation edges).

# ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­
● The “polygons” operation will
# METAL2_SW turn the markers back into
min_metal2_s = 700.nm polygons.
FSiC 2019

min_metal2_wide_w = 3.um
● A NOT operation forms the
narrow_metal2_markers =
metal2.width(min_metal2_wide_w, projection) polygons that represent wide
metal.
wide_metal2 = metal2 ­ narrow_metal2_markers.polygons

wide_metal2_edges = wide_metal2.edges
● Using these markers the metal2
narrow_metal2_edges = metal2.edges – wide_metal2_edges edges are separated into edges
r_metal2_sw = wide_metal2_edges
for wide metal and narrow
.separation(narrow_metal2_edges, min_metal2_s) metal. A “separation”
measurement implements the
r_metal2_sw.output("METAL2_SW: metal2 space < 0.7 µm
for wide metal1 (>= 3 µm) to narrow/wide") check.
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 Combined Operations II
Example How this works:
● The “area” method computes
Implementation the physical area counting
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# ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ multiple coverage once.

# METAL1_x
● The “border” marking layer is
min_metal1_dens = 0.2
max_metal1_dens = 0.8 taken for reference. It’s area
must be > 0 to avoid division
metal1_area = metal1.area
border_area = border.area
by zero. The area is a float, so
if border_area >= 1.dbu * 1.dbu the compare should not be
done against 0, but against a
r_min_dens = polygon_layer
very small positive value.
FSiC 2019

r_max_dens = polygon_layer

dens = metal1_area / border_area ● Compute the density from the

ds = '%.2f' % (dens * 100)
area ratio and produce markers
if dens < min_metal1_dens based on the results.
r_min_dens = border # use border as marker
end
if dens > max_metal1_dens
r_max_dens = border # use border as marker
end

r_min_dens.output("METAL1_Xa: metal1 density (#{ds}) below threshold of #20%")

r_max_dens.output("METAL1_Xb: metal1 density (#{ds}) above threshold of #80%")

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 Global Operations
Example How this works:
● We kept a list of variable
names (not the layers itself!)
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Implementation in “all_drawing” at the

beginning of the file. Keeping
# ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ names instead of layers
# ONGRID
means we can output their
grid = 5.nm names in the message.
# we kept a list of all original layer’s variable
# names in “all_drawing” ● This check is supposed to
all_drawing.each do |dwg| apply to all layers. We can
iterate over all variable
FSiC 2019

# a Ruby idiom to get the value of a

# variable whose name is in "dwg" (as symbol) names, get the layer object
layer = binding.local_variable_get(dwg)
and run the “ongrid” check.
r_grid = layer.ongrid(grid).polygons(10.nm)
r_grid.output("GRID: vertexes on layer #{dwg} ● “ongrid” produces very small
not on grid of 5 nm")
markers (dot-like edge pairs).
end Converting them to polygons
with some minimum size (10
nm) enhances visibility.

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 Advanced Topics

● Raw and clean mode

– Shapes are automatically merged by default (“clean mode”)
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– To address individual shapes, put an original layer into “raw”

mode with the same method
● Tiling
– By default, all operations will be performed on big, single sets of
polygons, edges or edge pairs
FSiC 2019

– This can lead to memory peaks

– With tiling mode, the layout is cut into rectangular parts with a
given size (one tile if the layout is smaller) and the engine works
on the tiles one by one
– This mode also supports distribution to multiple cores

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More details: https://www.klayout.de/doc-qt4/manual/drc_runsets.html
 DRC Batch Mode

● Two formats: .drc (plain text), .lydrc (XML)

● Plain text is easier to write with a text editor
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● In batch mode, input and output files need to be specified:

# At the beginning of the script use:
source($input)
report("DRC report", $output)

Set the “input” and “output” variables in the klayout batch mode (“-
b”) call:
FSiC 2019

klayout ­b \
­rd input=myfile.gds \
­rd output=drc_result.lyrdb \
­r rules.drc

●
To review the results:
klayout myfile.gds ­m drc_result.lyrdb

●
Use “verbose” to get a log, use “puts” to print your own messages
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 Online Resources

● Documentation links:
https://www.klayout.de/doc-qt4/manual/drc.html
16/03/19

DRC method references:

https://www.klayout.de/doc-qt4/about/drc_ref.html

● For development master (future version):

http://www.klayout.org/downloads/master/doc-qt5/manual/drc.html
FSiC 2019

DRC method references:

http://www.klayout.org/downloads/master/doc-qt5/about/drc_ref.html

● Description of KLayout’s marker DB format:

https://www.klayout.de/rdb_format.html

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 Layout to Netlist and Deep
Mode
This chapter will tell you ...

A lot about
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A little bout
D e e p D RC m o d e layout and
connectivity
FSiC 2019

m e p re li m in a ry
re ab o u t So
Ev e n m o
information –
layout and watch for this:
devices
rk in progress!
This is wo

33 / 62
 Disclaimer

The Layout To Netlist feature is still under

development. If you want to try it you’ll need
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the lastet development version:

Binaries (look for version 0.26) from

FSiC 2019

http://www.klayout.org/downloads/master/
Sources from
https://github.com/klayout/klayout
Blog
https://github.com/klayout/klayout/wiki/Deep-Verification-Base

34 / 62
 Deep Mode

● Deep mode is a general add-on to DRC that

enables hierarchical operations
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(development branch only)

● This mode is strongly recommended as
otherwise the netlist does not have a
subcircuit structure
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● Deep mode is enabled by putting the

“deep” statement in front of the script
● “Hierarchical mode” means: perform
operations in subcells if possible.
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 Deep vs. Flat Mode
Flat Mode Deep Mode
Render the same image
diff = input(2,0) when seen from the top cell ... deep
poly = input(5,0) diff = input(2,0)
(diff – poly).output(...) poly = input(5,0)
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(diff – poly).output(...)
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... but only deep mode

leaves the source/drain
shapes in their cells.

Devices can be assigned

to these cells / circuits.
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 Deep Mode Limitations

● Most operations are available in deep mode,

but:
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– Tiling is not compatible with deep mode

– Currently there is no multi-core support
– No raw mode – clean mode is implied
FSiC 2019

– Some operations will create cell variants

rog re s s !
i s wo rk in p
37 / 62 This
 DRC/Netlisting Crossover:
Antenna Check
● The antenna effect is the accumulation of charge during
plasma etch resulting in a potential damage or degradation of
gate oxide
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potential
gate oxide
damage
FSiC 2019

● The risk is measured in terms of antenna ratio (metal area /

gate area) on each connected cluster. Bigger ratio = higher
risk.
● For this you need to derive the net clusters – a typical
38 / 62 netlisting act.
 Steps to Transform a
Layout to a Netlist
● Device recognition
– Identify devices and produce markers for the device terminals. The
16/03/19

netlister will later connect to the devices through these markers.

● Netlisting
– Trace the wires through the connections made over vias and between
shapes on the same layers. All connected shapes form one net.
– Include terminal shapes of the devices and use the information from
these shapes to identify the device and the terminal it is connected to
FSiC 2019

this net.
– Trace nets over hierarchy: form connections between cells. Connections
between cells are called pins.
● Netlist formation and simplification
– From the nets, pins and device terminals form the hierarchical netlist
graph
– Simplify the netlist by device combination, elimination of empty instances
(e.g. vias) and removal of floating nets
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 Running The Netlister

● Most of the netlisting part is now available

as a special feature set of the DRC script
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framework
● After the netlist has been built, you can
– Use it inside DRC for antenna checking
FSiC 2019

– Write the netlist to a file in Spice format

– For the advanced user: Use the Ruby
netlist API to access the netlist and the
LayoutToNetlist database (links layout to
nets)
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 Yet To Do / Plan

● A netlist viewer / browser, analogous to the

DRC marker browser
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● Closing the verification loop with a netlist-

vs-netlist compare
● Enhanced integration of netlisting feature
into a script language and provide as “LVS”
FSiC 2019

feature parallel to DRC

41 / 62
 Example (same as for DRC)

● Repo at
16/03/19

https://github.com/klayoutmatthias/si4all
● Clone with git
git clone https://github.com/klayoutmatthias/si4all.git

● Or download as zip
FSiC 2019

https://github.com/klayoutmatthias/si4all/archive/master.zip

● Design manual link

https://github.com/klayoutmatthias/si4all/blob/master/dm.pdf

● Netlist specific samples in this package:

Extraction Script: drc/netlist.lydrc
Layout: ringo.gds
42 / 62
 Example Layout
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FSiC 2019

ENABLE
OUT

FB
43 / 62
 Anatomy of a Netlister
Script
● Input phase
– Fetch the original layers
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● Derived layer computation

– E.g. source/drain area is “diffusion – poly”
● Device extraction
Derive the device instances and place terminal
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–
markers on specific layers
● Network formation
– Specify connections between conducting layers
● Netlist simplification (optional)
● Netlist output
44 / 62
 Netlist Script Anatomy:
Input Phase
How this works:
Sample:
● “deep” enables hierarchical
# Hierarchical extraction
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mode which is recommended

deep
for netlisting (otherwise the
netlist will be flat)
# Drawing layers
● “input” reads layers from the
nwell = input(1, 0) layout as in DRC
diff = input(2, 0)
pplus = input(3, 0)
● In contrast to DRC, labels are
important for netlist extraction
FSiC 2019

nplus = input(4, 0)
poly = input(5, 0) as they add names to nets.
thickox = input(6, 0) “input” pulls both polygons and
polyres = input(7, 0) texts, although formally the
contact = input(8, 0) resulting layer will be a polygon
metal1 = input(9, 0)
via = input(10, 0)
layer.
metal2 = input(11, 0)
To only pull polygons, use
“polygons” instead of “input”.
To only pull labels use “labels”.

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 Netlist Script Anatomy:
Derive Computed Layers
How this works:
Sample:
● The “bulk” layer is a virtual
bulk = make_layer
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layer representing the

diff_in_nwell = diff & nwell substrate (bulk) of the wafer.
pdiff = diff_in_nwell ­ nplus It’s required for the device
ntie = diff_in_nwell & nplus extraction. There is no layout
pgate = pdiff & poly for this, so we create an empty
psd = pdiff ­ pgate
hv_pgate = pgate & thickox
layer with “make_layer” (don’t
lv_pgate = pgate ­ hv_pgate use “polygon_layer” as this one
hv_psd = psd & thickox is flat)
FSiC 2019

lv_psd = psd ­ thickox

● The other layers are derived
diff_outside_nwell = diff ­ nwell purely with boolean operations.
ndiff = diff_outside_nwell ­ pplus
ptie = diff_outside_nwell & pplus
ngate = ndiff & poly
nsd = ndiff ­ ngate
hv_ngate = ngate & thickox
lv_ngate = ngate ­ hv_ngate
hv_nsd = nsd & thickox
lv_nsd = nsd ­ thickox

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 Which Layers are
Computed? N-TIEDOWN ntie
lv_ngate
LVPMOS lv_pgate LVNMOS
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lv_psd lv_nsd

HVNMOS P-TIEDOWN ptie

FSiC 2019

HVPMOS hv_pgate hv_ngate

47 / 62
hv_psd hv_nsd
 Netlist Script Anatomy:
Device Extraction
Sample: How this works:

# PMOS transistor device extraction

● The device extraction is
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delegated to device-specific
hvpmos_ex = classes. “Device extractors” are
RBA::DeviceExtractorMOS4Transistor::new("HVPMOS")
instances of those classes.
extract_devices(hvpmos_ex, Some classes are provided by
{ "SD" => psd, "G" => hv_pgate,
"P" => poly, "W" => nwell }) KLayout. More classes can be
defined in Ruby code. Device
lvpmos_ex = extractors identify devices from
RBA::DeviceExtractorMOS4Transistor::new("LVPMOS")
shape clusters, deliver the
FSiC 2019

extract_devices(lvpmos_ex, terminal shapes and the device

{ "SD" => psd, "G" => lv_pgate,
"P" => poly, "W" => nwell }) parameters measured from the
shapes.
# NMOS transistor device extraction
● “extract_devices” implements
lvnmos_ex =
RBA::DeviceExtractorMOS4Transistor::new("LVNMOS") device extraction. The hash
provided lists device
extract_devices(lvnmos_ex,
{ "SD" => nsd, "G" => lv_ngate, recognition layers against
"P" => poly, "W" => bulk }) device class specific symbols.
...
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 What the Device Extractor
does
lvpmos_ex = NOTE: no terminals are created
RBA::DeviceExtractorMOS4Transistor::new("LVPMOS") on the “G” layer – this layer is input
only!
extract_devices(lvpmos_ex,
{ "SD" => psd, "G" => lv_pgate,
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"P" => poly, "W" => nwell })

Sent to “P” layer
as terminal for “Gate”
(“P” is output only)
G
lv_pgate

Sent to “W” layer

as terminal for “Bulk”
(“W” is output only)
B
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Sent to “SD” layer

S D as terminal for “Source”
and “Drain”
(“SD” is input and output)

lv_psd M$1 S G D B MLVPMOS Device instance

+ L=0.25U Gate shape length and width
+ W=1.5U
+ AS=0.6375U AD=0.6375U source/drain area
+ PS=3.85U PD=3.85U source/drain perimeter
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 Netlist Script Anatomy:
Network Formation
Sample: How this works:

# Define connectivity for netlist extraction

● “connect” forms a connection
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between two layers. The layers

# Inter­layer
connect(contact, ntie)
can be original layers or
connect(contact, ptie) computed layers. Labels on
connect(nwell, ntie)
connect(psd, contact)
those layers will be taken as
connect(nsd, contact) (hierarchy-local) net names.
connect(poly, contact) Pure label layers can be
connect(contact, metal1)
connect(metal1, via) included as well for the purpose
connect(via, metal2) of assigning net names.
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# Global connections
● “connect_global” will make
# ptie will make an explicit connection to “BULK” connections of the named
# (the substrate)
connect_global(ptie, "BULK") global nets. Global nets
automatically make
# “bulk” is the layer introduced so the n­MOS
# transistory can produce “B” terminals. These
connections between across
# need to be connected to the global “BULK” net too. cells.
connect_global(bulk, "BULK")
● Note that the device terminal
shapes need to be included too
(device extractor output layers)
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 Connectivity Visualized
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METAL2

VIA

METAL1

CONTACT CONTACT CONTACT CONTACT CONTACT

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NTIE PTIE NSD PSD POLY

NWELL BULK (global) SD SD

P
P
W W

NMOS NMOS

Device connections through terminals

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 Netlist Script Anatomy:
Netlist Simplification
Sample: How this works:

# Compute the netlist:

● “l2n_data” gives access to the
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# This will trigger the actual netlisting Layout-to-netlist database.

# process!
netlist = l2n_data.netlist
“netlist” is the netlist object.
netlist.combine_devices ● “combine_devices” creates
netlist.make_top_level_pins
netlist.purge
single devices from multi-finger
netlist.purge_nets transisors, parallel or serial
resistors etc.

“make_top_level_pins” creates
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pins on the top level circuit for

named nets (those with a label)
● “purge” purges all empty
subcircuits (created from via
cells for example)
● “purge_nets” purges all floating
nets

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 Netlist Script Anatomy:
Netlist Output
Sample: How this works:

writer = RBA::NetlistSpiceWriter::new
● The “NetlistSpiceWriter” class
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provides the spice format writer

path = "ringo_simplified.cir”
netlist.write(path, writer, "Netlist comment")
(no other format available
currently)
● This object also allows
customizing the output through
a “delegate”

“netlist.write” will write the

FSiC 2019

rog res s ! netlist to the given file. The

i s wo r k in p other arguments to “write” are

This the writer object and a
comment to include in the
netlist

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 Simulating the Netlist

● Our netlist lacks parasitic R/C elements

We cannot expect realistic results, but still
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check the functionality

Testbench:
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* 180nm models from

* http://ptm.asu.edu/modelcard/180nm_bulk.txt:
.INCLUDE "models.cir"

.INCLUDE "ringo_simplified.cir"

VDD VDD 0 1.8V

VPULSE EN 0 PULSE(0,1.8V,1NS,1NS)

XRINGO FB VDD OUT EN 0 RINGO

.TRAN 0.01NS 100NS

.PRINT TRAN V(EN) V(FB) V(OUT)

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 L2N Database

● The LayoutToNetlist database is an object providing:

The geometry of the nets
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– The Netlist object for the extracted netlist (schematic)

– Serialization and deserialization (Open question: good
format for this purpose?)
● It offers an API for retrieving the geometry for a given net
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● The netlist itself is accessed through the Netlist API

● Further information here:
https://www.klayout.org/downloads/dvb/doc-qt5/code/class_LayoutToNetlist.html

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 L2N Scripting Examples

● Retrieve the flat shapes for a certain net

inside a DRC script:
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# Gets the Circuit object for the top level cell

top_circuit = l2n_data.netlist.circuit_by_name(source.layout.top_cell.name)

# Finds the Net object for the "VDD" net

net = top_circuit.net_by_name("VDD")

# outputs the shapes for this net to layers 2000 (ntie), 2001 (ptie), 2002 (nwell)
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# etc ...
{ 2000 => ntie, 2001 => ptie,
2002 => nwell, 2003 => nsd,
2004 => psd, 2005 => contact,
2006 => poly, 2007 => metal1,
2008 => via, 2009 => metal2 }.each do |n,l|
DRC::DRCLayer::new(self, l2n_data.shapes_of_net(net, l.data, true)).output(n, 0)
end

rog res s !
i s wo r k in p
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 L2N Scripting Examples

● Probe a net at a specific position:

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# This is where we want to probe

probe_point = RBA::DPoint::new(10.0.um, 7.0.um)

# Looks for a net at the given point on layer metal1

net = l2n_data.probe_net(metal1.data, probe_point)

# Prints the net name to the macro development IDE console:

net && puts("Net at #{probe_point}: #{net.name}")
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rog res s !
i s wo r k in p
57 / 62 This
 L2N Scripting Examples

● Dump all nets to cells “NET_...” with subcells

“CIRCUIT_...” for the subcircuits
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# build a map of layer indexes (in target layout) to layer objects

# (maps ntie to layer 2000, ptie to 2001, nwell to 2002 etc ...)
lmap = {}
{ 2000 => ntie, 2001 => ptie,
2002 => nwell, 2003 => nsd,
2004 => psd, 2005 => contact,
2006 => poly, 2007 => metal1,
2008 => via, 2009 => metal2 }.each do |n,l|
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lmap[source.layout.layer(n, 0)] = l.data

end

# builds the new hierarchy with the cells for nets and circuits
# CAUTION: this will modify the ORIGINAL layout!
cellmap = l2n_data.cell_mapping_into(source.layout, source.cell_obj)
l2n_data.build_all_nets(cellmap, source.layout, lmap, "NET_", "CIRCUIT_")

rog res s !
i s wo r k in p
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 Custom Device Extraction

● Right now, only a simple MOS (3 or 4

terminal) device recognition scheme is
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provided
● More will follow, but in general the
variability of devices is huge
e.g. capacitors come as metal plates,
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–
gate oxide caps, well capacitors, combs,
fingers, ...
● So KLayout provides a flexible recognition
scheme
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 Device Extraction Domain
Terminal Annotations

Connection Tracing
The device
extractor sees ...
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Original Layout
G B

S D

Netlist
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Device Instance
and produces ...

Device Extraction Domain

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 Flexibility: Device
Extractor Classes
● Device extraction for a specific kind of device is delegated to a
Device Extractor Class
● It is possible to implement a device extractor within DRC’s Ruby code
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based on RBA::GenericDeviceExtractor
● For example see
– Doc: http://www.klayout.org/downloads/master/doc-
qt5/code/class_GenericDeviceExtractor.html
– drc/custom_device.lydrc
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● A device extractor class needs to reimplement

– setup to define the layers involved
– get_connectivity to define the relationship between these
layers
– extract_devices to turn shapes on these layers into device
definitions and terminals
61 / 62 ● For more details please see documentation and sample code
 That’s it for now ...

Thank you
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for liste n in g !
:­)
FSiC 2019

[email protected] http://www.klayout.org
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