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MCQ On Computer Architecture

The document contains a series of multiple-choice questions (MCQs) focused on computer architecture concepts, including the Program Counter, memory types, pipelining, cache memory, and instruction sets. Each question is followed by the correct answer, covering topics such as RISC and CISC architectures, the function of CPU components, and various addressing modes. The document serves as a study guide for understanding fundamental principles of computer architecture.

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isha chatterjee
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50 views8 pages

MCQ On Computer Architecture

The document contains a series of multiple-choice questions (MCQs) focused on computer architecture concepts, including the Program Counter, memory types, pipelining, cache memory, and instruction sets. Each question is followed by the correct answer, covering topics such as RISC and CISC architectures, the function of CPU components, and various addressing modes. The document serves as a study guide for understanding fundamental principles of computer architecture.

Uploaded by

isha chatterjee
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Computer Architecture MCQ

1. What does the Program Counter (PC) hold?


A. The address of the next instruction to be executed
B. The result of the last operation
C. The base address of the stack
D. The value of the current instruction

Answer: A

2. Which of the following memory types is volatile?


A. ROM
B. Flash
C. RAM
D. EEPROM

Answer: C

3. What is pipelining in a CPU?


A. Executing multiple processes in parallel
B. Dividing memory into several parts
C. Overlapping the execution of multiple instructions
D. Multiplying pipeline registers

Answer: C

4. What is the main advantage of using cache memory?


A. It is non-volatile
B. It increases storage capacity
C. It is faster than main memory
D. It is cheaper than RAM

Answer: C

5. Which of the following is not a type of addressing mode?


A. Immediate
B. Direct
C. Indirect
D. Abstract

Answer: D
6. In a Von Neumann architecture, which unit performs both instruction fetch
and data operation?
A. ALU
B. Control Unit
C. Memory
D. CPU

Answer: D

7. What does CPI stand for in performance evaluation?


A. Cycles per Instruction
B. Clock per Instruction
C. Cycles per Interval
D. Clock Performance Index

Answer: A

8. Which logic gate is used in the construction of a full adder?


A. OR
B. AND
C. XOR
D. All of the above

Answer: D

9. RISC architecture is characterized by:


A. Complex instruction set
B. Multiple cycles per instruction
C. Few and simple instructions
D. Microprogramming

Answer: C

10. A cache hit occurs when:


A. Data is found in RAM
B. Data is found in secondary memory
C. Data is found in the cache
D. Data is not found in the cache

Answer: C
11. Which of the following architectures uses a single memory for both data and
instructions?
A. Harvard Architecture
B. Von Neumann Architecture
C. Modified Harvard Architecture
D. RISC Architecture

Answer: B

12. In which memory location are the operands stored in a stack-based


architecture?
A. Accumulator
B. Registers
C. Stack
D. Cache

Answer: C

13. Which of the following is not a feature of RISC architecture?


A. Simple instructions
B. Single-cycle execution
C. Complex instruction decoding
D. Load/Store architecture

Answer: C

14. What is the purpose of the Control Unit in the CPU?


A. Store data
B. Perform arithmetic
C. Decode and execute instructions
D. Manage input/output

Answer: C

15. Which component performs arithmetic and logic operations?


A. Register
B. ALU
C. CU
D. Memory Unit
Answer: B
16. Which of the following is not a stage in the instruction cycle?
A. Fetch
B. Decode
C. Execute
D. Interrupt

Answer: D

17. What does 'hazard' mean in pipelining?


A. Increase in clock speed
B. Data dependency issue
C. Instruction overflow
D. Control signal failure

Answer: B

18. What kind of memory is used for high-speed storage that sits between CPU
and main memory?
A. Register
B. DRAM
C. Cache
D. EEPROM

Answer: C

19. The number of bits processed in a single CPU cycle is determined by:
A. Word length
B. Instruction set
C. Address bus
D. Control unit

Answer: A

20. Instruction pipelining is used to:


A. Increase latency
B. Increase instruction execution time
C. Improve CPU throughput
D. Decrease the number of instructions

Answer: C

21. Which architecture uses separate memory for data and instructions?
A. Von Neumann Architecture
B. Harvard Architecture
C. RISC Architecture
D. CISC Architecture

Answer: B
22. What is the function of the ALU?
A. Controls the operation of the CPU
B. Stores instructions
C. Performs arithmetic and logic operations
D. Stores data temporarily

Answer: C

23. In pipelining, which hazard is caused by data dependencies?


A. Control hazard
B. Structural hazard
C. Data hazard
D. Memory hazard

Answer: C

24. What is the full form of RISC?


A. Reduced Instruction Set Computer
B. Random Instruction Set Computer
C. Recursive Instruction Set Computer
D. Rewritable Instruction Set Computer

Answer: A

25. The number of address lines determines:


A. Word size
B. Cache size
C. Memory size
D. Clock speed

Answer: C

26. Which type of memory is fastest?


A. DRAM
B. Cache
C. Hard Disk
D. ROM

Answer: B

27. Which of the following is not part of the CPU?


A. Control Unit
B. ALU
C. Register
D. RAM

Answer: D
28. Instruction cycle includes the following steps in order:
A. Decode → Fetch → Execute
B. Fetch → Decode → Execute
C. Execute → Decode → Fetch
D. Fetch → Execute → Decode

Answer: B

29. What is a register?


A. Slow storage
B. External memory
C. Temporary storage inside CPU
D. Permanent storage

Answer: C

30. Which is a characteristic of CISC architecture?


A. Few instructions
B. Simple instructions
C. Complex instructions
D. Fixed instruction size

Answer: C

31. Which of the following best describes instruction pipelining?


A. Execution of multiple instructions at once
B. Storing instructions for later use
C. Overlapping instruction stages to increase throughput
D. Preloading memory addresses

Answer: C

32. In RISC architecture, which statement is TRUE?


A. Instructions are complex and multi-cycle
B. Memory-to-memory operations are frequent
C. Each instruction is of a fixed size
D. Instructions are interpreted by microcode

Answer: C

33. Which of the following improves CPU performance?


A. Decreasing clock speed
B. Increasing CPI
C. Adding more registers
D. Using slower memory

Answer: C
34. What is the primary function of the control unit?
A. Execute instructions
B. Perform arithmetic
C. Fetch and decode instructions
D. Store data

Answer: C

35. Cache memory is placed between:


A. RAM and Hard Disk
B. CPU and RAM
C. ALU and Control Unit
D. CPU and I/O ports

Answer: B

36. The term ‘latency’ in memory refers to:


A. The total memory available
B. Delay before the transfer starts
C. Memory speed
D. Time taken to process an instruction

Answer: B

37. What is the function of the MAR (Memory Address Register)?


A. Stores data from memory
B. Holds the next instruction
C. Stores the address of data to be accessed
D. Controls memory timing

Answer: C

38. Which addressing mode uses a constant as part of the instruction?


A. Register
B. Direct
C. Indirect
D. Immediate

Answer: D

39. CISC processors are known for:


A. Few and simple instructions
B. Single-cycle execution
C. Multiple addressing modes and complex instructions
D. Minimal instruction formats

Answer: C
40. What causes a control hazard in pipelining?
A. Data dependency
B. Hardware limitations
C. Branch instructions
D. Memory faults

Answer: C

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