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Sequential Circuits

The document discusses the implementation of sequential functions using Mealy machines, emphasizing the importance of causal functions and finite memory. It details the state minimization process for Mealy machines, the implementation using logic gates, and the timing correctness requirements for ensuring accurate operation. Additionally, it outlines the design procedure and signoff specifications necessary for a CMOS positive-edge-triggered sequential circuit block.

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Shubham Gupta
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6 views5 pages

Sequential Circuits

The document discusses the implementation of sequential functions using Mealy machines, emphasizing the importance of causal functions and finite memory. It details the state minimization process for Mealy machines, the implementation using logic gates, and the timing correctness requirements for ensuring accurate operation. Additionally, it outlines the design procedure and signoff specifications necessary for a CMOS positive-edge-triggered sequential circuit block.

Uploaded by

Shubham Gupta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Sequential Circuits

Madhav Desai
February 12, 2017

1 Sequential Functions
A one-sided sequence from a finite set A is a set of elements
{x(0), x(1), x(2), . . .}
and is represented by {x(k)}. A sequential function f maps sequences to se-
quences:
f ({x(k)}) = {y(k)}
f is a causal sequential function if, given that
f ({x1 (k)}) = {y1 (k)}
f ({x2 (k)}) = {y2 (k)}
and that x1 (k) = x2 (k) for k ≤ M , it is also true that y1 (k) = y2 (k) for k ≤ M .
Simply put, the output at instant k should not depend on inputs at instants
greater than k.

2 Sequential Functions: Finite State Machines


Clearly, we can implement a sequential function only if it is causal. Further, we
can only implement a finite amount of memory. Thus, we need a general model
for sequential systems which has these two properties.
• We are interested in those implementations of causal sequential functions
that need a finite amount of memory.
• A Mealy machine (Q, Σ, Λ, δ, λ, q0 ∈ Q) is a system with an input sequence
{x(k)} with x(k) ∈ Σ, and output sequence {y(k)} with y(k) ∈ Λ, an
internal state sequence {q(k)} with q(k) ∈ Q, and the following relations
between the sequences {x(k)}, {y(k)} and {q(k)}.
q(0) = q0
q(k + 1) = δ(x(k), q(k))
y(k) = λ(x(k), q(k)
Here, Σ, Λ, Q are finite sets and δ, λ are functions from Σ × Q → Q and
Σ × Q → Λ respectively.

1
3 State Minimization of a Mealy Machine
In many cases, if we are given a Mealy FSM, we can reduce the number of states
without changing the behaviour of the state machine.
For an integer m ≥ 0, two states u, v are said to be m-compatible if it is
not possible to distinguish them using input sequences of length m. That is, for
k ≥ 0, the sequence of outputs y(k), y(k + 1), . . . y(k + m − 1) produced by an
input sequence x(k), x(k + 1), . . . x(k + m − 1) is the same if q(k) is either u or
v.
Then, the minimization procedure (described in Kohavi) proceeds as follows:

• Find the sets of 1-compatible states. This is easy, because u and v are
1-compatible if λ(u, σ) = λ(v, σ) for all σ ∈ Σ. We generate a collection
of subsets of 1-compatible states, which is a partition of the state space.

• Now for k > 1, we use induction. Assuming that we know the set of
1-compatibles and the set of (k − 1)−compatibles, the collection of k-
compatible sets can be built by noting that u and v are k-compatible if
they are 1-compatible, and further for each σ ∈ Σ, the states λ(u, σ) and
λ(v, σ) are (k − 1)-compatible.

• As soon as the set of k-compatibles converges (that is the set of k-compatibles


is the same as the set of (k − 1)-compatibles), we can stop. This conver-
gence will happen for some k ≤ (|Q| − 1) (why?). At the convergence
point, we have a collection of sets of compatible states.

• The reduced state machine can be constructed easily: The number of


states in the reduced state space is the size of the collection of compatible
sets. The transitions are built up in the obvious manner (how?).

One of the consequences of this procedure is that two incompatible states


in a Mealy FSM can be distinguished by an input sequence of length at most
|Q| − 1.

4 Implementing a Mealy Machine


Implementation of a Mealy machine using logic gates is easy.

• The sets Σ, Λ, Q are encoded with bit-vectors (note: there are many
possible encodings). After this step, x(k), y(k) and q(k) are viewed as
bit-vectors. Thus, δ and λ become Boolean functions which we know how
to implement as combinational functions. We implement the following

y(k) = λ(x(k), q(k))


nq(k) = δ(x(k), q(k))

where nq(k) is introduced to represent the next state.

2
• We need a concept of a sequential delay element to implement

q(k + 1) = nq(k)

• Some questions:
– How are the instants k defined?
– Using logic gates, how can we construct the delay element?
– Under what conditions will a logic circuit faithfully implement the
equations describing a Mealy machine?

4.1 Defining the time instants: a clock


To define the time instants k, we can use a periodic waveform, for example a
square wave, and associate the rising edges of the square wave with the time-
instants. The simplest clock is a square wave with 50% duty-cycle. We denote
the period of the clock by T .
If x is a wire in a logic circuit, then x(k) is the voltage on the wire at the
k th rising edge on the clock.

4.2 A delay element: the data flip-flop (DFF)


The data (or delay) flip-flop is a logic circuit which
• has two inputs: a data input d, a clock input clk, one output q.
• The d input is sampled at the rising edge of clock, and sampled value
appears at q after a delay (dclk→q ).
• The data input must be stable for a period S before the sampling clock
edge and a period H after the sampling clock edge (the setup time S and
the hold time H).

4.3 Implementation of a Mealy machine


The implementation of a Mealy machine then proceeds as follows:
• Encode the states in Q using a set of state variables s = (s0 s1 . . . sk ). You
will need at least log2 |Q| state variables.
• Encode the input and output symbol sets Σ and Λ using variables x =
(x0 x1 . . . xm ) and y = (y0 y1 . . . yp ) repectively.
• Implement the next-state and output functions λ and δ using logic gates.
• Use one flip-flop for each state variable and connect the next-state vari-
ables to the flip-flop inputs (outputs are connected to state variables).
The structure of the resultant circuit is shown in Figure 1

3
x(k) y(k)
lambda

(combinational logic)
s(k) ns(k)
delta

Clock

Figure 1: Mealy machine circuit structure

4.4 Timing correctness of a Mealy machine


For the implementation in Figure 1 to be faithful to the original model, we must
ensure that the D-flipflops will correctly sample the next-state values. That is,
the computation of the next-state values must be completed so that the correct
next-state value is stable during the flip-flop setup and hold window.
The computation of the next state value at time k starts from the clock
instant k − 1, and will take a certain amount of time to complete. The paths of
interest start from clock, proceed through a D-FF (the launch D-FF), continue
through combinational logic and end at the input of a D-FF (the capture D-
FF). Let m and M be the minimum and maximum possible delays of paths of
interest (including the Clock → Q delay of the launch flip-flop.
The circuit will correctly implement the Mealy machine if

m ≥ H
M ≤ T −S

If the clock at the capture flip-flop is delayed by an amount ∆ relative to


the clock at the launch flip-flop, then

m ≥ H +∆
M ≤ T − (S − ∆)

4.5 Summary: design procedure for a Mealy machine


• Choose input, state and output encodings.

– Some common encodings: binary and variants (e.g. Gray codes),


one-hot encodings, k-hot encodings etc.

4
• Implement the λ and δ function blocks.

• Introduce the delay elements to close the loop.

• Confirm that the circuit works correctly at some clock period (and calcu-
late the minimum clock period and circuit setup and delay times).

5 Signoff: Specification of a CMOS positive-


edge-triggered Sequential Circuit Block
To finish the design process, you must characterize your implementation and
find:

• The input set-up time relative to the rising edge of the clock (could be
different for each input).

• The minimum and maximum delays from an input of the system to an


input of a flip-flop (the input-to-flop delay, which could be different for
each input).

• The minimum and maximum values of the clock to output delay (could be
different for each output bit, both minimum and maximum delays should
be specified).

• The minimum and maximum values of the clock to flip-flop input delay.
• The minimum and maximum values of the input to output delay.

• For CMOS circuits, the input capacitance at all inputs (including clock)
and the maximum load capacitances that can be connected at the outputs.

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