Advanced Computer Architecture

MIPS
Instruction-Set Architecture
Instructor: Md. Abdur Razzak
 Topics
 Instructions & MIPS instruction set
 Where are the operands ?
 Machine language
 Assembler
 Translating C statements into Assembler
 For details see the book (ch 2):

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 Main Types of Instructions
 Arithmetic
 Integer
 Floating Point

 Memory access instructions

 Load & Store

 Control flow
 Jump
 Conditional Branch
 Call & Return

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 MIPS arithmetic
 Most instructions have 3 operands
 Operand order is fixed (destination first)

Example:

C code: A = B + C

MIPS code: add $s0, $s1, $s2

($s0, $s1 and $s2 are associated with variables by

compiler)

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 MIPS arithmetic

C code: A = B + C + D;
E = F - A;

MIPS code: add $t0, $s1, $s2

add $s0, $t0, $s3
sub $s4, $s5, $s0

 Operands must be registers, only 32 registers

provided
 Design Principle: smaller is faster. Why?

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 Registers vs. Memory
 Arithmetic instruction operands must be registers,
— only 32 registers provided
 Compiler associates variables with registers
 What about programs with lots of variables ?

CPU Memory
register file

IO
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 Register allocation
 Compiler tries to keep as many variables in registers
as possible

 Some variables can not be allocated

 large arrays (too few registers)
 aliased variables (variables accessible through pointers in C)
 dynamic allocated variables
 heap

 stack

 Compiler may run out of registers => spilling

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 Memory Organization
 Viewed as a large, single-dimension array, with an
address
 A memory address is an index into the array
 "Byte addressing" means that successive addresses
are one byte apart
0 8 bits of data

1 8 bits of data

2 8 bits of data

3 8 bits of data

4 8 bits of data

5 8 bits of data

6 8 bits of data

...
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 Memory Organization
 Bytes are nice, but most data items use larger "words"
 For MIPS, a word is 32 bits or 4 bytes.

0 32 bits of data

4 32 bits of data Registers hold 32 bits of data

8 32 bits of data

...
12 32 bits of data

 232 bytes with byte addresses from 0 to 232-1

 230 words with byte addresses 0, 4, 8, ... 232-4

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 Memory layout: Alignment
31 23 15 7 0
0 this word is aligned; the others are not!
4
8
address

12
16
20
24

Words are aligned

 What are the least 2 significant bits of a word
address?
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 Instructions: load and store
Example:

C code: A[8] = h + A[8];

MIPS code: lw $t0, 32($s3)

add $t0, $s2, $t0
sw $t0, 32($s3)

 Store word operation has no destination (reg) operand

 Remember arithmetic operands are registers, not
memory!

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 Our First C code translated
 Can we figure out the code?

swap(int v[], int k);

{ int temp;
temp = v[k]
v[k] = v[k+1];
v[k+1] = temp;
}
swap:
muli $2 , $5, 4
add $2 , $4, $2
lw $15, 0($2)
lw $16, 4($2)
sw $16, 0($2)
sw $15, 4($2)
jr $31
Explanation:
index k : $5
base address of v: $4
address of v[k] is $4 + 4.$5
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 So far we’ve learned:
 MIPS
— loading words but addressing bytes
— arithmetic on registers only

 Instruction Meaning

add $s1, $s2, $s3 $s1 = $s2 + $s3

sub $s1, $s2, $s3 $s1 = $s2 – $s3
lw $s1, 100($s2) $s1 = Memory[$s2+100]
sw $s1, 100($s2) Memory[$s2+100] = $s1

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 Machine Language: R-type instr
 Instructions, like registers and words of data, are also 32 bits long
 Example: add $t0, $s1, $s2
 Registers have numbers: $t0=9, $s1=17, $s2=18

 Instruction Format:

op rs rt rd shamt funct

000000 10001 10010 01000 00000 100000

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

Can you guess what the field names stand for?

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 Machine Language: I-type instr
 Consider the load-word and store-word instructions,
 What would the regularity principle have us do?
 New principle: Good design demands a compromise
 Introduce a new type of instruction format
 I-type for data transfer instructions
 other format was R-type for register
 Example: lw $t0, 32($s2)

35 18 9 32

op rs rt 16 bit number

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 Control
 Decision making instructions
 alter the control flow,
 i.e., change the "next" instruction to be executed

 MIPS conditional branch instructions:

bne $t0, $t1, Label

beq $t0, $t1, Label

 Example: if (i==j) h = i + j;

bne $s0, $s1, Label

add $s3, $s0, $s1
Label: ....

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 Control
 MIPS unconditional branch instructions:
j label
 Example:

if (i!=j) beq $s4, $s5, Lab1

h=i+j; add $s3, $s4, $s5
else j Lab2
h=i-j; Lab1:sub $s3, $s4, $s5
Lab2:...

 Can you build a simple for loop?

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 So far (including J-type instr):
 Instruction Meaning

add $s1,$s2,$s3 $s1 = $s2 + $s3

sub $s1,$s2,$s3 $s1 = $s2 – $s3
lw $s1,100($s2) $s1 = Memory[$s2+100]
sw $s1,100($s2) Memory[$s2+100] = $s1
bne $s4,$s5,L Next instr. is at Label if $s4 ° $s5
beq $s4,$s5,L Next instr. is at Label if $s4 = $s5
j Label Next instr. is at Label

 Formats:
R op rs rt rd shamt funct
I op rs rt 16 bit address

J op 26 bit address
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 Control Flow
 We have: beq, bne, what about Branch-if-less-than?
 New instruction:
meaning:
if $s1 < $s2 then
$t0 = 1
slt $t0, $s1, $s2 else
$t0 = 0

 Can use this instruction to build "blt $s1, $s2, Label"

— can now build general control structures

 Note that the assembler needs a register to do this,

— use conventions for registers

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 Used MIPS compiler conventions
Name Register number Usage
$zero 0 the constant value 0
$v0-$v1 2-3 values for results and expression evaluation
$a0-$a3 4-7 arguments
$t0-$t7 8-15 temporaries
$s0-$s7 16-23 saved (by callee)
$t8-$t9 24-25 more temporaries
$gp 28 global pointer
$sp 29 stack pointer
$fp 30 frame pointer
$ra 31 return address

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 Small Constants: immediates
 Small constants are used quite frequently (50% of operands)
e.g., A = A + 5;
B = B + 1;
C = C - 18;

 MIPS Instructions:

addi $29, $29, 4

slti $8, $18, 10
andi $29, $29, 6
ori $29, $29, 4

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 How about larger constants?
 We'd like to be able to load a 32 bit constant into a register
 Must use two instructions; new "load upper immediate"
instruction
lui $t0, 1010101010101010 filled with zeros
1010101010101010 0000000000000000

 Then must get the lower order bits right, i.e.,

ori $t0, $t0, 1010101010101010

1010101010101010 0000000000000000

0000000000000000 1010101010101010
ori
1010101010101010 1010101010101010

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 Assembly Language vs. Machine Language

 Assembly provides convenient symbolic representation

 much easier than writing down numbers
 e.g., destination first
 Machine language is the underlying reality
 e.g., destination is no longer first
 Assembly can provide 'pseudoinstructions'
 e.g., ―move $t0, $t1‖ exists only in Assembly
 would be implemented using ―add $t0,$t1,$zero‖
 When considering performance you should count real
instructions

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 Addresses in Branches and Jumps
 Instructions:
bne $t4,$t5,Label Next instruction is at Label if $t4  $t5
beq $t4,$t5,Label Next instruction is at Label if $t4 = $t5
j Label Next instruction is at Label

 Formats:

I op rs rt 16 bit address

J op 26 bit address

 Addresses are not 32 bits

— How do we handle this with load and store instructions?

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 Addresses in Branches
 Instructions:
bne $t4,$t5,Label Next instruction is at Label if $t4  $t5
beq $t4,$t5,Label Next instruction is at Label if $t4 = $t5
 Formats: use I-type

I op rs rt 16 bit address

 Could specify a register (like lw and sw) and add it to address

 use Instruction Address Register (PC = program counter)
 most branches are local (principle of locality)


Jump instructions just use high order bits of PC

 address boundaries of 256 MB

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 To summarize:
MIPS operands
Name Example Comments
$s0-$s7, $t0-$t9, $zero, Fast locations for data. In MIPS, data must be in registers to perform
32 registers $a0-$a3, $v0-$v1, $gp, arithmetic. MIPS register $zero alw ays equals 0. Register $at is
$fp, $sp, $ra, $at reserved for the assembler to handle large constants.
Memory[0], Accessed only by data transfer instructions. MIPS uses byte addresses, so
230 memory Memory[4], ..., sequential w ords differ by 4. Memory holds data structures, such as arrays,
words Memory[4294967292] and spilled registers, such as those saved on procedure calls.

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 To summarize:
MIPS assembly language
Category Instruction Example Meaning Comments
add add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; data in registers

Arithmetic subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; data in registers

add immediate addi $s1, $s2, 100 $s1 = $s2 + 100 Used to add constants
load word lw $s1, 100($s2) $s1 = Memory[$s2 + 100] Word from memory to register
store word sw $s1, 100($s2) Memory[$s2 + 100] = $s1 Word from register to memory
Data transfer load byte lb $s1, 100($s2) $s1 = Memory[$s2 + 100] Byte from memory to register
store byte sb $s1, 100($s2) Memory[$s2 + 100] = $s1 Byte from register to memory
load upper immediate lui $s1, 100 $s1 = 100 * 2
16 Loads constant in upper 16 bits

branch on equal beq $s1, $s2, 25 if ($s1 == $s2) go to Equal test; PC-relative branch
PC + 4 + 100

branch on not equal bne $s1, $s2, 25 if ($s1 != $s2) go to Not equal test; PC-relative
PC + 4 + 100
Conditional
branch set on less than slt $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1; Compare less than; for beq, bne
else $s1 = 0

set less than slti $s1, $s2, 100 if ($s2 < 100) $s1 = 1; Compare less than constant
immediate else $s1 = 0

jump j 2500 go to 10000 Jump to target address

Uncondi- jump register jr $ra go to $ra For switch, procedure return
tional jump jump and link jal 2500 $ra = PC + 4; go to 10000 For procedure call
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 MIPS (3+2) addressing modes overview
1. Immediate addressing
op rs rt Immediate

2. Register addressing
op rs rt rd ... funct Registers
Register

3. Base addressing
op rs rt Address Memory

Register + Byte Halfword Word

4. PC-relative addressing
op rs rt Address Memory

PC + Word

5. Pseudodirect addressing
op Address Memory

PC Word

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 Intermezzo: another approach 80x86
see intel museum: www.intel.com/museum/online/hist_micro/hof

 1978: The Intel 8086 is announced (16 bit architecture)

 1980: The 8087 floating point coprocessor is added
 1982: The 80286 increases address space to 24 bits, +instructions
 1985: The 80386 extends to 32 bits, new addressing modes
 1989-1995: The 80486, Pentium, Pentium Pro add a few
instructions (mostly designed for higher performance)
 1997: Pentium II with MMX is added
 1999: Pentium III, with 70 more SIMD instructions
 2001: Pentium IV, very deep pipeline (20 stages) results in high freq.
 2003: Pentium IV – Hyperthreading
 2005: Multi-core solutions
 2008: Low power ATOM: about 1 Watt
 2009: Lincroft: integrated graphics

Note: AMD has competitive processors

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 A dominant architecture: 80x86
 See your textbook for a more detailed description

 Complexity:
 Instructions from 1 to 17 bytes long
 one operand must act as both a source and destination
 one operand can come from memory
 complex addressing modes
e.g., ―base or scaled index with 8 or 32 bit displacement‖

 Saving grace:
 the most frequently used instructions are not too difficult to
build
 compilers avoid the portions of the architecture that are slow

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 Starting a program
 Compile and Assemble C program

 Link
 insert library code
 determine addresses of data and instruction labels
 relocation: patch addresses

 Load into memory

 load text (code)
 load data (global data)
 initialize $sp, $gp
 copy parameters to the main program onto the stack
 jump to ‗start-up‘ routine
 copies parameters into $ai registers

 call main

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 Starting a program
C program

compiler

Assembly program

assembler

Object program (user module) Object programs (library)

linker

Executable

loader
Memory
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