Chapter 3

Basic Input/Output
 Chapter Outline
• Basic I/O capabilities of computers
• I/O device interfaces
• Memory-mapped I/O registers
• Program-controlled I/O transfers
• Interrupt-based I/O
• Exceptions
 Accessing I/O Devices
• Computer system components communicate
through an interconnection network
• Address space and memory access concepts
from preceding chapter also apply here
• Locations associated with I/O devices are
accessed with Load and Store instructions
• Locations implemented as I/O registers within
same address space  memory-mapped I/O
Input - Output Interface
• Input Output Interface provides a method for
transferring information between internal
storage and external I/O devices.
• Peripherals connected to a computer need
special communication links for interfacing
them with the central processing unit.
• The purpose of communication link is to
resolve the differences that exist between the
central computer and each peripheral.
The Major Differences are:-
• 1. Peripherals are electro mechnical and electromagnetic devices
and CPU and memory are electronic devices. Therefore, a
conversion of signal values may be needed.
• 2. The data transfer rate of peripherals is usually slower than the
transfer rate of CPU and consequently, a synchronization
mechanism may be needed.
• 3. Data codes and formats in the peripherals differ from the word
format in the CPU and memory.
• The operating modes of peripherals are different from each other
and must be controlled so as not to disturb the operation of other
peripherals connected to the CPU.

To Resolve these differences, computer systems include special

hardware components between the CPU and Peripherals to
supervises and synchronizes all input and out transfers
• These components are called Interface Units because they
interface between the processor bus and the peripheral devices.
 Input-output subsystems
• I/O devices are very important in the computer systems. They
provide users the means of interacting with the system. So there is
a separate I/O system devoted to handling the I/O devices.
• Input and output (I/O) devices allow us to communicate with the
computer system. I/O is the transfer of data between primary
memory and various I/O peripherals.
• Input devices such as keyboards, mice, card readers, scanners,
voice recognition systems, and touch screens enable us to enter
data into the computer.
• Output devices such as monitors, printers, plotters, and speakers
allow us to get information from the computer.
• These devices are not connected directly to the CPU. Instead,
there is an interface that handles the data transfers.
• This interface converts the system bus signals to and from a format
that is acceptable to the given device. The CPU communicates to
these external devices via I/O registers. ...
 I/O Device Interface
• An I/O device interface is a circuit between
a device and the interconnection network
• Provides the means for data transfer and
exchange of status and control information
• Includes data, status, and control registers
accessible with Load and Store instructions
• Memory-mapped I/O enables software to
view these registers as locations in memory
 Program-Controlled I/O
• Discuss I/O issues using keyboard & display
• Read keyboard characters, store in memory,
and display on screen
• Implement this task with a program that
performs all of the relevant functions
• This approach called program-controlled I/O
• How can we ensure correct timing of actions
and synchronized transfers between devices?
 I/O Bus and Interface Modules
The I/O bus is the route used for peripheral devices to interact
with the computer processor. A typical connection of the I/O bus
to I/O devices is shown in the figure.

• Each Interface decodes the address and control received from the I/O bus, interprets them for
peripherals and provides signals for the peripheral controller.
• Control command- A control command is issued to activate the peripheral and to inform it what
to do.
• Status command- A status command is used to test various status conditions in the interface and
the peripheral.
• Data Output command- A data output command causes the interface to respond by transferring
data from the bus into one of its registers.
• The I/O bus includes data lines, address lines, and
control lines.
• In any general-purpose computer, the magnetic disk,
printer, and keyboard, and display terminal are
commonly employed.
• Each peripheral unit has an interface unit associated
with it.
• Each interface decodes the control and address
received from the I/O bus.
• It can describe the address and control received
from the peripheral and supports signals for the
peripheral controller.
• It also conducts the transfer of information between
peripheral and processor and also integrates the
data flow.
• The I/O bus is linked to all peripheral interfaces
from the processor.
• The processor locates a device address on the
address line to interact with a specific device.
• Each interface contains an address decoder
attached to the I/O bus that monitors the address
lines.
• When the address is recognized by the interface, it
activates the direction between the bus lines and
the device that it controls.
• The interface disables the peripherals whose
address does not equivalent to the address in the
bus.
• In micro-computer base system, the only
purpose of peripheral devices is just to
provide special communication links for the
interfacing them with the CPU.
• To resolve the differences between peripheral
devices and CPU, there is a special need for
communication links.
An interface receives any of the following four commands
• Control − A command control is given to activate the
peripheral and to inform its next task. This control
command depends on the peripheral, and each
peripheral receives its sequence of control
commands, depending on its mode of operation.
• Status − A status command can test multiple test
conditions in the interface and the peripheral.
• Data Output − A data output command creates the
interface counter to the command by sending data
from the bus to one of its registers.
• Data Input − The data input command is opposite to
the data output command. In data input, the
interface gets an element of data from the peripheral
and places it in its buffer register.
 Memory mapped I/O and Isolated
I/O
• As a CPU needs to communicate with the
various memory and input-output devices (I/O)
as we know data between the processor and
these devices flow with the help of the system
bus. There are three ways in which system bus
can be allotted to them :
1.Separate set of address, control and data bus
to I/O and memory.
2.Have common bus (data and address) for I/O
and memory but separate control lines.
3.Have common bus (data, address, and control)
for I/O and memory.
Isolated I/O –
• Then we have Isolated I/O in which we Have
common bus(data and address) for I/O and
memory but separate read and write control
lines for I/O.
• So when CPU decode instruction then if data is
for I/O then it places the address on the
address line and set I/O read or write control
line on due to which data transfer occurs
between CPU and I/O.
• As the address space of memory and I/O is
isolated and the name is so.
• The address for I/O here is called ports. Here
we have different read-write instruction for both
I/O and memory.
Memory Mapped I/O –
• In this case every bus in common due to which the same
set of instructions work for memory and I/O.
• Hence we manipulate I/O same as memory and both have
same address space, due to which addressing capability of
memory become less because some part is occupied by
the I/O.
Isolated I/O Memory Mapped I/O
Memory and I/O have separate address
Both have same address space
space

Due to addition of I/O addressable

All address can be used by the memory
memory become less for memory

Separate instruction control read and Same instructions can control both I/O
write operation in I/O and Memory and Memory

In this I/O address are called ports. Normal memory address are for both

More efficient due to separate buses Lesser efficient

Larger in size due to more buses Smaller in size

It is complex due to separate logic is used Simpler logic is used as I/O is also treated
to control both. as memory only.
Mode of Transfer:
• The binary information that is received from an
external device is usually stored in the memory
unit.
• The information that is transferred from the CPU
to the external device is originated from the
memory unit.
• CPU just processes the information, but the
source and target is always the memory unit.
• Data transfer between CPU and the I/O devices
may be done in different modes.
• Data transfer to and from the peripherals may be
done in any of the three possible ways
1.Programmed I/O.
2.Interrupt- initiated I/O.
3.Direct memory access( DMA).
• Programmed I/O: It is due to the result of
the I/O instructions that are written in the
computer program.
• Each data item transfer is initiated by an
instruction in the program.
• Usually the transfer is from a CPU register
and memory.
• In this case it requires constant monitoring by
the CPU of the peripheral devices.
• Example of Programmed I/O: In this case, the
I/O device does not have direct access to the
memory unit.
• A transfer from I/O device to memory requires
the execution of several instructions by the
CPU, including an input instruction to transfer
the data from device to the CPU and store
instruction to transfer the data from CPU to
memory.
• In programmed I/O, the CPU stays in the
program loop until the I/O unit indicates that it
is ready for data transfer.
• This is a time consuming process since it
needlessly keeps the CPU busy.
• This situation can be avoided by using an
• Interrupt- initiated I/O: Since in the above
case we saw the CPU is kept busy
unnecessarily.
• This situation can very well be avoided by using
an interrupt driven method for data transfer.
• By using interrupt facility and special
commands to inform the interface to issue an
interrupt request signal whenever data is
available from any device.
• In the meantime, the CPU can proceed for any
other program execution. The interface
meanwhile keeps monitoring the device.
• Whenever it is determined that the device is
ready for data transfer it initiates an interrupt
request signal to the computer.
• Upon detection of an external interrupt signal
the CPU stops momentarily the task that it was
already performing, branches to the service
program to process the I/O transfer, and then
return to the task it was originally performing.
• The I/O transfer rate is limited by the speed with
which the processor can test and service a
device.
• The processor is tied up in managing an I/O
transfer; A number of instructions must be
executed for each I/O transfer.
• Direct Memory Access(DMA): The data
transfer between a fast storage media such as
magnetic disk and memory unit is limited by the
speed of the CPU.
• Thus we can allow the peripherals directly
communicate with each other using the
memory buses, removing the intervention of
the CPU.
• This type of data transfer technique is known
as DMA or direct memory access.
• During DMA the CPU is idle and it has no
control over the memory buses.
• The DMA controller takes over the buses to
manage the transfer directly between the I/O
devices and the memory unit.
• Bus Request : It is used by the DMA
controller to request the CPU to surrender the
control of the buses.
• Bus Grant : It is activated by the CPU to
Inform the external DMA controller that the
buses are in high impedance state and the
requesting DMA can take control of the
buses.
• Once the DMA has taken the control of the
buses it transfers the data. This transfer can
take place in many ways.
DMA Block Diagram
 DMA Mechanism
• DMA controller definition is, an external device that
is used to control the data transfer between memory
and I/O device without the processor involvement is
known DMA controller. This controller has the
capacity to access the memory directly to read or
write operations. DMA controller was implemented
by Intel for having very fast data transfer with less
utilization of the processor.
 How Does DMA Controller Work?
• The direct memory access controller produces memory addresses and it covers
numerous hardware registers that can be read & written through the CPU. These registers
mainly include a byte count, memory address & minimum of one or above control
registers. So based on the DMA controller features, these registers can select some
combination of source, destination, transfer direction, the transfer unit size & the number
of bytes to move within the single burst.
• To execute different operations like input (i/p), output (o/p), otherwise memory-to-
memory, the host processor initializes the controller by the number of words to transmit &
the memory address to utilize, then the CPU orders the peripheral device to start data
transfer.
• The DMA controller provides addresses & reads or writes control lines toward the
system memory. Every time, a data byte is arranged to be transmitted in between the
memory & peripheral device, the controller increases its inside address register until a
whole data block is transmitted.
• Types of DMA transfer using DMA controller(Data
transmission in DMA controller: )
• Burst Transfer :
DMA returns the bus after complete data transfer. A
register is used as a byte count, being decremented for
each byte transfer, and upon the byte count reaching
zero, the DMAC will release the bus.
• When the DMAC operates in burst mode, the CPU is
halted for the duration of the data transfer.
Steps involved are:
1. Bus grant request time.
2. Transfer the entire block of data at transfer rate of device
because the device is usually slow than the
speed at which the data can be transferred to CPU.
3. Release the control of the bus back to CPU
So, total time taken to transfer the N bytes
= Bus grant request time + (N) * (memory transfer rate) +
Bus release control time.
• Where,
• X µsec =data transfer time or preparation time
(words/block)
• Y µsec =memory cycle time or cycle time or
transfer time (words/block)
• % CPU idle (Blocked)=(Y/X+Y)*100
• % CPU Busy=(X/X+Y)*100
• Cyclic Stealing :
An alternative method in which DMA controller transfers
one word at a time after which it must return the control of
the buses to the CPU. The CPU delays its operation only
for one memory cycle to allow the direct memory I/O
transfer to “steal” one memory cycle.
Steps Involved are:
1. Buffer the byte into the buffer
2. Inform the CPU that the device has 1 byte to transfer (i.e. bus
grant request)
3. Transfer the byte (at system bus speed)
4. Release the control of the bus back to CPU.
• Before moving on transfer next byte of data, device
performs step 1 again so that bus isn’t tied up and
the transfer won’t depend upon the transfer rate of device.
So, for 1 byte of transfer of data, time taken by using cycle
stealing mode (T).
= time required for bus grant + 1 bus cycle to transfer data
+ time required to release the bus, it will be
NxT
• In cycle stealing mode we always follow pipelining
concept that when one byte is getting transferred then
Device is parallel preparing the next byte. “The
fraction of CPU time to the data transfer time” if asked
then cycle stealing mode is used.

• Where,
• X µsec =data transfer time or preparation time
• (words/block)
• Y µsec =memory cycle time or cycle time or transfer
• time (words/block)
• % CPU idle (Blocked) =(Y/X)*100
• % CPU busy=(X/Y)*100
• Transparent Mode
• This mode uses more time for transmitting data blocks;
however, it is also the most significant type of mode in the
overall performance of the system. In this mode, the DMA
controller transmits data simply whenever the CPU
executes operations that do not utilize the buses of the
system.
• The main benefit of this mode is that the CPU never
ends performing its programs & DMA transmits are free
in terms of time, whereas the drawback is that the
hardware requires to decide once the CPU is not utilizing
the buses of the system, which can be complex. So this is
also known as hidden DMA data transfer mode.
 Signaling Protocol for I/O Devices
• Assume that the I/O devices have a way to
send a ‘ready’ signal to the processor
• For keyboard, indicates character can be read
so processor uses Load to access data register
• For display, indicates character can be sent so
processor uses Store to access data register
• The ‘ready’ signal in each case is a status flag
in status register that is polled by processor
 Example I/O Registers
• For sample I/O programs that follow, assume
specific addresses & bit positions for registers
• Registers are 8 bits in width and word-aligned
• For example, keyboard has KIN status flag in
bit b1 of KBD_STATUS reg. at address 0x4004
• Processor polls KBD_STATUS register,
checking whether KIN flag is 0 or 1
• If KIN is 1, processor reads KBD_DATA register
 Wait Loop for Polling I/O Status
• Program-controlled I/O implemented with a
wait loop for polling keyboard status register:
READWAIT: LoadByte R4, KBD_STATUS
And R4, R4, #2
Branch_if_[R4]0 READWAIT
LoadByte R5, KBD_DATA
• Keyboard circuit places character in KBD_DATA
and sets KIN flag in KBD_STATUS
• Circuit clears KIN flag when KBD_DATA is read
 Wait Loop for Polling I/O Status
• Similar wait loop for display device:
WRITEWAIT: LoadByte R4, DISP_STATUS
And R4, R4, #4
Branch_if_[R4]0 WRITEWAIT
StoreByte R5, DISP_DATA
• Display circuit sets DOUT flag in DISP_STATUS
after previous character has been displayed
• Circuit automatically clears DOUT flag
when DISP_DATA register is written
 RISC- and CISC-style I/O Programs
• Consider complete programs that use polling
to read, store, and display a line of characters
• Each keyboard character echoed to display
• Program finishes when carriage return (CR)
character is entered on keyboard
• LOC is address of first character in stored line
• CISC has TestBit, CompareByte instructions
as well as auto-increment addressing mode
 Interrupts
• Drawback of a wait loop: processor is busy
• With long delay before I/O device is ready,
cannot perform other useful computation
• Instead of using a wait loop, let I/O device
alert the processor when it is ready
• Hardware sends an interrupt-request signal
to the processor at the appropriate time
• Meanwhile, processor performs useful tasks
 Example of Using Interrupts
• Consider a task with extensive computation
and periodic display of current results
• Timer circuit can be used for desired interval,
with interrupt-request signal to processor
• Two software routines: COMPUTE & DISPLAY
• Processor suspends COMPUTE execution to
execute DISPLAY on interrupt, then returns
• DISPLAY is short; time is mostly in COMPUTE
 Interrupt-Service Routine
• DISPLAY is an interrupt-service routine
• Differs from subroutine because it is executed
at any time due to interrupt, not due to Call
• For example, assume interrupt signal asserted
when processor is executing instruction i
• Instruction completes, then PC saved to
temporary location before executing DISPLAY
• Return-from-interrupt instruction in DISPLAY
restores PC with address of instruction i  1
 Issues for Handling of Interrupts
• Save return address on stack or in a register
• Interrupt-acknowledge signal from processor
tells device that interrupt has been recognized
• In response, device removes interrupt request
• Acknowledgement can be done by accessing
status or data register in device interface
• Saving/restoring of general-purpose registers
can be automatic or program-controlled
 Enabling and Disabling Interrupts
• Must processor always respond immediately
to interrupt requests from I/O devices?
• Some tasks cannot tolerate interrupt latency
and must be completed without interruption
• Need ways to enable and disable interrupts,
both in processor and in device interfaces
• Provides flexibility to programmers
• Use control bits in processor and I/O registers
 Event Sequence for an Interrupt
• Processor status (PS) register has IE bit
• Program sets IE to 1 to enable interrupts
• When an interrupt is recognized, processor
saves program counter and status register
• IE bit cleared to 0 so that same or other signal
does not cause further interruptions
• After acknowledging and servicing interrupt,
restore saved state, which sets IE to 1 again
 Handling Multiple Devices
• Which device is requesting service?
• How is appropriate service routine executed?
• Should interrupt nesting be permitted?
• How are two simultaneous requests handled?
• For 1st question, poll device status registers,
checking if IRQ bit for each device is set
• For 2nd question, call device-specific routine
for first set IRQ bit that is encountered
 Vectored Interrupts
• Vectored interrupts reduce service latency;
no instructions executed to poll many devices
• Let requesting device identify itself directly
with a signal or a binary code
• Processor uses info to find address of
correct routine in an interrupt-vector table
• Table lookup is performed by hardware
• Vector table is located at fixed address, but
routines can be located anywhere in memory
 Interrupt Nesting
• Service routines usually execute to completion
• To reduce latency, allow interrupt nesting
by having service routines set IE bit to 1
• Acknowledge the current interrupt request
before setting IE bit to prevent infinite loop
• For more control, use different priority levels
• Current level held in processor status register
• Accept requests only from higher-level devices
 Simultaneous Requests
• Two or more devices request at the same time
• Arbitration or priority resolution is required
• With software polling of I/O status registers,
service order determined by polling order
• With vectored interrupts, hardware must
select only one device to identify itself
• Use arbitration circuits that enforce desired
priority or fairness across different devices
 Controlling I/O Device Behavior
• Processor IE bit setting affects all devices
• Desirable to have finer control with separate
IE bit for each I/O device in its control register
• Such a control register also enables selecting
the desired mode of operation for the device
• Access register with Load/Store instructions
• For example interfaces, setting KIE or DIE to 1
enables interrupts from keyboard or display
 Processor Control Registers
• In addition to a processor status (PS) register,
other control registers are often present
• IPS register is where PS is automatically saved
when an interrupt request is recognized
• IENABLE has one bit per device to control if
requests from that source can be recognized
• IPENDING has one bit per device to indicate if
interrupt request has not yet been serviced
 Accessing Control Registers
• Use special Move instructions that transfer
values to and from general-purpose registers
• Transfer pending interrupt requests to R4:
MoveControl R4, IPENDING
• Transfer current processor IE setting to R2:
MoveControl R2, PS
• Transfer desired bit pattern in R3 to IENABLE:
MoveControl IENABLE, R3
 Examples of Interrupt Programs
• Use keyboard interrupts to read characters,
but polling within service routine for display
• Illustrate initialization for interrupt programs,
including data variables and control registers
• Show saving of registers in service routine
• Consider RISC-style and CISC-style programs
• We assume that predetermined location ILOC
is address of 1st instruction in service routine
 Multiple Interrupt Sources
• To use interrupts for both keyboard & display,
call subroutines from ILOC service routine
• Service routine reads IPENDING register
• Checks which device bit(s) is (are) set
to determine which subroutine(s) to call
• Service routine must save/restore Link register
• Also need separate pointer variable to indicate
output character for next display interrupt
 Exceptions
• An exception is any interruption of execution
• This includes interrupts for I/O transfers
• But there are also other types of exceptions
• Recovery from errors: detect division by zero,
or instruction with an invalid OP code
• Debugging: use of trace mode & breakpoints
• Operating system: software interrupt to enter
• The last two cases are discussed in Chapter 4
 Recovery from Errors
• After saving state, service routine is executed
• Routine can attempt to recover (if possible)
or inform user, perhaps ending execution
• With I/O interrupt, instruction being executed
at the time of request is allowed to complete
• If the instruction is the cause of the exception,
service routine must be executed immediately
• Thus, return address may need adjustment
 Concluding Remarks
• Two basic I/O-handling approaches:
program-controlled and interrupt-based
• 1st approach has direct control of I/O transfers
• Drawback: wait loop to poll flag in status reg.
• 2nd approach suspends program when needed
to service I/O interrupt with separate routine
• Until then, processor performs useful tasks
• Exceptions cover all interrupts including I/O