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Indian Institute of Technology Kharagpur

Course Name: VLSI PHYSICAL DESIGN

Assignment- Week 8
TYPE OF QUESTION: MCQ/MSQ/SA
Number of questions: 10 Total mark: 10 x 1 = 10
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QUESTION 1:
Consider an interconnection wire of length L = 20 units and width W = 6 units. If L changes to 30
units and W changes to 2 units, the resistance of the wire will increase by
a. 1.5 times
b. 3.0 times
c. 4.5 times
d. None of these.
Correct Answer: c

Detailed Solution: The resistance is directly proportional to L and inversely proportional to W.

Suppose, R = k.L/W.
In the first case, R1 = 20k / 6 = 10k/3
In the second case, R2 = 30k / 2 = 15k
Thus, R2/R1 = 15 * 3 /10 = 4.5
The correct option is (c).
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QUESTION 2:
Consider a parallel place capacitor with length, width and thickness as 10 units, 10 units and 2
units respectively. If the length and width changes to 6 units and the thickness changes to 3.6
units, the value of the capacitance will increase by
a. 2 times
b. 3 times
c. 4 times
d. None of these.
Correct Answer: d
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Detailed Solution: The capacitance is directly proportional to length L and width W, and
inversely proportional to thickness T. Suppose, C = kLW/T.
In the first case, C1 = 100k / 2 = 50k
In the second case, C2 = 36k / 3.6 = 10k
Hence, the capacitance value reduces by 5 times.
The correct option is (d).
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QUESTION 3:
Miller effect concerns the crosstalk between two lines X and Y. Which of the following will
result in maximum crosstalk effect?
a. Both X and Y switch in the same direction.
b. X and Y switch in opposite directions.
c. X does not change, but Y switches.
d. Both X and Y do not change.
Correct Answer: b

Detailed Solution: Maximum crosstalk occurs when the signal change between the two lines is
the maximum. This maximum happens when X and Y changes in opposite directions (say, +V1
and –V2), so that the effective difference is V1+V2.
The correct option is (b).
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QUESTION 4:
Which of the following wire capacitance values is the largest?
a. Polysilicon to substrate.
b. N+ diffusion to substrate.
c. Metal1 to substrate.
d. Metal2 to substrate.

Correct Answer: a

Detailed Solution: The maximum capacitance value is between polysilicon and substrate, which
follows from the table that has been provided in the slides.
The correct option is (a).
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Indian Institute of Technology Kharagpur

QUESTION 5:
How many transistors are required to construct a 4-input NAND gate in CMOS?
a. 4
b. 5
c. 6
d. 8

Correct Answer: d

Detailed Solution: For an n-input NAND gate, there are n pMOS transistors in parallel in the
pullup network, and n nMOS transistors in series in the pulldown network. So, total number of
transistors is 2n. Here, n=4, and so the number of transistors is 8.
The correct option is (d).
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QUESTION 6:
Which of the following layers is most suitable for routing power supply connections?
a. Polysilicon
b. Metal
c. Diffusion
d. None of these.

Correct Answer: b

Detailed Solution: The conductivity of the Metal layer is much better as compared to
Polysilicon or Diffusion. Hence, power supply connections are laid out on Metal lines.
The correct option is (b).
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QUESTION 7:
What is/are the advantages of using design rules in VLSI layout generation?
a. Reduces the chance of fabrication errors.
b. All feature geometries are in terms of the basic feature size.
c. Maximum speed of operation can be achieved.
d. All of these.

Correct Answer: a, b
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Detailed Solution: Across a wide range of fabrication technologies, lambda-based design rules
are applicable. This means that a design created for 25-micron technology, will also work
correctly for 18-micron technology, provided the design rules are followed. The correct options
are (a) and (b).
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QUESTION 8:
Crosstalk effect on a line carrying a signal can be controlled by:
a. Making the line wider.
b. Shielding it between parallel VDD and GND lines.
c. Making it run parallel to the aggressor line(s).
d. None of these.

Correct Answer: b

Detailed Solution: Shielding is a standard method to reduce the effect of crosstalk. Both (a) and
(c) will increase crosstalk effect.
The correct option is (b).
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QUESTION 9:
In 1½-dimensional compaction, an X-Y adjacency graph is used, where:
a. Two blocks have a vertical edge if they share a horizontal boundary.
b. Two blocks have a vertical edge if they share a vertical boundary.
c. Two blocks have a horizontal edge if they share a horizontal boundary.
d. None of these.

Correct Answer: a

Detailed Solution: The answer follows from the definition.

The correct option is (a).
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QUESTION 10:
What is/are the role of constraint graph in layout compaction?
a. It can specify connectivity constraints.
b. It can specify delay constrains.
c. It can specify separation constraints.
d. All of these.
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Indian Institute of Technology Kharagpur

Correct Answer: a, c

Detailed Solution: Constraint graphs can be used to generate both connectivity and separation
constraints between pairs of blocks. However, it does not maintain any information about
delay. The correct options are (a) and (c).
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