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Indian Institute of Technology Kharagpur

Course Name: VLSI PHYSICAL DESIGN

Assignment- Week 11
TYPE OF QUESTION: MCQ/MSQ/SA
Number of questions: 10 Total mark: 10 x 1 = 10
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QUESTION 1:
In a CMOS circuit, if the frequency of operation is increased 2 times, the power supply voltage is
reduced by 1.5 times, and load capacitance is increased 2 times, then the dynamic power
consumption will increase ___________ times.

Correct Answer: Range 1.700 to 1.800

Detailed Solution: In CMOS circuits, the dynamic power consumption is directly proportional
to VDD2, CL and f, where VDD is the power supply voltage, CL is the load capacitance, and f is the
frequency of operation. Suppose, for the original circuit, dynamic power consumption is:

P1 = k VDD2 CL f, where k is a constant.

For the modified circuit, the dynamic power consumption will be:

P2 = k (VDD / 1.5)2 x (2 x CL) x (2 x f) = 1.777 k VDD2 CL f

Thus, the dynamic power dissipation increases 1.777 times.

QUESTION 2:
If the signal probability of a node A is 0.6, the activity factor of the node will be _________.
Correct Answer: Range from 0.20 to 0.30

Detailed Solution: The activity factor is defined as = Pi (1-Pi), where Pi is the signal probability
of the node.
Thus, the activity factor = 0.6 x 0.4 = 0.24.

QUESTION 3:
Which of the following can be used to reduce power consumption in a CMOS circuit?
a. Reduce α.
b. Increase the load capacitance (CL).
c. Reduce the power supply voltage (VDD).
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d. Increase the clock frequency (f).

Correct Answer: a, c

Detailed Solution: The possible strategies to reduce power consumption can be to reduce α,
reduce load capacitance, reduce VDD, and reduce clock frequency.
Hence the correct answers are (a) and (c).
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QUESTION 4:
The dynamic power consumption of a CMOS gate occurs when:
a. Both the pull-up and pull-down networks of the gate are conducting in the
steady state.
b. The output of the gate changes state.
c. There is fluctuation in the power supply voltage.
d. Either the pull-up or the pull-down network is conducting in the stable state.
Correct Answer: b

Detailed Solution: The dynamic power consumption in a CMOS gate occurs when both the pull-
up and pull-down networks are momentarily ON while the output of the gate is in changing state.
The correct answer is (b).
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QUESTION 5:
Which of the following statement(s) is/are false for a glitch?
a. Glitch is a spurious transition in the output due to unbalanced path delays.
b. Glitch results in no additional power dissipation.
c. Glitch results in additional power dissipation.
d. Glitch is a spurious transition in the output due to balanced path delays.
Correct Answer: b, d

Detailed Solution: Glitch is a spurious transition in the output due to unbalanced path delays,
which also results in additional power dissipation.
Hence, the correct options are (b) and (d).
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QUESTION 6:
Which of the following scenarios will increase the performance of a circuit?
a. Increase the supply voltage without changing the operating frequency.
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b. Increase the operating frequency without changing the supply voltage.

c. Decrease the supply voltage without changing the operating frequency.
d. None of these.

Correct Answer: a, b

Detailed Solution: The performance of a circuit changes when either the supply voltage is
increased or the frequency of operation is increased.
The correct options are (a) and (b).
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QUESTION 7:
Which of the following strategies can reduce the leakage power in a CMOS gate?
a. Use dynamic threshold scaling.
b. Increase the size of the transistors.
c. Increase the frequency of operation.
d. Increase the operating voltage.

Correct Answer: a

Detailed Solution: Increasing the size of the transistors will increase the leakage power.
Similarly, increasing the frequency of operation will also increase the leakage power. One of the
methods of controlling leakage power is to use dynamic threshold scaling (transistors with high
threshold voltage has smaller leakage power).
Hence, the correct option is (a).
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QUESTION 8:
If 0.4, 0.7, 0.6 and 0.35 denote the probabilities that the inputs of a 4-input NOR gate are at
logic 0, then the probability that the gate output is at logic 1 is given by __________.
Correct Answer: Range from 0.050 to 0.060

Detailed Solution: The output of an NOR gate is 1 only when all the inputs are at 0.
Hence, the required probability = 0.4 x 0.7 x 0.6 x 0.35 = 0.058
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QUESTION 9:
If 0.4 and 0.7 denote the signal probabilities of the inputs of a 2-input OR gate, then the output
signal probability is given by __________.
Correct Answer: Range from 0.078 to 0.090
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Detailed Solution: The output signal probability of a OR gate = 1 – (1 – Pa).(1 – Pb).

Hence, the required probability = 1 – (0.6 x 0.3) = 0.82
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QUESTION 10:
Which of the following is/are true for clock gating?
a. It makes a circuit easily testable.
b. It reduces the power consumption.
c. For static timing analysis, race conditions are avoided.
d. It makes testing of circuit more difficult.

Correct Answer: b, d

Detailed Solution: Using clock gating, the clock signal is prevented from reaching some of the
circuit modules. Consequently, the power consumption for such modules will get drastically
reduced. It is in fact disadvantageous from testing point of view. Also, it does not have any
connection with race condition.
The correct options are (b) and (d).
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