Digital Logic Design

Combinational Logic
Sequential circuit design

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 Combinational Circuits

 Output is function of input only

i.e. no feedback

Combinational
n inputs • • m outputs
• Circuits •
• •


When input changes, output may change (after a delay)

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 Combinational Circuits

 Analysis
● Given a circuit, find out its function A
B
C
F1
?
A

● Function may be expressed as:

B
C
A
B
?
♦ Boolean function
A
F2
C

B
C

♦ Truth table

 Design
● Given a desired digital operation, determine its
circuit
● Function may be expressed as: ?
♦ Boolean function
♦ Truth table 2 / 65
 Analysis Procedure

 Boolean Expression Approach

A
B
F1
C T2=ABC
A T1=A+B+C
B T3=AB'C'+A'BC'+A'B'C
C
A
B F’2=(A’+B’)(A’+C’)(B’+C’)

A
F2
C
F2=AB+AC+BC
B
C
F1=AB'C'+A'BC'+A'B'C+ABC
F2=AB+AC+BC
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 Analysis Procedure

 Truth Table Approach A B C F1 F2

A =0 0 0
0 0 0 0 0
B =0
F1
C =0
001
A =0 0
B =0 0
C =0
010
1
A =0 0 011
B =0
100
A =0 0 0
F2
C =0
101
B =0 0
C =0 110
111

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 Analysis Procedure

 Truth Table Approach A B C F1 F2

A =0 0 0 0 0 0
0 1
B =0 0 0 1 1 0
F1
C =1
A =0 1
B =0 1
C =1
1
A =0 0
B =0

A =0 0 0
F2
C =1

B =0 0
C =1

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 Analysis Procedure

 Truth Table Approach A B C F1 F2

A =0 0 0 0 0 0
0 1
B =1 0 0 1 1 0
F1
C =0
0 1 0 1 0
A =0 1
B =1 1
C =0
1
A =0 0
B =1

A =0 0 0
F2
C =0

B =1 0
C =0

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 Analysis Procedure

 Truth Table Approach A B C F1 F2

A =0 0 0 0 0 0
0 0
B =1 0 0 1 1 0
F1
C =1
A =0
0 1 0 1 0
1 0
B =1 0 1 1 0 1
C =1
0
A =0 0
B =1

A =0 0 1
F2
C =1

B =1 1
C =1

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 Analysis Procedure

 Truth Table Approach A B C F1 F2

A =1 0 0 0 0 0
0 1
B =0 0 0 1 1 0
F1
C =0
A =1
0 1 0 1 0
1 1
B =0 0 1 1 0 1
C =0 1 0 0 1 0
1
A =1 0
B =0

A =1 0 0
F2
C =0

B =0 0
C =0

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 Analysis Procedure

 Truth Table Approach A B C F1 F2

A =1 0 0 0 0 0
0 0
B =0 0 0 1 1 0
F1
C =1
A =1
0 1 0 1 0
1 0
B =0 0 1 1 0 1
C =1 1 0 0 1 0
0
A =1 0 0 1
B =0
1 0 1

A =1 1 1
F2
C =1

B =0 0
C =1

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 Analysis Procedure

 Truth Table Approach A B C F1 F2

A =1 0 0 0 0 0
0 0
B =1 0 0 1 1 0
F1
C =0
A =1
0 1 0 1 0
1 0
B =1 0 1 1 0 1
C =0 1 0 0 1 0
0
A =1 1
B =1
1 0 1 0 1
1 1 0 0 1
A =1 0 1
F2
C =0

B =1 0
C =0

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 Analysis Procedure

 Truth Table Approach A B C F1 F2

A =1 0 0 0 0 0
1 1
B =1 0 0 1 1 0
F1
C =1
A =1
0 1 0 1 0
1 0
B =1 0 1 1 0 1
C =1 1 0 0 1 0
0
A =1 1
B =1
1 0 1 0 1
1 1 0 0 1
A =1 1 1
C =1
F2 1 1 1 1 1
B =1 1
C =1 B B
0 1 0 1 0 0 1 0
K map for f1 A 1 0 1 0 A 0 1 1 1
C C
K map for f2
F1=AB'C'+A'BC'+A'B'C+ABC F2=AB+AC+BC
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 Design Procedure

 Given a problem statement:

● Determine the number of inputs and outputs
● Derive the truth table
● Simplify the Boolean expression for each output
● Produce the required circuit

Example:
Design a circuit to convert a “BCD” code to “Excess 3” code

 4-bits  4-bits
 0-9 values
?  Value+3

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 Design Procedure

 BCD-to-Excess 3 Converter
C C
A B C D w x y z
1 1 1
0 0 0 0 0 0 1 1
1 1 1 1
0 0 0 1 0 1 0 0 B B
x x x x x x x x
0 0 1 0 0 1 0 1 A A
1 1 x x 1 x x
0 0 1 1 0 1 1 0
D D
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0 w = A+BC+BD x = B’C+B’D+BC’D’
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0 C C
1 0 0 0 1 0 1 1 1 1 1 1
1 0 0 1 1 1 0 0 1 1 1 1
1 0 1 0 x x x x x x x x
B x x x x
B
A 1 x x
A 1 x x
1 0 1 1 x x x x
1 1 0 0 x x x x D D
1 1 0 1 x x x x
1 1 1 0 x x x x y = C’D’+CD z = D’
1 1 1 1 x x x x 13 / 65
 Design Procedure

 BCD-to-Excess 3 Converter
A B C D w x y z A
0 0 0 0 0 0 1 1 w
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1 x
B
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1 C y
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
D z
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x w = A + B(C+D) y = (C+D)’ + CD
1 1 1 0 x x x x x = B’(C+D) + B(C+D)’ z = D’
1 1 1 1 x x x x 14 / 65
Design of Seven-Segment Decimal Display Decoder

a
w x y z abcdefg
w a
0 0 0 0 1111110 b
0 0 0 1 0110000 x c f b
? d g
0 0 1 0 1101101 y e
0 0 1 1 1111001 z f
g
0 1 0 0 0110011 e c
0 1 0 1 1011011 BCD code
0 1 1 0 1011111
0 1 1 1 1110000 y d
1 0 0 0 1111111 1 1 1
1 0 0 1 1111011 1 1 1
1 0 1 0 xxxxxxx x x x x
x
1 0 1 1 xxxxxxx w 1 1 x x
1 1 0 0 xxxxxxx z
1 1 0 1 xxxxxxx
1 1 1 0 xxxxxxx a = w + y + xz + x’z’ b=...
c=...
1 1 1 1 xxxxxxx
d=...
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 Design a Binary half Adder

 Half Adder x S
y HA
C
● Adds 1-bit plus 1-bit
● Produces Sum and Carry x
+ y
C = x.y ───
x y C S S = x xor y C S
0 0 0 0
0 1 0 1 x S
1 0 0 1
1 1 1 0
y C

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 Design a Full Binary Adder Circuit

 Full Adder x S
y FA
z C
● Adds 1-bit plus 1-bit plus 1-bit
● Produces Sum and Carry x
+ y
y + z
x y z C S ───
0 1 0 1
0 0 0 0 0 C S
0 0 1 0 1 x 1 0 1 0
z
0 1 0 0 1
S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
0 1 1 1 0 C = xy + xz + yz
y
1 0 0 0 1 0r
0 0 1 0 xy + x’yz + xy’z
1 0 1 1 0
x 0 1 1 1
1 1 0 1 0
z xy + z(x’y+y’x)
1 1 1 1 1 Xy+z(x XOR y)
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 Binary Adder
S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
 Full Adder = (xy’ + x’y).z’ + z(xy +x’y’)
= A.z’ + z.A’
x C = xy + xz + yz
y
z
x
y x
x z y
x S z S
y
z
x
x
x y
y y y
z x
x z C
y z
y
z x C
z
z
y
z

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 Binary Adder
(xy’ + yx’)’.z + (xy’ + yx’).z’
 Full Adder A = xy’ + yx’
A’.z + A.z’
x S
y HA HA
(xy’ + yx’).z
xy
z C
xy (xy’ + yx’).z + xy

x
S

y
C

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Practice question of combinational circuit

Design of half subtractor and Full

subtractor

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 Four Bits Binary Adder
Add A + B
x3x2x1x0 y3y2y1y0 A = x3 x2 x1 x0 c3 c 2 c1 .
B = y3 y2 y1 y0 + x3 x2 x1 x0
+ y3 y2 y1 y0
C4 Binary Adder C0 Carry ────────
Propagate C4 S3 S2 S1 S0
Addition
S3S2S1S0

x3 x2 x1 x0
y3 y2 y1 y0
0

FA FA FA FA

C4 C3 C2 C1
S3 S2 S1 S0
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 Disadvantage:
 Output is not stable unless MSB bits are added
There is a delay for stable correct output
 Delay = 4 times individual FA delay

Solution :
Parallel adder with look carry ahead:
All the four bits are added simultaneously

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 Binary Adder
25 0010 0 101
 Carry Propagate Adder
+14 0001 0100

x7 x6 x5 x 4 x3 x2 x1 x0
y7 y6 y5 y4 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 A0 B3 B2 B1 B0

Cy CPA C0 Cy CPA C0 0

S3 S2 S1 S0 S 3 S2 S1 S0

S7 S6 S5 S4 S3 S2 S1 S0

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 Carry propagation
● When the correct outputs are available
● The critical path counts (the worst case)
● (A1, B1, C1) → C2 → C3 → C4 → (C5, S4)
● When 4-bits full-adder → 8 gate levels (n-bits: 2n gate
levels)

Figure 4.10 Full Adder with P and G Shown

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 Parallel Adders

 Reduce the carry propagation delay

● Employ faster gates
● Look-ahead carry (more complex mechanism, yet faster)
● Carry propagate: Pi = AiBi
● Carry generate: Gi = AiBi
● Sum: Si = PiCi
● Carry: Ci+1 = Gi+PiCi
● C0 = Input carry
● C1 = G0+P0C0
● C2 = G1+P1C1 = G1+P1(G0+P0C0) = G1+P1G0+P1P0C0
● C3 = G2+P2C2 = G2+P2G1+P2P1G0+ P2P1P0C0

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 Carry Look-ahead Adder (1/2)
 Logic diagram

P0Co

P0C0 + G0

Fig. 4.11 Logic Diagram of Carry Look-ahead Generator

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 Carry Look-ahead Adder (2/2)

 4-bit carry-look
ahead adder
● Propagation delay
of C3, C2 and C1 are
equal.

Fig. 4.12 4-Bit Adder with Carry Look-ahead

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4 bit full adder IC

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4 bit full adder IC

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Addition of two decimal digits in BCD code :BCD Adder

 4-bits plus 4-bits + x3 x2 x1 x0

+ y3 y2 y1 y0
 Operands and Result: 0 to 9 ────────
Cy S3 S2 S1 S0
X +Y x3 x2 x1 x0 y3 y2 y1 y0 Sum Cy S3 S2 S1 S0
0+0 0 0 0 0 0 0 0 0 =0 0 0 0 0 0
0+1 0 0 0 0 0 0 0 1 =1 0 0 0 0 1
0+2 0 0 0 0 0 0 1 0 =2 0 0 0 1 0

0+9 0 0 0 0 1 0 0 1 =9 0 1 0 0 1
1+0 0 0 0 1 0 0 0 0 =1 0 0 0 0 1
1+1 0 0 0 1 0 0 0 1 =2 0 0 0 1 0

1+8 0 0 0 1 1 0 0 0 =9 0 1 0 0 1
1+9 0 0 0 1 1 0 0 1 =A 0 1 0 1 0 Invalid Code
2+0 0 0 1 0 0 0 0 0 =2 0 0 0 1 0

9+9 1 0 0 1 1 0 0 1 = 12 1 0 0 1 0 Wrong BCD Value

0001 1000 30 / 65
 BCD Adder

X +Y x3 x2 x1 x0 y3 y2 y1 y0 Sum Cy S3 S2 S1 S0 Required BCD Output Value

9+0 1 0 0 1 0 0 0 0 =9 0 1 0 0 1 0 0 0 0 1 0 0 1 =9
9+1 1 0 0 1 0 0 0 1 = 10 0 1 0 1 0 0 0 0 1 0 0 0 0 = 16 
9+2 1 0 0 1 0 0 1 0 = 11 0 1 0 1 1 0 0 0 1 0 0 0 1 = 17 
9+3 1 0 0 1 0 0 1 1 = 12 0 1 1 0 0 0 0 0 1 0 0 1 0 = 18 
9+4 1 0 0 1 0 1 0 0 = 13 0 1 1 0 1 0 0 0 1 0 0 1 1 = 19 
9+5 1 0 0 1 0 1 0 1 = 14 0 1 1 1 0 0 0 0 1 0 1 0 0 = 20 
9+6 1 0 0 1 0 1 1 0 = 15 0 1 1 1 1 0 0 0 1 0 1 0 1 = 21 
9+7 1 0 0 1 0 1 1 1 = 16 1 0 0 0 0 0 0 0 1 0 1 1 0 = 22 
9+8 1 0 0 1 1 0 0 0 = 17 1 0 0 0 1 0 0 0 1 0 1 1 1 = 23 
9+9 1 0 0 1 1 0 0 1 = 18 1 0 0 1 0 0 0 0 1 1 0 0 0 = 24 

1 1 0010
2 + 0110 +6
3 ---------------------
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Sum Ca S3 S2 S1 S0 Cb S3b S2b s1b s0b
0
1
2

10

11

12

13

14

15 32 / 65
 BCD Adder

 Correct Binary Adder’s Output (+6)

● If the result is between ‘A’ and ‘F’
● If Cy = 1

S3 S2 S1 S0 Err
0 0 0 0 0 00 01
11 S1 10

0 0 0 1 0 00
01
1 0 0 0 0 S2
1 1 1 1
1 0 0 1 0 S3 1 1
1 0 1 0 1
1 0 1 1 1
S0
Err = S3 S2 + S3 S1 + Cy
1 1 0 0 1
1 1 0 1 1 If Err = 0, nothing to be added to s3s2s1s0
1 1 1 0 1
If Err = 1, then add BCD code 0110 (6) to the
1 1 1 1 1
sum value
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 BCD Adder
x3 x2 x1 x0 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 0
S3 S2 S1 S0
Err

0 0

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 0
S3 S2 S1 S0

Cy S3 S2 S1 S0

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 4 bits Binary Subtractor

 Use 2’s complement with binary adder

● x – y = x + (-y) = x + y’ + 1, where 1 is carry at LSB bit
● We need to add four bits of x with 2’s complement of
four bits of y
● Four x bits are represented as x3 x2 x1 x0
● Four y bits are represented as y3 y2 y1 y0
● 2’s Complement of y = y3’ y2’ y1’ y0’ + 1
● 2 ‘s complement = 1’s complement + 1
● 1’s complement is obtained by inverting every bit of y

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 Hardware for Binary Subtractor

 Use 2’s complement with binary adder

● x – y = x + (-y) = x + y’ + 1, where 1 is carry at LSB bit
x3 x2 x1 x0 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 1
S3 S2 S1 S0

F3 F2 F1 F0

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 Combinational Ckt for Binary Adder/Subtractor

 M: Control Signal (Mode)

● M=0  F = x + y
● M=1  F = x – y x3 x2 x1 x0 y3 y2 y1 y0 M
1
XOR gate property
y0 = y , = y’0 + 0’.y = 0 + 1.y = y
y1 = y‘ = y’1 + y.1’ = y’ + y.0 = y’
So, y = y when M = 0
A3 A2 A1 A0 B3 B2 B1 B0
and
Cy Binary Adder Ci
y = y’ when M = 1 1
S3 S2 S1 S0

F3 F2 F1 F0

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 Over flow
 Addition of two n bits numbers results (n+1) bits
 This is true for both unsigned and signed number
 For unsigned number, end carry is the overflow bit
 For signed number MSB bit is the signed bit
 When two signed bits (both positive or both negative) are
added, there will be a overflow at the end carry (sign bit
position)
 The carry generated for addition of bits at end carry
position is overflow
 Over flow is indicated by XORing Carries at the end carry
input and output
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 Overflow

 Unsigned Binary Numbers

x x2 x1 x0
3
y3 y2 y1 y0
0

FA FA FA FA
Carry =
Overflow C S
4 C
S
C
3 S 3C
S 2
2
1
1
0

 2’s Complement Numbers (two signed numbers)

x3 x2 x1 x0
y3 y2 y1 y0
0

FA FA FA FA

Overflow C4 C3 C2 C1
S3 S2 S1 S0

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 Overflow for both unsigned and signed
numbers

x3 x2 x1 x0
y3 y2 y1 y0
0
Overflow
FA FA FA FA
for unsigned

Overflow for C4
S3
C3
S2
C2
S1
C1
S0

signed

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 Magnitude Comparator

 Compare 4-bit number to 4-bit number

● 3 Outputs: < , = , >
● Expandable to more number of bits

x3 = A3 B3  A3 B3 A3A2A1A0 B3B2B1B0

x2 = A2 B2  A2 B2
Magnitude
x1 = A1 B1  A1 B1 Comparator
x0 = A0 B0  A0 B0
A<B A=B A>B
( A = B ) = x3 x2 x1 x0
( A  B) = A3 B3  x3 A2 B2  x3 x2 A1 B1  x3 x2 x1 A0 B0
( A  B) = A3 B3  x3 A2 B2  x3 x2 A1 B1  x3 x2 x1 A0 B0
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Magnitude Comparator
A3
x3

B3

A2
x2

B2

A1 (A<B)
x1

B1

A0
x0 (A>B)

B0
(A=B)

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 Magnitude Comparator

x7 x6 x5 x 4 x3 x2 x1 x0
y7 y6 y5 y4 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 A0 B3 B2 B1 B0
0 I(A>B) I(A>B)
1
Magnitude Magnitude
I(A=B) I(A=B)
I(A<B)
Comparator I(A<B)
Comparator
0
A<B A=B A>B A<B A=B A>B

A<B A=B A>B

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 Decoders (CKT to Convert Binary Code to Discrete
Element of Information)

 Extract “Information” from the code Only one

lamp will
 Binary Decoder turn on
● Example: 2-bit Binary Number

2x4
00, 01, 10, 11

0 1
x1 0
Binary
x0 0 Decoder 0
0

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 Decoders

 2-to-4 Line Decoder

Y3

y3 Y2
Decoder
I1 Binary
y2
y1 Y1
I0 y0
Y0

I1 I0 Minterm Y3 Y2 Y1 Y0
I1
I0
0 0 m0 0 0 0 1
0 1 m1 0 0 1 0 Y3 = I1 I 0 Y2 = I1 I 0
1 0 m2 0 1 0 0
Y1 = I1 I 0 Y0 = I1 I 0
1 1 m3 1 0 0 0
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 Decoders

 3-to-8 Line Decoder Y7 = I 2 I1 I 0

Y7
Y6 = I 2 I1 I 0

Y6 Y5 = I 2 I1 I 0
Y5
Decoder

Y4 = I 2 I1 I 0
Binary

I2 Y4
I1 Y3 Y3 = I 2 I1 I 0
I0 Y2 Y2 = I 2 I1 I 0
Y1
Y0 Y1 = I 2 I1 I 0

Y0 = I 2 I1 I 0

I2
I1
I0
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 Decoders with enable input

 “Enable (E) ” Control Y3

Y3

Decoder
I1 Y2
Binary Y2
I0 Y1
E Y1
Y0
Y0
E I1 I0 Y3 Y2 Y 1 Y0
0 x x 0 0 0 0
I1
1 0 0 0 0 0 1 I0
E
1 0 1 0 0 1 0 Y0 = I1’I0’E
1 1 0 0 1 0 0 Y1= I’I0E
1 1 1 1 0 0 0 ---
Y3 47 / 65
 Decoders: Convert 2 x 4 decoder into 3 x 8 decoder
Decoder with enable input can be used to convert 2 x4 decoder to 3 x 8 decoder
I2 I1 I0
1 10
Expansion using 2 , 2 x 4 deocder , 3 x 8 decoder

I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Y3 Y7

Decoder
0 I0

Binary
0 0 0 0 0 0 0 0 0 0 1 Y2 Y6
I1 Y1 Y5
0 0 1 0 0 0 0 0 0 1 0
E Y0 Y4
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0 Y3 Y3

Decoder
I0

Binary
1 0 1 0 0 1 0 0 0 0 0 Y2 Y2
1 1 0 0 1 0 0 0 0 0 0 I1 Y1 Y1
1 1 1 1 0 0 0 0 0 0 0 E Y0 Y0
0
Two 3 x 8 decoder with E input can be used to convert 4
x 16 decoder 48 / 65
 Is it possible to make 4 x 16 decder using 2 x 4
decoder, using two 3 x 8 decoder

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 Decoders with low output
Active-High
I 1 I0 Y 3 Y 2 Y 1 Y 0
Y3

Decoder
0 0 0 0 0 1 I1

Binary
Y2
0 1 0 0 1 0 Y1
1 0 0 1 0 0 I0 Y0
1 1 1 0 0 0
Y3

 Active-Low Y2

I1 I0 Y 3 Y 2 Y 1 Y 0 Y3 Y1

I1 Decoder
Binary
0 0 1 1 1 0 Y2 Y0

0 1 1 1 0 1 Y1
I0 Y0 I1
1 0 1 0 1 1 I0

1 1 0 1 1 1
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 Combinational Circuit Implementation Using Decoders

 Each decoder output is a minterm

 Decoder produces all the minterms Binary 3 x 8
Decoder
 Sum the required minterms Y7
Any logic expression can be represented
Y6
by sum of minterms Y5
x I2 Y4
Example: Full Adder y I1 Y3
z I0 Y2
S(x, y, z) = ∑(1, 2, 4, 7)
Y1
S = m1 + m2 + m4 + m7 Y0
= Y1 + Y2 + Y4 + Y7
C(x, y, z) = ∑(3, 5, 6, 7)
C = Y3 + Y5 + Y6 + Y7 S C 51 / 65
 Full adder Implementation Using Decoders
Binary Binary
Decoder Decoder

Y7 Y7
Y6 Y6
Y5 Y5
x I2 Y4 x I2 Y4
y I1 Y3 y I1 Y3
z I0 Y2 z I0 Y2
Y1 Y1
Y0 Y0

S = (Y1’.Y2’.Y4’.Y7’)’
Y1 + Y2 + Y4 + Y7
S C
S C Applying Demorgan law
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Practice example: Combinational
circuit using decoder

 Design a Half subtractor,

Full subtractor,
 3 bit binary to gray code converter
 4 bit parity generator circuit , 3 x 8
decoder

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 Encoders
 Put “Information” into code form
Only one
It is reverse of decoder switch
should be
 Binary Encoder activated
at a time
● Example: 4-to-2 Binary Encoder
x1

x3 x2 x1 x0 y1 y0
x2 y1
Binary 0 0 0 1 0 0
Encoder 0 0 1 0 0 1
x3 y0
0 1 0 0 1 0
1 0 0 0 1 1

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 Encoders

 Octal-to-Binary Encoder (8-to-3)

I7
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0 I6
I5

Encoder
0 0 0 0 0 0 0 1 0 0 0 Y2

Binary
0 0 0 0 0 0 1 0 0 0 1 I4 Y1
0 0 0 0 0 1 0 0 0 1 0 I3 Y0
0 0 0 0 1 0 0 0 0 1 1 I2
0 0 0 1 0 0 0 0 1 0 0 I1
0 0 1 0 0 0 0 0 1 0 1 I0
0 1 0 0 0 0 0 0 1 1 0 I7
1 0 0 0 0 0 0 0 1 1 1 I6 Y2
I5
Y2 = I 7  I 6  I 5  I 4 I4
I3 Y1
Y1 = I 7  I 6  I 3  I 2 I2
I1
Y0 = I 7  I 5  I 3  I1 I0 Y0
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 Priority Encoders

 4-Input Priority Encoder

I3

Encoder
V

Priority
I3 I2 I 1 I0 Y1 Y0 V I2 Y1
0 0 0 0 0 0 0 I1 Y0
0 0 0 1 0 0 1 I0
0 0 1 x 0 1 1
0 1 x x 1 0 1 V is valid code
I3 Y0
1 x x x 1 1 1
I2
Y1 I1 I1
Y1 = I 3  I 2 Y1
1 1 1 1
1 1 1 1
I2 Y0 = I 3  I 2 I1
I3 I0 V
1 1 1 1
I0
V = I 3  I 2  I1  I 0

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 I3I2/I1I0 00 01 11 10

00 1 1

01

11 1 1 1 1

10 1 1 1 1

Y0 = I3 +I2’.I0

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Encoder / Decoder Pairs

Binary Binary
Encoder Decoder

I7 Y7
I6 Y6
I5 Y5
Y2 I2 Y4
I4 Y1 I1 Y3
I3 Y0 I0 Y2
I2
I1 Y1
I0 Y0

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Decoder (74LS138)and encoder IC (74148)

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Multiplexers

4 x 1 MUX
Input Select Y
inputs Two select inputs S0 and S1

S1 S0 I0 4 x 1 MUX
I0 0 0 I0 I1
MUX Y
I1 0 1 I1 I2
I3
I2 1 0 I2 S1 S0
I3 1 1 I3 60 / 65
 Multiplexers
2-to-1 MUX
I0
I0
MUX Y
I1 Y
S Input Y S
I1
0 I0 Y = I0
1 I1 Y = I1 S
I0
 4-to-1 MUX
I1
I0
Y
I1 I2
MUX Y
I2 I3
I3
S1 S0

Y = I 0 S0 S1  I1S0 S1  I 2 S0 S1  I1S0 S1 S1 S0
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 Multiplexers

 Quad 2-to-1 MUX A 3

Y3
A2
A3 I0 Y2
B3 MUX Y A1
I1 Y1
S
A0
Y0
A2 I0 B3
B2 MUX Y
I1
S B2
A3
B1 A2
A1 I0 A1
Y3
B1 MUX Y B0 A0
I1 Y
MUX 2
S Y1
B3 Y0
B2
A0 I0
MUX Y
S E
B1
B0 I1 B0
S S E

S
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 Multiplexers with enable input

 Quad 2-to-1 MUX

A3
Y3 A3
A2
Y2 A2
A1 A1
Y1 Y3
A0
Y0
A0 Y2
MUX
B3 Y1
B3
B2 Y0
B2
B1 B1
B0 B0
S E
Extra
Buffers
S E
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 Implementation Using Multiplexers

 Example
F(x, y) = ∑(0, 1, 3) = m0 + m1 + m3

x y F I0
1
0 0 1 1 I1
MUX Y F
0 1 1 0 I2
1 0 0 1 I3
S1 S0
1 1 1
x y

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 Implementation Using Multiplexers

 Example
F(x, y, z) = ∑(1, 2, 6, 7)
0 I0
x y z F 1 I1
0 0 0 0 1 I2
0 0 1 1 0 I3
Y F
0 1 0 1 0 I4 MUX
0 1 1 0 0 I5
1 I6
1 0 0 0
1 I7
1 0 1 0 S2 S1 S0
1 1 0 1
1 1 1 1 x y z

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 Implementation Using Multiplexers

 Example
F(x, y, z) = ∑(1, 2, 6, 7)

x y z F
0 0 0 0 z I0
F=z z I1 F
0 0 1 1
MUX Y
0 1 0 1 0 I2
F=z 1 I3
0 1 1 0 S1 S0
1 0 0 0
F=0 x y
1 0 1 0
1 1 0 1
F=1
1 1 1 1
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 Implementation Using Multiplexers

 Example
F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
A B C D F
0 0 0 0 0
F=D
D I0
0 0 0 1 1
0 0 1 0 0
D I1
F=D
0 0 1 1 1 D I2
0 1 0 0 1
0 1 0 1 0
F=D 0 I3
0 MUX Y F
0 1 1 0 0
F=0 I4
0 1 1 1 0 D
1 0 0 0 0
I5
1 0 0 1 0 F=0 1 I6
1 0 1 0 0
1 0 1 1 1
F=D 1 I7
1 1 0 0 1 S2 S1 S0
F=1
1 1 0 1 1
1 1 1 0 1 F=1
1 1 1 1 1 A B C
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 Multiplexer Expansion

 8-to-1 MUX using Dual 4-to-1 MUX and one 2 to 1 MUX

I0 I0
I1 I1
MUX Y
I2 I2
I3 I3
S1 S0 I0
MUX Y Y
I1
I0 S
I4
I5 I1 1
MUX Y
I6 I2
I7 I3
S1 S0

1 0 0
S2 S1 S0 68 / 65
 DeMultiplexers

Y3
Y2
I DeMUX Y
1

S S Y0
1 0

Y3

Y2 S1 S0 Y3 Y2 Y1 Y0
I
Y1 0 0 0 0 0 I
Y0
0 1 0 0 I 0
1 0 0 I 0 0
S1 1 1 I 0 0 0
S0
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Multiplexer / DeMultiplexer Pairs

MUX DeMUX

I7 Y7
I6 Y6
I5 Y5
I4 Y4
Y I Y3
I3
I2 Y2
I1 Y1
I0 Y0

S2 S1 S0 S2 S1 S0

Synchronize
x2 x1 x0 y2 y 1 y0
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DeMultiplexers / Decoders
Y3 Y3

Decoder
I1

Binary
Y2 Y2
I DeMUX Y I0 Y1
1
E Y0
S S Y0
1 0

Decoder with Enable input 1 is a DeMultilxer

E I1 I0 Y3 Y2 Y1 Y0
S1 S0 Y3 Y2 Y1 Y0 0 x x 0 0 0 0
0 0 0 0 0 I 1 0 0 0 0 0 1
0 1 0 0 I 0 1 0 1 0 0 1 0
1 0 0 I 0 0 1 1 0 0 1 0 0
1 1 I 0 0 0 1 1 1 1 0 0 0

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 Three-State Gates

 Tri-State Buffer
C A Y
High impedance
0 x Hi-Z
A Y state
1 0 0
1 1 1
Y = A when C
C high

A Y
Tri-State Inverter
C A Y C
Symbol
0 x Hi-Z
1 0 1 Y = A’ when c = 1

1 1 0
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Three-State Gates

A C D Y
0 0 Hi-Z
Y 0 1 B
C
1 0 A
B 1 1 ?

Not Allowed
D
A
C A if C = 1
Y=
B if C = 0
B
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 Three-State Gates with decoder as MUX

E S1 S0 Ya Y

1 0 0 Y0 I0

1 0 1 Y1 I1

1 1 0 Y2 I2

1 1 1 Y3 I3

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 Practice problem

 Design Full subtractor, 3 bit binary to gray code

converter, 3 bits parity generator using Decoder
and Multiplexer
 Design a 7 segment display using decoder

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