Chapter 5 Synchronous Sequential Circuit
Chapter 5 Synchronous Sequential Circuit
0
Sequential Circuits
Asynchronous
Inputs Outputs
Combinational
Circuit
Memory
Elements
Synchronous
Inputs Outputs
Combinational
Circuit
Flip-flops
Clock
1
Latches
SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
R
0 0
Q
S Q
0 1
Initial Value
SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0 Q = Q0
R
0 1
Q
S Q
0 0
3
Latches
SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R
1 0
Q
S Q
0 1
SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R
1 1 0 1 1 0 1 Q=0
Q
S Q
0 0
SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
0 0 0 1 1 0 1
Q=0
Q 1 0 0 1 0 Q=1
S Q
1 1
SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
0 1 0 1 1 0 1
Q=0
Q 1 0 0 1 0 Q=1
1 0 1 1 0 Q=1
S Q
1 0
SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
1 0 0 1 1 0 1
Q=0
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’
S Q
1 10
SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
1 10 0 1 1 0 1
Q=0
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’
1 1 1 0 0 Q = Q’
S Q
1 0
9
Latches
SR Latch
S R Q
R Q Q0 No change
0 0
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid
S S R Q
Q Invalid
0 0 Q=Q’=1
0 1 1 Set
1 0 0 Reset
R Q
1 1 Q0 No change
10
Latches
SR Latch
S R Q
R Q Q0 No change
0 0
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid
S S’ R’ Q
Q Invalid
0 0 Q=Q’=1
0 1 1 Set
Q 1 0 0 Reset
R Q0 No change
1 1
11
Controlled Latches
C S R Q
0 x x Q0 No change
1 0 0 Q0 No change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Q=Q’ Invalid
12
Controlled Latches
S
C
D
Q
C D
R Q
Q
t
C D Q
Output may
0 x Q0 No change change
1 0 0 Reset
1 1 1 Set
S
C
D
Q
C D
R Q
Q
C D Q Output may
0 x Q0 No change change
1 0 0 Reset
1 1 1 Set
14
Flip-Flops
15
Flip-Flops
Master-Slave D Flip-Flop
D D Q D Q Q
D Latch D Latch
(Master) (Slave)
C C
Master Slave
CLK
CLK
D
Looks like it is negative
edge-triggered QMaster
QSlave
16
Flip-Flops
Edge-Triggered D Flip-Flop
D Q
Q Positive Edge
CLK
Q
D Q
D Negative Edge
17
Flip-Flops
JK Flip-Flop
J
D Q Q
K
CLK Q Q
J Q
D = JQ’ + K’Q
K Q
18
Flip-Flops
T Flip-Flop
T J Q T D Q
Q
K Q
T Q
D = JQ’ + K’Q
D = TQ’ + T’Q = T Q Q
19
Flip-Flop Characteristic Tables
D Q D Q(t+1)
0 0 Reset
Q 1 1 Set
J K Q(t+1)
J Q 0 0 Q(t) No change
0 1 0 Reset
K Q 1 0 1 Set
1 1 Q’(t) Toggle
T Q T Q(t+1)
0 Q(t) No change
Q
1 Q’(t) Toggle
20
Flip-Flop Characteristic Equations
D Q D Q(t+1)
0 0 Q(t+1) = D
Q 1 1
J K Q(t+1)
J Q 0 0 Q(t)
0 1 0 Q(t+1) = JQ’ + K’Q
K Q 1 0 1
1 1 Q’(t)
T Q T Q(t+1)
0 Q(t) Q(t+1) = T Q
Q
1 Q’(t)
21
Flip-Flop Characteristic Equations
Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0 No change
J Q 0 0 1 1
0 1 0 Reset
0 1 1
K Q
1 0 0 Set
1 0 1
1 1 0 Toggle
1 1 1
22
Flip-Flop Characteristic Equations
Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0 No change
J Q 0 0 1 1
0 1 0 0 Reset
0 1 1 0
K Q
1 0 0 Set
1 0 1
1 1 0 Toggle
1 1 1
23
Flip-Flop Characteristic Equations
Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0 No change
J Q 0 0 1 1
0 1 0 0 Reset
0 1 1 0
K Q
1 0 0 1 Set
1 0 1 1
1 1 0 Toggle
1 1 1
24
Flip-Flop Characteristic Equations
Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0 No change
J Q 0 0 1 1
0 1 0 0 Reset
0 1 1 0
K Q
1 0 0 1 Set
1 0 1 1
1 1 0 1 Toggle
1 1 1 0
25
Flip-Flop Characteristic Equations
Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0
J Q 0 0 1 1 K
0 1 0 0 0 1 0 0
0 1 1 0 J 1 1 0 1
K Q Q
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Asynchronous Reset
D Q R’ D CLK Q(t+1)
0 x x 0
Q
R
Reset
27
Flip-Flops with Direct Inputs
Asynchronous Reset
D Q R’ D CLK Q(t+1)
0 x x 0
Q 1 0 ↑ 0
R 1 1 ↑ 1
Reset
28
Flip-Flops with Direct Inputs
Preset
Q
CLR
Reset
Preset
30
Flip-Flops with Direct Inputs
Preset
31
Analysis of Clocked Sequential Circuits
The State
● State = Values of all Flip-Flops
x
A
Example D Q
Q
AB=00
D Q B
CLK Q
32
Analysis of Clocked Sequential Circuits
State Equations
x
A
A(t+1) = DA D Q
=Ax+Bx
D Q B
B(t+1) = DB
CLK Q
= A’(t) x(t)
y
= A’ x
y(t) = [A(t)+ B(t)] x’(t)
= (A + B) x’
33
Analysis of Clocked Sequential Circuits
1 0 0 0 0 1
1 0 1 1 0 0
A(t+1) = A x + B x
1 1 0 0 0 1
1 1 1 1 0 0 B(t+1) = A’ x
y(t) = (A + B) x’
t t+1 t 34
Analysis of Clocked Sequential Circuits
t t+1 t A(t+1) = A x + B x
B(t+1) = A’ x
y(t) = (A + B) x’
35
Analysis of Clocked Sequential Circuits
CLK Q
01 11
y
1/0 36
Analysis of Clocked Sequential Circuits
D Flip-Flops
Example: x D Q A
Present Next
y
Input
State State CLK Q
A x y A
0 0 0 0
0 0 1 1 A(t+1) = DA = A x y
0 1 0 1
0 1 1 0
1 0 0 1 01,10
1 0 1 0
00,11 0 1 00,11
1 1 0 0
1 1 1 1 01,10
37
Analysis of Clocked Sequential Circuits
JK Flip-Flops J Q A
Example: x K Q
0 0 0 0 1 0 0 1 0 CLK
0 0 0 0 0 1
0 0 1 JA = B KA = B x’
0 1 0 1 1 1 1 1 0
JB = x’ KB = A x
0 1 1 1 0 1 0 0 1
1 0 0 1 1 0 0 1 1 A(t+1) = JA Q’A + K’A QA
1 0 1 1 0 0 0 0 0 = A’B + AB’ + Ax
1 1 0 0 0 1 1 1 1 B(t+1) = JB Q’B + K’B QB
1 1 1 1 1 1 0 0 0 = B’x’ + ABx + A’Bx’
38
Analysis of Clocked Sequential Circuits
JK Flip-Flops J Q A
x K Q
Example:
Present Next Flip-Flop J Q B
I/P
State State Inputs
A B x A B JA KA JB KB K Q
0 0 0 0 1 0 0 1 0 CLK
0 0 1 0 0 0 0 0 1 1 0 1
0 1 0 1 1 1 1 1 0 00 11
0 1 1 1 0 1 0 0 1
0
1 0 0 1 1 0 0 1 1 0 0
1 0 1 1 0 0 0 0 0
1 1 0 0 0 1 1 1 1 01 10
1 0 0 0
1
1 1 1 1 1 1
39
Analysis of Clocked Sequential Circuits
A
T Flip-Flops
x T Q y
R Q
Example:
Present Next F.F
I/P O/P
State State Inputs T Q
B
A B x A B TA TB y
R Q
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 CLK Reset
0 1 0 0 1 0 0 0
TA = B x TB = x
0 1 1 1 0 1 1 0
y =AB
1 0 0 1 0 0 0 0
1 0 1 1 1 0 1 0
A(t+1) = TA Q’A + T’A QA
= AB’ + Ax’ + A’Bx
1 1 0 1 1 0 0 1
1 1
B(t+1) = TB Q’B + T’B QB
1 1 1 0 0 1
=xB 40
Analysis of Clocked Sequential Circuits
A
T Flip-Flops
x T Q y
R Q
Example:
Present Next F.F
I/P O/P
State State Inputs T Q
B
A B x A B TA TB y
R Q
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 CLK Reset
0 1 0 0 1 0 0 0 0/0 0/0
0 1 1 1 0 1 1 0 00 1/0 01
1 0 0 1 0 0 0 0
1 0 1 1 1 0 1 0 1/1 1/0
1 1 0 1 1 0 0 1 11 10
1 1
0/1 0/0
1 1 1 0 0 1 1/0
41
Mealy and Moore Models
42
Mealy and Moore Models
Mealy Moore
Present Next Present Next
I/P O/P I/P O/P
State State State State
A B x A B y A B x A B y
0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 1 0 1 0
0 1 0 0 0 1 0 1 0 0 1 0
0 1 1 1 1 0 0 1 1 1 0 0
1 0 0 0 0 1 1 0 0 1 0 0
1 0 1 1 0 0 1 0 1 1 1 0
1 1 0 0 0 1 1 1 0 1 1 1
1 1 1 1 0 0 1 1 1 0 0 1
44
Moore State Diagram
State / Output
0 0
1
00/0 01/0
1 1
11/1 10/0
1
0 0
45
State Reduction and Assignment
State Reduction
Reductions on the
number of flip-flops and
the number of gates.
● A reduction in the
number of states may
result in a reduction in
the number of flip-flops.
● An example state
diagram showing in Fig.
5.25.
State: a a b c d e f f g f g a
Input: 0 1 0 1 0 1 1 0 1 0 0
Output: 0 0 0 0 0 1 1 0 1 0 0
48
Reducing the state table
● e = g (remove g);
● d = f (remove f);
49
● The reduced finite state machine
State: a a b c d e d d e d e a
Input: 0 1 0 1 0 1 1 0 1 0 0
Output: 0 0 0 0 0 1 1 0 1 0 0
51
Implication Table
(a, b) imply (c, d) and (c, d) imply (a, b). Both pairs of states are
equivalent; i.e., a and b are equivalent as well as c and d.
53
Implication Table
54
Implication Table
On the left side along the vertical are listed all the states
defined in the state table except the last, and across the bottom
horizontally are listed all the states except the last.
The states that are not equivalent are marked with a ‘x’ in the
corresponding square, whereas their equivalence is recorded
with a ‘√’.
Some of the squares have entries of implied states that must be
further investigated to determine whether they are equivalent
or not.
The step-by-step procedure of filling in the squares is as
follows:
1. Place a cross in any square corresponding to a pair of states whose
outputs are not equal for every input.
2. Enter in the remaining squares the pairs of states that are implied by
the pair of states representing the squares. We do that by starting from
the top square in the left column and going down and then proceeding
with the next column to the right.
55
Implication Table
3. Make successive passes through the table to determine whether any
additional squares should be marked with a ‘x’. A square in the table is
crossed out if it contains at least one implied pair that is not equivalent.
4. Finally, all the squares that have no crosses are recorded with check
marks. The equivalent states are: (a, b), (d, e), (d, g), (e, g).
We now combine pairs of states into larger groups of equivalent states.
The last three pairs can be combined into a set of three equivalent states
(d, e,g) because each one of the states in the group is equivalent to the
other two. The final partition of these states consists of the equivalent
states found from the implication table, together with all the remaining
states in the state table that are not equivalent to any other state:
(a, b) (c) (d, e, g) (f)
The reduced state table is:
56
Implication Table
57
State Assignment
State Assignment
To minimize the cost of the combinational circuits.
● Three possible binary state assignments. (m states need
n-bits, where 2n > m)
58
● Any binary number assignment is satisfactory as long
as each state is assigned a unique number.
● Use binary assignment 1.
59
Design Procedure
60
Design of Clocked Sequential Circuits
Example:
Detect 3 or more consecutive 1’s
0 1
S0 / 0 S1 / 0
0 State A B
S0 0 0
0 1
0 S1 0 1
S2 1 0
S3 / 1 S2 / 0 S3 1 1
1 1
61
Design of Clocked Sequential Circuits
Example:
Detect 3 or more consecutive 1’s
Present Next
Input Output
State State
A B x A B y 0 1
0 0 0 0 0 0 S0 / 0 S1 / 0
0 0 1 0 1 0 0
0 1 0 0 0 0
0 1 1 1 0 0 0 0 1
1 0 0 0 0 0
1 0 1 1 1 0
S3 / 1 S2 / 0
1 1 0 0 0 1
1 1
1 1 1 1 1 1
62
Design of Clocked Sequential Circuits
Example:
Detect 3 or more consecutive 1’s
Present Next
Input Output
State State
A B x A B y Synthesis using D Flip-Flops
0 0 0 0 0 0
0 0 1 0 1 0 A(t+1) = DA (A, B, x)
0 1 0 0 0 0 = ∑ (3, 5, 7)
0 1 1 1 0 0
1 0 0 0 0 0 B(t+1) = DB (A, B, x)
1 0 1 1 1 0
= ∑ (1, 5, 7)
1 1 0 0 0 1
1 1 1 1 1 1 y (A, B, x) = ∑ (6, 7)
63
Design of Clocked Sequential Circuits with
D F.F.
Example:
Detect 3 or more consecutive 1’s
=AB A 0 0 1 1
x 64
Design of Clocked Sequential Circuits with
D F.F.
Example:
Detect 3 or more consecutive 1’s
DA = A x + B x
D Q A
DB = A x + B’ x x
Q
y =AB y
D Q B
CLK Q
65
Flip-Flop Excitation Tables
Q(t) Q(t+1) T
0 0 0
0 1 1
1 0 1
1 1 0
66
Design of Clocked Sequential Circuits with
JK F.F.
Example:
Detect 3 or more consecutive 1’s
K Q
CLK 68
Design of Clocked Sequential Circuits with T
F.F.
Example:
Detect 3 or more consecutive 1’s
Present Next F.F.
Input
State State Input
A B x A B TA TB Synthesis using T Flip-Flops
0 0 0 0 0 0 0
0 0 1 0 1 0 1 TA (A, B, x) = ∑ (3, 4, 6)
0 1 0 0 0 0 1 TB (A, B, x) = ∑ (1, 2, 3, 5, 6)
0 1 1 1 0 1 1
1 0 0 0 0 1 0
1 0 1 1 1 0 1
1 1 0 0 0 1 1
1 1 1 1 1 0 0
69
Design of Clocked Sequential Circuits with T
F.F.
Example:
Detect 3 or more consecutive 1’s
Q y
B B
T Q B
0 0 1 0 0 1 1 1
Q
A 1 0 0 1 A 0 1 0 1
x x
CLK
70
71