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Indian Institute of Technology Kharagpur

Course Name: VLSI PHYSICAL DESIGN

Assignment- Week 6
TYPE OF QUESTION: MCQ/MSQ/SA
Number of questions: 10 Total mark: 10 x 1 = 10
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QUESTION 1:
What is the main purpose of timing‐driven routing?
a. Minimize the signal delays when selecting routing topologies and specific routes.
b. Minimize the signal delays when the cells are assigned locations on the layout
area.
c. Minimize the skew and jitter of all the signal lines.
d. None of these.
Correct Answer: a

Detailed Solution: The main purpose of timing driven routing is to minimize the signal delays
when selecting routing topologies and specific routes.
The correct option is (a).
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QUESTION 2:
Which of the following delays dominate in modern‐day VLSI chips?
a. Clock delay.
b. Gate delay.
c. Interconnection delay.
d. All of these.
Correct Answer: c

Detailed Solution: As the process technology reduces with advancements in fabrication

technology, delays of the interconnection lines start to dominate as compared to the delays of the
circuit blocks.
The correct option is (c).
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QUESTION 3:
Which of the following statements are true for static timing analysis?
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a. Propagates actual arrival times (AAT) to the terminals of every gate or cell.
b. Can quickly identify timing violations.
c. Cannot model propagation of signal transitions with the worst possible delay.
d. The process includes false paths from the analysis.
Correct Answer: a, b

Detailed Solution: Static timing analysis propagates actual arrival time (AAT) to the terminals
of every gate or cell. It can quickly identify timing violations. It models propagation of signal
transitions with the worst possible delay. This typically excludes false paths from the analysis.
Hence, the correct options are (a) and (b).
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QUESTION 4:
Which of the following are not instances of controlling values?

a. Logic 0 at the input of an XOR gate.

b. Logic 1 at the input of an OR gate.
c. Logic 0 at the input of an AND gate.
d. Logic 0 at the input of an OR gate.

Correct Answer: a, d

Detailed Solution: The controlling values depend on the type of the gate. For AND and NAND
gates, the controlling value is 0. For OR and NOR gates, the controlling value is 1. However, for
XOR and XNOR gates, neither 0 nor 1 is a controlling value.
Hence, the correct options are (a) and (d).
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QUESTION 5:
The Boolean difference of a Boolean function X with respect to another function Y defines the
conditions where:
a. The logic values of X and Y are always different.
b. The logic values of X and Y are always same.
c. Any change in the logic value of X will also cause the logic value of Y to change.
d. Any change in the logic value of Y will also cause the logic value of X to change.

Correct Answer: d

Detailed Solution: The Boolean difference dX/dY specifies the condition where a change in the
logic value of Y will change the logic value of X. None of (a), (b) or (c) specify this.
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Hence, the correct option is (d).

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QUESTION 6:
When we want to sensitize a path from a primary input to one of the primary outputs, we have
to:
a. Apply controlling values to the side inputs of all gates in the path.
b. Ensure that there is no skew or jitter in the path.
c. Apply non‐controlling values to the side inputs of all gates in the path.
d. None of these.

Correct Answer: c

Detailed Solution: One of the necessary conditions for sensitizing a path from a primary input to
a primary output is that non-controlling values must be applied to the side inputs of all the gates
that lie along the path.
Hence, the correct option is (c).
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QUESTION 7:
Static timing analysis is applicable to asynchronous subsystems. True or False?

Correct Answer: False

Detailed Solution: Static timing analysis is not applicable to asynchronous subsystems.

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QUESTION 8:
Which of the following statements is/are true for SAT based false path analysis?
a. Modern SAT solvers cannot handle large number of variables.
b. Modern SAT solvers can handle large number of variables.
c. A SAT solver tries to find some assignments of the variables for which F=1, where
F is in sum‐of‐products form.
d. A SAT solver tries to find some assignments of the variables for which F=1, where
F is in product‐of‐sums form.

Correct Answer: b, d
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Detailed Solution: SAT based methods are used to carry out false path analysis as well. Modern
SAT solvers can handle large number of variables. For a given Boolean function F in product-of-
sums form, a SAT solver tries to find some assignment of the variables for which F=1.
Hence correct options are (b) and (d).
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QUESTION 9:
If the RAT and AAT values for line x are RAT(x) = 17 and AAT(x) = 14, which of the following
is/are true?
a. The Slack value on line x is +3.
b. The Slack value on line x is ‐3.
c. The timing constraint has been met.
d. The Slack value on line x is ‐4.

Correct Answer: a, c

Detailed Solution: The Slack value on line x is given by 17 – 14 = +3. A positive value of Slack
indicates that the timing constraint has been met.
The correct options are (a) and (c).
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QUESTION 10:
Which of the following is/are used to speed up the process of static timing analysis?
a. All the timing violations are eliminated before starting the process.
b. All the false paths in the circuit are excluded from the analysis.
c. The RAT and AAT values of all the lines are made equal.
d. All of these.

Correct Answer: b

Detailed Solution: Option (a) is false as it is not possible to eliminate all timing violations in the
beginning. Also, (c) is false as the RAT and AAT values of all the lines need not be made equal.
To speed up the process of static timing analysis, we can eliminate the inactive (false) paths from
the computation.
Hence, the correct option is (b).
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