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Week 4 Assignment 4 with solution final

The document presents an assignment on VLSI Physical Design focusing on partitioning and timing analysis. It includes multiple-choice questions regarding partitioning concepts, algorithms like Kernighan-Lin and Fiduccia-Mattheyses, and calculations related to the algorithms. Answers and explanations are provided for each question based on lecture notes.

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13 views

Week 4 Assignment 4 with solution final

The document presents an assignment on VLSI Physical Design focusing on partitioning and timing analysis. It includes multiple-choice questions regarding partitioning concepts, algorithms like Kernighan-Lin and Fiduccia-Mattheyses, and calculations related to the algorithms. Answers and explanations are provided for each question based on lecture notes.

Uploaded by

rishiKumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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VLSI Physical Design with Timing Analysis

Assignment – 4
Qns.1: Which option(s) is/are correct related to partitioning?
a. Partitioning is the process of decomposing complex systems into smaller, manageable
parts.
b. Partitioning of a chip into smaller subcircuits is called system level partitioning.
c. The partitioning of a system into a group of PCBs is called board-level partitioning.
d. The aim is to minimize the area of each chip as the manufacturing cost is proportional to
chip area.

Ans: (a, d) Refer lecture notes

Qns.2: Which option(s) is/are correct?


a. Deterministic algorithms always generate a different solution for a given problem.
b. Probabilistic algorithms can produce the same solution for the same problem each time.
c. Group Migration algorithms are often trapped at a local optimum and cannot proceed
further.
d. In Kernighan-Lin (KL) Algorithm, High costs (D < 0) indicate that the node should move,
while low costs (D > 0) indicate that the node should stay within the same partition.

Ans: (c) Refer lecture notes

Qns.3: Which option(s) is/are incorrect?


a. The primary objective of chip-level partitioning is to facilitate the efficient design of the
chip.
b. Partitioning may impact the chip's performance, especially when critical components that
should be close together are separated.
c. System performance improvement does not rely on minimizing the length of the critical
path formed by several components.
d. The delay between partitions is smaller than the delay within a partition at any level of
partition.

Ans: (c, d) Refer lecture notes

Qns.4: Choose the correct options regarding partitioning algorithms.


a. Kernighan-Lin (KL) and Fiduccia-Mattheyses (FM) algorithms are examples of group
migration algorithms.
b. Kernighan-Lin (KL) and Fiduccia-Mattheyses (FM) algorithms are examples of
probabilistic algorithms.
c. Constructive algorithms provide initial partitions which are typically optimal.
d. The simulated annealing algorithm is a deterministic algorithm.

Ans: (a) Refer lecture notes


Question Numbers: (5 to 7):
Consider the following graph as an input to the Kernighan-Lin(KL) algorithm. The initial partition
is done as shown in the figure.

Qns.5: The values of D(1), D(3), D(6), and D(8) in the first iteration of the KL algorithm for the
given graph are _____ respectively.
a. 1, 0, 0, 1
b. 0, 1, 1, 0
c. 0, 1, 0, -2
d. 1, 0, 0, -2
e. 0, 0, 1, -1

Ans: (b)

Sol: The definition of the cost function used in the KL algorithm is D(a) = Ec(a) – Enc(a)
Where Ec(a) is the set of a’s incident edges that are cut by the cut line, and
Enc(a) is the set of a’s incident edges that are not cut by the cut line.
D(1) = 1 – 1 = 0
D(3) = 2 – 1 = 1
D(6) = 2 – 1 = 1
D(8) = 1 – 1 = 0

Qns.6: The sum of Δg(2,5) and Δg(3,7) in the first iteration of the KL algorithm for the given
graph is _____.

Ans: 0

Sol: The definition of the gain used in the KL algorithm is Δg(a,b) = D(a) + D(b) – 2c(a,b)
Where c(a,b) = 1, if there is an edge between a and b else c(a,b) = 0.
Δg(2,5) = D(2) + D(5) – 2c(2,5) = 0 + 0 – 2*0 = 0.
Δg(3,7) = D(3) + D(7) – 2c(3,7) = 1 + 1 – 2*1 = 0.
Sum = Δg(2,5) + Δg(3,7) = 0 + 0 = 0.

Qns.7: How many times is Cost D(nodes) calculated in the first pass of the KL algorithm for the
given graph?

Ans: 20
Sol: In the first iteration (k=1), there are 8 nodes.
∴ In the first iteration, D is calculated 8 times. In the successive iterations, two nodes are fixed.
So, in second iteration, D is calculated 6 times and so on.
∴ Number of times D is calculated in first pass of KL algorithm is = 8 + 6 + 4 + 2 = 20.

Question Numbers: (8 to 10):


Consider the following graph as an input to the Fiduccia-Mattheyses (FM) algorithm. The initial
partition is done as shown in the figure.

The ratio factor is 1/3. Area of logic gates are given as

Qns.8: The value of gain, Δg(c), in the first iteration of the FM algorithm, is ____.

Ans: 1

Sol: The graph of given circuit is


Gain ∆g(c) for cell c, ∆g(c) = FS(c) – TE(c). Where,
FS(c) is the number of nets connected to c but not connected to any other cells within c’s
partition, i.e., cut nets that connect only to c, and
TE(c) is the number of uncut nets connected to c.
So, Δg(c) = FS(c) – TE(c) = 1 – 0 = 1.

Qns.9: Which of the following is the correct balance criterion for the given graph?
a. 4 ≤ Area(A) ≤ 11
b. 3 ≤ Area(A) ≤ 11
c. 3 ≤ Area(A) ≤ 12
d. 4 ≤ Area(A) ≤ 12

Ans: (b)

Sol: The balance criterion is given by


[ r ∙ area(V) – areamax(V) ] ≤ area(A) ≤ [ r ∙ area(V) + areamax(V) ]
Where area(V) = sum of areas of all nodes = 20 and
areamax(V) = area of largest node = 5.
[(1/3)*21 – 4] ≤ area(A) ≤ [[(1/3)*21 + 4]
3 ≤ area(A) ≤ 11.

Qns.10: Choose the base cell(s) for the first iteration of the FM algorithm for the given graph.
a. a
b. b
c. c
d. d
e. e
f. f

Ans: (c)
Sol: A base cell is a cell c with the greatest cell gain ∆g(c), among all free cells whose move
does not violate the balance criterion.

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