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Week 3 Assignment 3 with solution final

The document contains a series of assignments related to VLSI Physical Design and Timing Analysis, focusing on circuit delays, maximum frequencies, hold constraints, and clock jitter. It includes specific questions with corresponding answers regarding circuit performance metrics and timing violations. Additionally, it addresses concepts like common path pessimism and clock skew versus jitter, providing insights into their implications on circuit functionality.

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rishiKumar
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11 views

Week 3 Assignment 3 with solution final

The document contains a series of assignments related to VLSI Physical Design and Timing Analysis, focusing on circuit delays, maximum frequencies, hold constraints, and clock jitter. It includes specific questions with corresponding answers regarding circuit performance metrics and timing violations. Additionally, it addresses concepts like common path pessimism and clock skew versus jitter, providing insights into their implications on circuit functionality.

Uploaded by

rishiKumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSI Physical Design with Timing Analysis

Assignment - 3
Qns 1: Consider the following circuit.

Delay values of Flipflop and Combinational circuit are: t setup = 3ns and thold = 2ns. The delay of the
buffer is tbuf = 2ns.
Delay tclk-q tNAND3 tNOT tNOR tNAND2
Max 3 ns 2.5 ns 1 ns 2.5 ns 2 ns
Min 2 ns 1.5 ns 0.3 ns 1.5ns 1.2 ns

The maximum frequency at which the given circuit can operate without failure is __ (MHz)
(Rounded to 2 decimal points)

Ans: 90.90 MHz

Qns 2: Choose the correct hold constraint equation for the circuit given in question 1.
a. 4ns – 2ns ≤ 2ns + 3ns
b. 4ns ≤ 2ns + 3ns
c. 4ns ≤ 3ns + 5.5ns
d. 4ns – 2ns ≤ 3ns + 5.5ns

Ans: (b)
Qns 3 : Consider the following circuit.

Delay values of Flipflop and Combinational circuit are: t setup = 3ns and thold = 2ns. The delay of the
buffer is tbuf = 2ns.
Delay tclk-q tNAND3 tNOT tNOR tNAND2
Max 3 ns 2.5 ns 1 ns 2.5 ns 2 ns
Min 2 ns 1.5 ns 0.3 ns 1.5 ns 1.2 ns

The maximum frequency at which the given circuit can operate without failure is___(MHz)
(Rounded to 2 decimal points)

Ans: 66.67 MHz

Qns 4: Consider the following circuit.

Delay values of Flipflop and Combinational circuit are: t setup = 3ns and thold = 2ns. The clock period is
TCLK = 20ns.
Delay tclk-q tNAND3 tNOT tNOR tNAND2
Max 3 ns 2.5 ns 1 ns 2.5 ns 2 ns
Min 2 ns 1.5 ns 0.3 ns 1.5 ns 1.2 ns

What is the maximum allowable jitter (tjitter) in the clock signal so that the given circuit works at the given
frequency without failure?
a. 0.5 ns
b. 1.5 ns
c. 2.5 ns
d. 3.5 ns

Ans: (b)
Qns 5 : Consider the following circuit.

Delay tclk-q(FF1) tclk-q(FF2) tNAND3 tNOT tNOR tNAND2


Max 3.8 ns 5 ns 2.5 ns 1 ns 2.5 ns 2 ns
Min 2 ns 2.8 ns 1.5 ns 0.3 ns 1.5 ns 1.2 ns

The delays of buffers tbuf1 = 1.2ns, tbuf2 = 0.9ns, and tbuf3 = 0.7ns. The setup and hold time of both flipflops
is tsetup = 2ns and thold = 1ns respectively.
The On-chip variation is modeled as
set_timing_derate -early 0.9
set_timing_derate -late 1.12

set_timing_derate -late 1.08 -cell_check


With On-chip variation, the maximum frequency at which the given circuit can operate without
failure is ____(MHz) (Rounded to 2 decimal points)

Ans: 67.12 MHz

Qns 6 : The value of common path pessimism (CPP) in the circuit given in question 5 is ___ps

Ans: 264 ps
Qns 7 to 9: Question Label: Comprehension
Consider the following logic circuit.

Logic gate Rise delay(ns) Fall delay(ns)


NAND 4 3
NOR 3 5
AND 2 3
OR 5 4
Buffer 1 2
Arrival Time at all primary inputs A, B, C, D and E is 0/0.
Required Time at node ‘N’ is 16/13
Qns 7: The fall output arrival time at node ‘J’ is ___(ns)

Ans: 6 ns

Qns 8: The rise input required time at node ‘G’ in the given circuit is ____ (ns)

Ans: -3 ns

Qns 9: The slack(rise/fall) at node ‘H’ in the given circuit is _____


a. 7/2
b. 7/-4
c. 0/-4
d. 7/-4

Ans: (c)

Qns 10: Choose the incorrect option(s) about clock skew and clock jitter.
a. Excessive skew can cause timing violations (setup or hold violations) leading to functional errors.
b. Clock skew is non-deterministic in nature while Clock Jitter is deterministic in nature.
c. Clock skew occurs due to noise & instability in clock while clock jitter occurs due to physical layout
& propagation delay.
d. Clock jitter can lead to data corruption in high-speed designs.

Ans: (b, c)
SOLUTION

Sol 1.

Sol 2.
Sol 3.

Sol 4.
Sol 5.

Sol 6.
Sol 7-9.
Equations used in the solution:

For inverting gates: For non inverting gates:


output rise AT = max(input fall AT) + trise output rise AT = max(input rise AT) + trise
output fall AT = max(input rise AT) + tfall output fall AT = max(input fall AT) + tfall
input rise RT = min(output fall RT) – tfall input rise RT = min(output rise RT) – trise
input fall RT = min(output rise RT) – trise input fall RT = min(output fall RT) – tfall

Sol 10. Refer lecture notes

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