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Week 2 Assignment 2 with solution final

The document contains a series of questions and answers related to VLSI Physical Design and Timing Analysis, focusing on logic circuits and flip-flops. It includes calculations for critical path delays, false path delays, setup and hold times, and unateness of outputs. The answers are provided for each question, along with the reasoning behind them.

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rishiKumar
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0 views

Week 2 Assignment 2 with solution final

The document contains a series of questions and answers related to VLSI Physical Design and Timing Analysis, focusing on logic circuits and flip-flops. It includes calculations for critical path delays, false path delays, setup and hold times, and unateness of outputs. The answers are provided for each question, along with the reasoning behind them.

Uploaded by

rishiKumar
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSI Physical Design with Timing Analysis

Assignment -2
Qns 1 to 2: Question Label: Comprehension
Consider the following logic circuit. Delays of logic gates are t NOR = 1.5ns, tNOT = 1ns,
tOR = 2ns, tAND= 1.5ns and tMUX = 2.5ns.

The critical path delay in the logic circuit given above is ______
a. 14 ns
b. 13.5 ns
c. 13 ns
d. 12.5 ns
Ans: (d) 12.5

Z = D + C.D.E = D (1 + C.E) = D
The value at point Z in the circuit does not depend on C and E, So the inverters
doesn’t need to be considered in the critical path delay.
Tcritical = tand + tand + tor + tnot + tmux + tnor + tmux
Tcritical = 1.5+1.5+2+1+2.5+1.5+2.5
Tcritical = 12.5 ns
Qns 2: Find the delay of the false path in the logic circuit given in question 1.
a. 11 ns
b. 12 ns
c. 13 ns
d. 14 ns
Ans: (d) 14ns

Tfalse = tNOT + tAND + tAND + tOR + tNOR + tMUX + tNOR + tMUX


Tfalse = 1+1.5+1.5+2+1.5+2.5+1.5+2.5
Tfalse = 14 ns

Qns 3: Which of the following is/are true?


a. If setup time increases, then speed will decrease.
b. For fixing hold violation, we may increase delay of combination path.
c. Negative skew improves speed of design.
d. Positive skew degrades hold requirement.
Ans: (a, b, d) refer lecture slide

Qns 4: Consider the following logic circuit.

What is the Unateness of output pin Z with respect to the input pin A?
a. Negative unate
b. Positive unate
c. Non-unate
d. Can’t determined
Ans: (b)
A B C Z
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1

Case – 1: keep B = 0, C = 0 and A is changing from 0 → 1. You see no change in the output Z from
truth table.

Case – 2: keep B = 0, C = 0 and A is changing from 1 → 0. You see no change in the output Z from
truth table.

Case – 3: keep B = 1, C = 1 and A is changing from 0 → 1. You see 0 → 1 in the output Z from truth table.

Case – 4: keep B = 1, C = 1 and A is changing from 1 → 0. You see 1 → 0 in the output Z from truth table.

Similarly, you can check for four other cases and find that output pin Z is of positive unate with respect to pin A.

Qns 5 to 7: Question Label: Comprehension


Consider the master-slave flipflop circuit given below.

Delays of gates are: tINV = 0.5ns, tBUF = 0.8ns, tTX = 1ns , tcomb = 1ns
Given master-slave flipflop is _________ triggered.
a. Positive edge
b. Negative edge
c. Level
d. Can’t determined
Ans: (a)

Data is captured by master during negative clock cycle and slave becomes
transparent during positive cycle. So, it is a Positive edge triggered flipflop.

Qns 6: The setup time of the master-slave flipflop in given main question is ______ns.
a. 3.5 ns
b. 3.8 ns
c. 2.8 ns
d. 2.5 ns
Ans: (b) 3.8 ns

Tsetup= tcomb + tTX + 2*tINV + tBUF


Tsetup = 1+1+2*0.5+0.8
Tsetup =3.8ns
Qns 7: The hold time of the master-slave flipflop in given main question is
a. Negative
b. Positive
c. Zero
d. Can’t determined
Ans: (c)
tcomb = 1ns, tTX =1ns
tcomb = tTX
Hold time is Zero. (refer lecture slide)

Qns 8 to 9: Question Label: Comprehension


Consider the following diagram

Delay values of Flipflop and Combinational circuit are: tsetup = 2.5 ns and thold = 3 ns

Delay Tclk-q (ns) Tcomb (ns)


Max. 7 10.5
Min. 4.5 3
The maximum frequency at which the given circuit can operate without failure is
____(MHz) (roundup to the nearest integer)

Ans: 50MHz
TCLK ≥ tclk-q (max) + tcomb (max) + tsetup
TCLK ≥ 7 + 10.5 + 2.5
TCLK ≥ 20ns
FMAX = 1 / TCLK (min)

FMAX = = 50 MHz

Qns 9: Choose the correct hold constraint equation for the circuit given in main
question.
a. 3ns ≤ 10.5ns + 7ns
b. 3ns ≤ 4.5ns + 3ns
c. 3ns ≤ 4.5ns + 7ns
d. 3ns ≤ 7ns + 3ns

Ans: (b)
tHOLD ≤ tclk-q (min) + tcomb (min)
3ns ≤ 4.5ns + 3ns

Qns 10: Consider the given logic circuit. Find the rise and fall delay of timing path
from input to output.

The rise and fall delay of the gates are as follow

Gate Not(ns) Nor(ns) Nand(ns)


Rise delay 3 5 3
Fall delay 2 4 4

a. trise=14ns, tfall=16ns
b. trise=11ns, tfall=10ns
c. trise=10ns, tfall=11ns
d. trise=16ns, tfall=14ns
Ans: (c)
trise= trise(nand)+tfall(nor)+ trise(inv)
trise=3+4+3
trise=10ns

tfall= tfall(nand)+trise(nor)+ tfall(inv)


tfall=4+5+2
tfall=11ns

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