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Indian Institute of Technology Kharagpur

Course Name: VLSI PHYSICAL DESIGN

QUESTION 1:
How do we define the radius of a spanning tree T that includes the source and sink nodes of a
net?
a. Length of the shortest path from source to any sink node in T.
b. Length of the longest path from source to any sink node in T.
c. Length of the shortest path between any pair of nodes in T.
d. Length of the longest path between any pair of nodes in T.

Correct Answer: b

Detailed Solution: The radius of a spanning tree is defined as the length of the longest path
from the source to any of the sink nodes in the spanning tree.
The correct answer is (b).
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QUESTION 2:
Which of the following algorithms generates a spanning tree with the smallest radius?
a. Dijkstra’s algorithm
b. Prim’s algorithm
c. Lee’s algorithm
d. None of these

Correct Answer: a

Detailed Solution: Dijkstra’s algorithm generates a spanning tree with the smallest value of
radius.
The correct answer is (a).
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QUESTION 3:
Which of the following algorithms generates a spanning tree with the smallest cost?
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Indian Institute of Technology Kharagpur

a. Dijkstra’s algorithm
b. Prim’s algorithm
c. Lee’s algorithm
d. None of these

Correct Answer: b

Detailed Solution: Prim’s algorithm generates a spanning tree with the smallest cost.
The correct answer is (b).
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QUESTION 4:
In the bounded radius bounded cost (BRBC) algorithm, which of the following statements is
true for the parameter ?
a. As  increases, the tree generated by the algorithm has smaller radius.
b. When  = 0, the algorithm generates a tree with smallest radius.
c. When  is infinite, the algorithm generates a tree with smallest cost.
d. None of the above.

Correct Answer: b, c

Detailed Solution: In the BRBC algorithm, the parameter  acts as a parameter. If  = 0, a tree
with the smallest radius is generated. Whereas, if  is infinite, a tree with the smallest cost is
generated.
The correct answers are (b) and (c).
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QUESTION 5:
Which of the following statement(s) is/are true?
a. Timing-driven routing tends to minimize the maximum sink delay.
b. Timing-driven routing tends to minimize the total wire length.
c. Timing-driven routing tends to minimize the total clock skew.
d. All of these.
Correct Answer: a, b
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Indian Institute of Technology Kharagpur

Detailed Solution: Timing driven routing tries to minimize both the maximum sink delay and
also the total wire length (and hence the interconnection delay). The clock skew problem is
handled separately.
The correct options are (a) and (b).
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QUESTION 6:
For a multi-pin net, the critical sink is defined as the sink for which:
a. The delay from source to sink is the smallest.
b. The delay from source to sink is the largest.
c. The timing slack is the largest.
d. The timing slack is the smallest.
Correct Answer: d

Detailed Routing: For a multi-pin net, the critical sink is defined as the sink point that has the
smallest timing slack. It has nothing to do with critical path.
The correct option is (d).
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QUESTION 7:
The use of buffers for the purpose of timing corrections in a circuit leads to:
a. An increase in power consumption.
b. An increase in signal skew.
c. An increase in area.
d. All of these.

Correct Answer: a, c

Detailed Solution: Use of buffers can reduce the overall delay. However, due to added circuitry,
the area as well as power consumption increases. It has no connection with signal skew.
The correct options are (a) and (c).
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QUESTION 8:
For which of the following modules, we can swap the input pins without changing the
functionality?
a. A module realizing the function F = A.B + B.C + C.A
b. A 2-to-1 multiplexer
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c. A 5-input NOR gate.

Correct Answer: a, c, d

Detailed Solution: We can swap the inputs of AND, OR, NAND, NOR, XOR and XNOR gates
without changing the functionality. This is also true for a symmetric function like F = A.B + B.C +
C.A. However, this is not true for a multiplexer, where swapping two inputs can change the
output function.
The correct options are (a), (c) and (d).
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QUESTION 9:
Suppose that a cascade of N progressively larger buffers is used to drive a large capacitive
load. If each buffer is larger than the previous one by U, the optimum value of U to
minimize the total delay is given by:
a. N2
b. √N
c. √(CL/Cin), where CL is the load capacitance and Cin the input capacitance of the
first buffer.
d. None of these.

Correct Answer: d

Detailed Solution: Buffer design to optimize delay has been discussed in the lectures. The
optimum value of U has been shown to be the base of the natural logarithm, e = 2.71828.
The correct option is (d).
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QUESTION 10:
Suppose that a long interconnection line is split into four shorter segments by inserting
repeaters. Which of the following statement(s) is/are true?
a. The total delay increases by an amount equal to the delay of three repeaters.
b. The RC delay excluding delay of repeater increases by 4 times.
c. The RC delay excluding delay of repeater reduces by 4 times.
d. None of these.

Correct Answer: c
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Detailed Solution: The delay of an interconnection line is roughly proportional to the square of
the length: say, D = k.L2, where k is a constant.
RC delay of the original design: D1 = k.L2 (say)
RC delay of the modified design: D2 = k.(L/4)2 + k.(L/4)2 + k.(L/4)2 + k.(L/4)2 = k.L2/4
Total RC delay reduces by 4 times.
The correct option is (c).
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