MEMORY TESTING

Name

Abstract— A key component of digital VLSI design is for expensive re-manufacturing. In addition to static fault
memory testing, which guarantees the yield, functionality, and detection, recent developments in memory testing also
dependability of integrated circuits as memory density and emphasise dynamic fault coverage, fault diagnosis, and
complexity increase. Efficient detection of faults like stuck-at, adaptive testing techniques that complement defect-oriented
transition, coupling, and retention faults is crucial since
memories are becoming essential parts of systems-on-chip (SoCs)
methodologies. Strong, effective, and scalable memory
and other high-performance devices. Because they allow for at- testing techniques are becoming more and more crucial as
speed testing, less reliance on outside testers, and support for in- digital systems continue to develop towards more intricate,
field diagnostics, Built-In Self-Test (BIST) techniques have multi-core, and memory-intensive architectures. In order to
become the go-to option. In order to achieve thorough fault achieve high reliability and performance in digital VLSI
coverage with the least amount of hardware overhead, modern designs, this paper examines the foundations and most recent
memory test strategies use sophisticated algorithms, such as developments in memory testing, including core concepts,
March tests and redundancy-based repair schemes. algorithms, BIST, and BISR techniques.
Additionally, defect-oriented and self-repairable testing
methodologies have emerged as a result of the growing need to
manage dynamic faults and subtle failure modes. In order to II. MEMORY ARCHITECTURE & MBIST MODEL
ensure robust and dependable digital VLSI designs, memory
testing is essential, and this paper provides an overview of its
fundamentals, methods, and developments. A crucial stage in VLSI design is memory testing, which
verifies that integrated circuits' embedded memories operate
Keywords— Memory testing, VLSI design, fault detection, accurately and consistently under various operating
Built-In Self-Test (BIST), March algorithms, stuck-at faults, circumstances. With the increasing density and complexity of
transition faults, coupling faults, retention faults, defect- contemporary semiconductor devices, memory defects are
oriented testing, redundancy repair, digital systems, memory
one of the main reasons for chip failure, as noted by VLSI
reliability.
Universe . To ensure the functionality and dependability of
I. INTRODUCTION the finished product, defects like stuck-at, transition, coupling,
and retention faults must be found. More effective on-chip
Built-In Self-Test (BIST) mechanisms have replaced
Memories are the foundation of digital designs in
conventional testing methods that used external Automatic
contemporary VLSI systems, taking up a sizable amount of
Test Equipment (ATE). These mechanisms allow for at-speed
silicon space and being essential to system performance.
testing and lower overhead costs and time. Memory testing
Memory circuits are more vulnerable to ageing effects,
has evolved from functional validation to defect-oriented and
environmental stresses, and manufacturing flaws as
self-repairing methodologies. Modern strategies include
semiconductor technology advances to nanometre sizes.
defect modelling, sophisticated March-based algorithms, on-
Therefore, a crucial component of integrated circuit (IC)
chip redundancy handling, and diagnostic support.
design and manufacturing is guaranteeing the robustness,
Maintaining high memory reliability and yield in
accuracy, and dependability of these memories. The process
semiconductor manufacturing requires addressing static and
of confirming that a memory device operates as intended and
dynamic behavior, adjusting to technology-specific fault
is free of flaws like stuck-at faults, transition faults, coupling
mechanisms, and facilitating affordable test and repair
faults, and retention faults is known as memory testing. For
solutions. Memory testing in digital systems has changed as
high-density memories, conventional external testing
a result of the use of BIST architectures. Memory BIST
techniques utilising Automatic Test Equipment (ATE) are
structures use specialised test algorithms to automate
frequently inadequate or prohibitively expensive. Because
read/write operations by integrating specialised hardware
they enable at-speed testing, eliminate the need for costly
within the chip. Rapid testing during manufacturing and in-
external hardware, and facilitate in-field diagnostics, Built-In
field operation is made possible, reducing the need for costly
Self-Test (BIST) architectures have consequently emerged as
external testing infrastructure. The comparator, control logic,
the industry standard. By embedding the test pattern
address generator, and test pattern generator are essential
generation, test application, and response analysis directly
parts of a Memory BIST. In addition to supporting
into the chip, BIST techniques increase test coverage while
redundancy management via Built-In Redundancy Analysis
reducing overhead. To effectively target various fault models,
(BIRA) and Built-In Self-Repair (BISR), Memory BIST aids
a number of memory-specific test algorithms have been
in the detection of multiple fault types. Conventional testing
developed, such as March tests, chequerboard patterns, and
is no longer adequate as VLSI designs advance towards
walking patterns. March algorithms are popular among them
advanced nodes (7nm, 5nm, and below), as new defect
because of their ease of use, consistent structure, and capacity
mechanisms appear. Memory test algorithms have had to
to identify a variety of faults. Built-In Self-Repair (BISR)
change in response to newer fault models, such as dynamic
mechanisms have also been introduced to increase yield as
and soft faults brought on by environmental factors. While
memory densities increase. These mechanisms identify
more sophisticated techniques are being developed to address
defective memory cells and replace them with spare rows or
timing-dependent and intermittent faults, March algorithms
columns, ensuring continued functionality without the need

XXX-X-XXXX-XXXX-X/XX/$XX.00 ©20XX IEEE

(such as March C-, March LA, and March SS) are still widely The tester examines the device's response and contrasts it
used for testing static faults. Furthermore, the ability to with the golden response that is recorded in the test pattern
diagnose problems quickly has become essential for data. By enclosing the memory on the chip in a test circuitry
increasing yield and decreasing time to market. The evolution and using a finite state machine (FSM) to produce stimuli and
of memory testing from fault detection to fault correction. evaluate memory responses, MBIST streamlines this
Chip yield is greatly increased by methods such as BISR, procedure. By making controllability and observability easier,
which not only detect defective cells but also replace them this interface reduces the difficulties associated with testing
with spare rows and columns. To reduce area and embedded memories. External test patterns are less necessary
performance overhead and increase repair efficiency, when using the FSM's test patterns for memory testing.
sophisticated redundancy analysis engines are used. Memory defects, such as those in RAMs and ROMs, are
Furthermore, advanced algorithms for realistic defect found through memory tests that use specialised algorithms.
coverage have been introduced, guaranteeing the efficient Detecting multiple failures with minimal test steps and time
detection and correction of both single-bit and multi-bit faults. is possible with two of the most significant algorithms.
BIST, BISD (Built-In Self-Diagnosis), BIRA, and BISR
work together to create a strong ecosystem that facilitates
lifetime reliability, field repair, and manufacturing testing.
Memory testing used to be primarily concerned with finding
functional errors, but as process nodes get smaller and circuit
complexity rises, defect-oriented testing is now required. Jee
demonstrated that fault coverage by itself does not ensure
high-quality memory testing by conducting a defect-oriented
analysis of memory BIST (Built-In Self-Test) tests. It was Figure 2: MBIST Model
shown that handling order and memory layout complexities
has a major impact on defect detection by utilising realistic
defect models and analog-level simulations. Their results
demonstrated the need for BIST techniques that can enhance
defect coverage for embedded memories while being
sensitive to the topological distribution of defects.

A. Basic Memory Model: Two-dimensional arrays of

memory cells with sense amplifiers and row and column
decoders make up memory models. While the column
decoder decodes the address to enable related column cell
arrays, the row decoder decodes the address and enables rows
based on it. A sense amplifier, which is connected to the
memory cell, detects, amplifies, and transmits the data that is
stored in the memory cell array. To carry out memory
operations, specialised circuitry receives the Read or Write
Fig 3: MBIST architecture at the chip level
enable signal. The number of clock cycles needed to write
and read data into and out of a memory cell is used to analyse Memory Repair: The process of fixing flaws in an IC's
memory performance. 1T DRAM and 6T SRAM are memory blocks found during memory testing is known as
common memory models. memory repair. Commonly used is repairable RAM with
reconfiguration circuits and redundancies. Using redundancy
logic, the built-in self-repair (BISR) technique improves
memory yield. Spare rows and columns are examples of
redundant memory locations found in repairable memories.
The fusebox, BIST circuit, BISR circuit, and repairable RAM
with a repair access port are important parts. Memory testing
compares the golden reference value with actual data using a
comparator to determine memory status. Failure information,
including failed row and address, is triggered by the BIRA
FSM and gathered from the memory. Using redundant rows
and columns, the system calculates the solution and
determines which failures can be fixed. Signals such as RRA
(repair row address), RAE (row address enable), CRA
(column repair address), and CAE (column address enable)
are produced by the BIRA FSM. The repair signatures are
moved to the repair register chain after being loaded into fuse
Fig1: Basics of Memory Architecture
registers. An address mapping process is used to get around
B. MBIST: External test patterns are used as a stimulus to the problematic memory location, and failing addresses are
verify the fabricated chip design on automated equipment. kept in BISR registers. A chain of registers in the BISR circuit
transfers data to the BISR controller. The fuse box stores patterns, and address information. The complexity of an
information about memory repair, and the BISR controller algorithm is expressed in terms of N, with higher complexity
writes the compressed scan chain content to it. Following the resulting in longer test times. The March algorithm detects
production test, the fusebox, a non-volatile memory, blows various memory faults, including stuck-at, stuck-open,
the fuse to fix the memory. transition, and destructive read faults.

A. Stuck at fault: The model focuses on the concept of

stuck-at faults, where a memory cell is permanently confined
to a logic 0 or 1 value, regardless of any written value. To
detect these faults, a logic 1 must be read from the cell under
test, while a logic 0 must be read. There can be two types of
stuck-at faults: stuck at 1 fault and stuck at 0 fault. The
notation for these faults is < ∀/0 >, indicating that the cell
response is 0 for any operation on the cell, and < ∀/1 >,
indicating that the cell response is 0 for any operation.

B. Stuck open fault: A stuck open fault happens when a

switch or word line discontinuity stays open all the time. In
this model, an open word line prevents access to a memory
cell. Examining the x or 1 value of the defective memory cell
Fig 4: Self-Repair Architecture is necessary to identify stuck-open faults.

Memory has a major impact on yield and is an essential part C. Transient Faults: Rising and falling transient faults are
of SoC design. Replicated or spare storage cells are two types of transient faults in memory cells. Cell responses
frequently added to divert malfunctioning cells to redundant are only 0 for rising faults and 1 for falling faults. When a
ones in order to prevent loss. Memory repair can be done in a memory cell fails to change from a logic 0 to a logic 1 value
row, a column, or both. Analysing memory failures and (up transition fault) or from a logic 1 to a logic 0 value (down
figuring out the repair signature for memories that can be transition fault), this is known as a transition fault. Since the
repaired are steps in the process. The repair signature is faulty cell cannot transition after a non-faulty transition takes
determined by the Built-In Redundancy Analysis (BIRA) place, it behaves like a stuck-at fault, making these faults
module using the implemented memory redundancy scheme special cases of stuck-at faults. The cell being tested must be
and memory failure data. The repair signature is kept in BIRA storing a logic 0, write a logic 1, and be read before a logic 0
registers so that ATE devices or MBIST Controllers can is written to it in order to identify transition faults. Before a
process it further. After that, the repair signature is sent to the logic 1 is written to the cell, it must be read, write a logic 0,
scan chain of the repair register for chip design-level Fusebox and store a logic 1 in order for there to be a down transition
programming. TAP and specific repair register scan chains fault.
are used to control a fusebox's reading and writing. The repair
data is instantly burned into the eFuse array after being D. Fault in Data Retention: This type of fault model appears
scanned and compressed. All redundancies are fixed as a when a cell loses the ability to store data or hold data for a
result of the repair information being automatically loaded predetermined amount of time. Here, the memory cell's data
and decompressed in the repair registers following an on-chip is lost on its own, independent of READ or WRITE
reset. The repaired memories are then subjected to BIST in operations.
order to confirm their accuracy.
E. Coupling faults: Inversion Coupling Fault (CFin),
Idempotent Coupling Fault (CFid), and State Coupling Faults
(CFst) are the three categories of coupling faults. When one
cell transition results in the inversion of other cell content,
this is known as an inversion fault. When a cell transition
results in a constant value in another cell's content, this is
known as an idempotent fault. Only when the coupled cell is
in this state are state coupling faults forcing it to a particular
value.

F. Destructive read faults: Cell values continuously flip as

a result of read operation errors. Although the correct value
may be read after the initial read, destructive read faults alter
Fig 5: Memory Built-in Self Repair (BISR) the contents of memory cells during read access. The cell
III. MEMORY FAULTS needs to be initialised and read several times in quick clock
cycles in order to identify destructive read faults.

Memory test algorithms are sequences of test elements used

to test memory cells, including read or write operations, data
 IV. ALGORITHMS lead to data corruption, system crashes, or even
catastrophic failures. By employing comprehensive
A. MBIST Algorithms: Special algorithms are used to test memory testing techniques, chip designers can detect
memories in order to identify any flaws. RAMs and ROMs and rectify these faults, enhancing the reliability and
can be tested using a variety of different algorithms. Two of robustness of the VLSI chip.
the most significant algorithms for memory testing are ⚫ Performance Optimization: Memory testing enables
explained below. With the least amount of test steps and test designers to evaluate the performance characteristics of
time, these algorithms are able to identify multiple memory memory elements, such as access time, read and write
failures. speeds, and power consumption. By identifying and
rectifying performance bottlenecks, designers can
B. Checkerboard Algorithm: In a chequerboard pattern, the optimize the memory subsystem for enhanced speed and
1s and 0s are written into different memory locations within efficiency.
the cell array. In order to place each neighbouring cell in a ⚫ Yield Enhancement: VLSI layout design fabrication
different group, the algorithm splits the cells into two involves complex manufacturing processes that can
alternate groups. The chequerboard pattern is primarily used introduce defects in the memory elements. Conducting
to activate failures brought on by SAF, leakage, and cell-to- extensive memory testing during the design phase can
cell shorts. The algorithm involves writing, reading, and identify potential fabrication-related issues early on,
inverse checkerboards with up addressing order. allowing for modifications and improvements that result
in higher chip yield.
⚫ Compatibility Assurance: Memory testing ensures
compatibility between the VLSI chip and its intended
application environment. Different applications may
have unique memory requirements, such as specific data
transfer rates or protocols. Through rigorous testing,
designers can validate the chip’s adherence to these
requirements, ensuring seamless integration into the
target system.
Figure 6: Read/Write in Checkerboard Algorithm
⚫ Advanced Memory Testing Techniques: To
C. March algorithm: March tests are well-liked algorithms accomplish through memory testing, designers employ
for testing memory that are quicker and easier to use than techniques such as Built-In Self-Test (BIST), March
other approaches. They write and read values from known algorithms, and Memory Built-In Self-Repair (MBISR).
memory locations using patterns that "march" up and down BIST allows for on-chip testing, enabling memory self-
memory addresses. The size and word length of memory are testing without external equipment. March algorithms
also assessed by these tests. One common algorithm targets are widely used for detecting common memory faults,
faults such as stuck-at, transition, address, inversion, and including stuck-at, transition, and coupling faults.
idempotent coupling faults. It consists of ten steps of reading MBISR techniques provide automatic repair
and writing in both ascending and descending address. Each mechanisms, allowing faulty memory elements to be
of the March elements in the March test algorithm is defined bypassed or repaired during runtime. At Tessolve, we
by two crucial factors: operations and data. The March have access to the latest tools, techniques, and
algorithm has a complexity of 4N and is written as (w0; (r0, methodologies, such as expertise in SystemVerilog,
w1); (r1). The algorithm makes use of the following notations: SystemC, e/eRM, UVM, and Formal. We can provide
W0 (write to the current location, applying 0 to the least significant benefits to our clients whether you are a large
significant input bit), R0 (read the current location and corporate or small startup.
compare the most significant output bit to 0), R1 (read the
current location and compare the most significant output bit The process of creating intricate integrated circuits by
to 1), and A (number of address locations, row address packing a lot of transistors onto one chip is known as VLSI
locations, column address locations). The majority of (Very Large-Scale Integration). It includes fabrication, logic
industry standards use the SMarchCKBD algorithm, which design, layout design, and architecture design. Achieving
combines the Serial March and Checkerboard algorithms, to high performance, low power consumption, and decreased
identify memory failures in MBIST controllers. The area utilisation is the primary objective. As data and
algorithm reads zeros, writes one, increases the address, and instruction storage components, memory components like
then decreases the address. This technique makes it possible RAM and ROM are essential to VLSI chips. In digital VLSI
to quickly access rows and columns in order to identify designs, memory testing refers to methods and procedures
memory failures. used to confirm the functionality, performance, and integrity
of the memory blocks. Tesslove provides IP and SOC-level
verification using C/C++ and SV-UVM methodologies,
V. THE IMPORTANCE OF MEMORY TESTING round-the-clock testing support, and tools like formal
verification and PSS for verification productivity.
⚫ Fault Detection: Memory testing helps identify
potential faults or defects in memory elements, ensuring VI. CONCLUSION
the chip operates flawlessly. Faulty memory cells can
In order to guarantee the dependability of intricate and dense https://vlsiuniverse.medium.com/basics-of-memory-testing-in-vlsi-
memory-bist-f16b4876498a
memory components, memory testing is essential in
[2] Maven Silicon, “What is Memory Test?,” Maven Silicon Blog,
contemporary digital VLSI design. Effective, automated on- [Online]. Available: https://www.maven-silicon.com/blog/what-is-
chip solutions such as Built-In Self-Test, Built-In Self- memory-test/
Diagnosis, Built-In Redundancy Analysis, and Built-In Self- [3] Tessolve, “Memory Testing in Digital VLSI Designs,” Tessolve Blogs,
Repair have replaced conventional external testing methods. Jan. 10, 2023. [Online]. Available:
These methods increase fault coverage, lower manufacturing https://www.tessolve.com/blogs/memory-testing-in-digital-vlsi-
designs/
costs, and facilitate quicker testing. Redundancy and self-
[4] eInfochips, “Memory Testing: An Insight into Algorithms and Self-
repair mechanisms preserve faulty memories, increasing Repair Mechanism,” eInfochips Blog, Nov. 14, 2022. [Online].
yield, while sophisticated memory test algorithms, such as Available: https://www.einfochips.com/blog/memory-testing-an-
March tests, identify static and dynamic faults. insight-into-algorithms-and-self-repair-mechanism/
[5] A. Jee, “Defect-Oriented Analysis of Memory BIST Tests,” in Proc.
IEEE Int. Workshop Memory Technol., Design and Testing (MTDT),
2002, pp. 91–96, doi: 10.1109/MTDT.2002.1028533.
[6] S. K. Thakur, R. A. Parekhji, and A. N. Chandorkar, “On-Chip Test
and Repair of Memories for Static and Dynamic Faults,” in Proc. Int.
Test Conf. (ITC), 2006, pp. 1–10, doi: 10.1109/TEST.2006.297654.
[7] V.-K. Kim and T. Chen, “On Comparing Functional Fault Coverage
and Defect Coverage for Memory Testing,” IEEE Trans. Comput.-
Aided Design Integr. Circuits Syst., vol. 18, no. 11, pp. 1676–1685,
Nov. 1999, doi: 10.1109/43.811465.
[8] J.-C. Yeh, K.-L. Cheng, Y.-F. Chou, and C.-W. Wu, “Flash Memory
Testing and Built-In Self-Diagnosis With March-Like Test
REFERENCES Algorithms,” IEEE Trans. Comput.-Aided Design Integr. Circuits
Syst., vol. 26, no. 6, pp. 1101–1111, Jun. 2007, doi:
10.1109/TCAD.2007.895808.
[1] VLSI Universe, “Basics of Memory Testing in VLSI - Memory BIST,”
Medium, Sep. 5, 2020. [Online]. Available: