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UNIT-3
8086 INTERFACING

S.NO TOPIC PAGE

1 3.1 SEMICONDUCTOR MEMORY INTERFACING 2

2 3.2 8255 BLOCK DIAGRAM: 7

3 3.3 CONTROL WORD FORMATS OF 8255: 10

4 3.4 8251 BLOCK DIAGRAM 12

5 3.5 CONTROL WORD OF 8251: 15

6 3.6 8259 BLOCK DIAGRAM: 19

7 3.7 8259 COMMAND WORDS: 21

8 3.8 DMA INTERFACING AND NEED OF DMA 30

9 3.9 BLOCK DIAGRAM OF 8237 DMA 32

10 3.10 8255 INTERFACING

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UNIT-3
8086 INTERFACING

3.1: SEMICONDUCTOR MEMORY INTERFACING

Semiconductor memories are of two types. viz RAM (Random Access Memory) and ROM
(Read Only Memory). For example, 4Kx 8 or 4k byte memory Contains 4096 locations, where
each location contains 8-bit data and only one of the 4096 locations can be selected at a time.
Once a location is selected all the bits in it are accessible using a group of conductors called 'data
bus.

Thus if the microprocessor has n address lines, then it is able to address at the most N locations
of memory, where 2n = N. However, if out of N locations only P memory locations are to be
interfaced, then the least significant p address lines out of the available n lines can be directly
connected from the microprocessor to the memory chip while the remaining (n-p) higher order
address lines may be used for address decoding (as inputs to the chip selection logic).

The memory address depends upon the hardware circuit used for decoding the chip select (CS).
The output of the decoding circuit is connected with the CS pin of the memory chip.

Procedure of static memory interfacing with 8086 is briefly described as follows

1. Arrange the available memory chips so as to obtain 16-bit data bus width. The upper 8-bit
bank is called 'odd address memory bank' and the lower 8-bit bank is called even address
memory bank', as described in memory organization.

2. Connect available memory address lines of memory chips with those of the microprocessor
and also connect the memory RD and WR inputs to the corresponding processor control signals.
Connect the 16-bit data bus of the memory bank with that of the microprocessor 8086.

3. The remaining address lines of the microprocessor, BHE and A0 are used for decoding the
required chip select signals for the odd and even memory banks. The CS of memory is derived
from the O/P of the decoding circuit.

In Case of ROM after reset the IP and CS are initialized from address FFFF0. Hence the address
must lie in EEPROM.

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PROBLEM

It is required to interface two chips of 32K x 8 ROM and four chips of 32K x 8 RAM with 8086
according to the following map.
ROM 1 and 2 F0000H- FFFFFH, (FFFF0 should lie in ROM)
RAM 1 and 2 D0000H- DFFFFH (if not given you can star anywhere)
RAM 3 and 4 E0000H- EFFFFH
For 32kb 15 address pins are required those are A15-A1
A0 to select even bank
BHE to select odd bank
A19-A16 lines are used to allow A0 and BHE for chip selection

ROM 1 and 2 F0000H- FFFFFH

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Need of 8255 (PPI)

The 8255A is a general purpose programmable I/O device designed to transfer the data from I/O
to interrupt I/O under certain conditions as required. It can be used with almost any
microprocessor.

It consists of three 8-bit bidirectional I/O ports (24I/O lines) which can be configured as per the
requirement.

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3.2: 8255 Block Diagram:

Fig. 14.2 shows the internal 8255 block diagram. It consists of data bus buffer, control logic and
Group A and Group B controls.

Data Bus Buffer:

This tri-state bi-directional buffer is used to interface the internal data bus of 8255 to the system
data bus. Input or Output instructions executed by the CPU either Read data from, or Write data
into the buffer. Output data from the CPU to the ports or control register, and input data to the
CPU from the ports or status register are all passed through the buffer.

Control Logic:
The control logic block accepts control bus signals as well as inputs from the address bus, and
issues commands to the individual group control blocks (Group A control and Group B control).

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It issues appropriate enabling signals to access the required data/control words or status word.
The input pins for the control logic section are described here.

Group A and Group B Controls:

Each of the Group A and Group B control blocks receives control words from the CPU and
issues appropriate commands to the ports associated with it. The Group A control block controls
Port A and PC7-PC4 while the Group B control block controls Port B and PC3-PC0.
Port A :
This has an 8-bit latched and buffered output and an 8-bit input latch. It can be programmed in
three modes: mode 0, mode 1 and mode 2.

Port B :
This has an 8-bit data I/O latch/ buffer and an 8-bit data input buffer. It can be programmed in
mode 0 and mode 1.

Port C :
This has one 8-bit unlatched input buffer and an 8-bit output latch/buffer. Port C can be splitted
into two parts and each can be used as control signals for ports A and B in the handshake mode.
It can be programmed for bit set/reset operation.

Modes of Operation of 8255 Microprocessor:

Bit Set-Reset (BSR) Mode:

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The individual bits of Port C can be set or reset by sending out a single OUT instruction to the
control register. When Port C is used for control/status operation, this feature can be used to set
or reset individual bits.

I/O Modes:
Mode 0 : Simple input/output:
In this mode, ports A and B are used as two simple 8-bit I/O ports and Port C as two 4-bit ports.
Each port (or half – port, in case of C) can be programmed to function as simply an input port or
an output port. The input/output features in Mode 0 are as follows :

1. Outputs are latched.

2. 2. Inputs are buffered, not latched.
3. Ports do not have handshake or interrupt capability.

Mode 1 : Input/output with handshake:

In this mode, input or output data transfer is controlled by handshaking signals. Handshaking
signals are used to transfer data between devices. Whose data transfer speeds are not same. For
example, computer can send data .to the printer with large speed but printer can’t accept data and
print data with this rate. So computer has to send data with the speed with which printer can
accept. This type of data transfer is achieved by using handshaking signals along-with data
signals. Fig. 14.3 shows data transfer between computer and printer using handshaking signals.

These handshaking signals are used to tell computer whether printer is ready to accept the data or
not. If printer is ready to accept the data then after sending data on data bus, computer uses
another handshaking signal (STB) to tell printer that valid data is available on the data bus.

The 8255 Pin Diagram mode 1 which supports handshaking has following features.

1. Two ports (A and B) function as 8-bit I/O ports. They, can be configured either as input
or output ports.
2. Each port uses three lines from Port C as handshake signals. The remaining two lines of.
Port C can be used for simple I/O functions.
3. Input and output data are latched.
4. Interrupt logic is supported.

5. Mode 2 : Bi-directional I/O data transfer:

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This mode allows bi-directional data transfer (transmission and reception) over a single 8-bit
data bus using handshaking signals. This feature is available only in Group A with Port A as the
8-bit bidirectional data bus; and PC3 – PC7 are used for handshaking purpose. In this mode, both
inputs and outputs are latched. Due to use of a single 8-bit data bus for bi-directional data
transfer, the data sent out by the CPU through Port A appears on the bus connecting it to the
peripheral, only when the peripheral requests it.

The remaining lines of Port C i.e. PC0-PC2 can be used for simple I/O functions. The Port
B can be programmed in mode 0 or in mode 1. When Port B is programmed in mode 1, PC 0-
PC2 lines of Port C are used as handshaking signals.

3.3: Control Word Formats of 8255:

A high on the RESET pin causes all 24 lines of the three 8-bit ports to be in the input mode. All
flip-flops are cleared and the interrupts are reset. This condition is maintained even after the
RESET goes low. The ports of the 8255 Pin Diagram can then be programmed for any other
mode by writing a single control word into the control register, when required.

For Bit Set/Reset Mode:

Fig. 14.4 shows bit set/reset control word format.

The eight possible combinations of the states of bits D 3 – D1 (B2 B1 B0) in the Bit Set-Reset
format (BSR) determine particular bit in PC0 – PC7 being set or reset as per the status of bit D0.

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A BSR word is to be written for each bit that is to be set or reset. For example, if bit
PC3 is to be set and bit PC4 is to be reset, the appropriate BSR words that will have to be loaded
into the control register will be, 0XXX0111 and 0XXX1000, respectively, where x is don’t care.

The BSR word can also be used for enabling or disabling interrupt signals generated by
Port C when the 8255 Pin Diagram is programmed for Mode 1 or 2 operations. This is done by
setting or resetting the associated bits of the interrupts. This is described in detail in next section.

For I/O Mode:

The mode definition format for I/O mode is shown in Fig. 14.5. The control words for both,
mode definition and Bit Set –Reset are loaded into the same control register, with bit D7 used for
specifying whether the word loaded into the control register is a mode definition word or Bit Set-
Reset word.

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If D7 is high, the word is taken as a mode definition word, and if it is low, it is taken as a
Bit Set-Reset word. The appropriate bits are set or reset depending on the type of operation
desired, and loaded into the control register.

Need of 8251(USART)
8251 universal synchronous asynchronous receiver transmitter (USART) acts as a mediator
between microprocessor and peripheral to transmit serial data into parallel form and vice versa.
1. It takes data serially from peripheral (outside devices) and converts into parallel data.
2. After converting the data into parallel form, it transmits it to the CPU.
3. Similarly, it receives parallel data from microprocessor and converts it into serial form.
4. After converting data into serial form, it transmits it to outside device (peripheral).

3.4: 8251 Block Diagram

Fig. 14.37 shows the 8251 Block Diagram in Microprocessor. It includes : Data bus buffer,
Read/Write control logic, modem control, Transmit buffer, Transmit Control, Receiver Buffer
and Receiver control.

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Data Bus Buffer:

This tri-state, bi-directional, 8-bit buffer is used to interface 8251 Block Diagram in
Microprocessor to the system data bus. Along with the data, control word, command words and
status information are also transferred through the Data Bus Buffer.

Read/Write control logic:

This functional block accepts inputs from the system control bus and generates control signals
for overall device operation. It decodes control signals on the 8086 control bus into signals which
controls the internal and external I/O bus. It contains the control word register and command
word register that stores the various controls formats for the device functional definition.

Transmit Buffer:
The transmit buffer accepts parallel data from the CPU, adds the appropriate framing
information, serializes it, and transmits it on the TxD pin on the falling edge of TxC.

It has two registers: A buffer register to hold eight bits and an output register to convert eight
bits into a stream of serial bits. The CPU writes a byte in the buffer register, Which is transferred

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to the output register when it is empty. The output register then transmits serial data on the TxD
pin. In the asynchronous mode the transmitter always adds START bit; depending on how the
unit is programmed, it also adds an optional even or odd parity bit, and either 1, 1 1/2, or 2 STOP
bits. In synchronous mode no extra bits (other than parity, if enable) are generated by the
transmitter.

8251 Transmitter Control :

It manages all activities associated with the transmission of serial data. It accepts and issues
signals both externally and internally to accomplish this function.

TxRDY (Transmit Ready ) : This output signal indicates CPU that buffer register is empty and
the USART is ready to accept a data character. It can be used as an interrupt to the system or, for
polled operation, the CPU can ‘check TxRDY using the status read operation. This signal is reset
when a data byte is loaded into the buffer register.

TxE (Transmitter Empty) : This is an output signal. A high on this line indicates that the
output buffer is empty. In the synchronous mode, if the CPU has failed to load a new character in
time, TxE will go high momentarily as SYN characters are loaded into the transmitter to fill the
gap in transmission.

TxC (Transmitter Clock) : This clock controls the rate at which characters are transmitted by
USART. In the synchronous mode TxC is equivalent to the ‘baud rate, and is supplied by the
modem. In asynchronous mode TxC is 1, 16, or 64 times the baud rate. The clock division is
programmable. It can be programmed by writing proper mode word in the mode set register.

Receiver Buffer:
The receiver accepts serial data on the RxD line, converts this serial data to parallel format,
checks for bits or characters that are unique to the communication technique and sends an
“assembled” character to the CPU.

When 8251 is in the asynchronous mode and it is ready to accept a character, it looks for a low
level on the RxD line. When it receives the low level, it assumes that it is a START bit and
enables an internal counter, At a count equivalent to one-half of a bit time, the RxD line is
sampled again. If the line is still low, a valid START bit is detected and the 8251A proceeds to
assemble the character.

After successful reception of a START bit the 8251A receives data, parity and STOP bits, and
then transfers the data on the receiver input register. The data is then transferred into the receiver
buffer register.

In the synchronous mode the receiver simply receives the specified number of data bits and
transfers them to the receiver input register and then to the receiver buffer register.

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Receiver Control:
It manages all receiver-related activities. Along with data reception, it does false start bit
detection, parity error detection, framing error detection, sync detection and break detection.

RxRDY (Receiver Ready) : This is an output signal. It goes high (active), when the USART has
a character in the buffer register and is ready to transfer it to the CPU. This line can be used
either to indicate the status in the status register or to interrupt the CPU. This signal is reset when
a data byte from receiver buffer is read by the CPU.

RxC (Receiver Clock) : This clock controls the rate at which the character is to be received by
USART in the synchronous mode. RxC is equivalent to the baud rate, and is supplied by the
modem. In asynchronous mode RxC is 1, 16, or 64 times the baud rate. The clock division is
programmable. It can be programmed by writing proper mode word in the mode set register.

Modem Control:
The 8251 has a set of control inputs and output’s that can be used to simplify the interface to
almost any modem. It provides control circuitry for the generation of RTS and DTR and the
reception of CTS and DSR. In addition, a general purpose inverted output and a general purpose
input are provided. The output is labeled DTR and the input is labeled DSR. DTR can be
asserted by setting bit 2 of the command instruction; DSR can be sensed as bit 7 of the status
register. When used as a modem control signal DTR indicates that the terminal is ready to
communicate and DSR indicates that it is ready for communication.

3.5: Control Word of 8251:

The Control Word of 8251 defines the complete functional definition of 8251 Block Diagram in
Microprocessor and they must be loaded before any transmission or reception. The control words
of Block Diagram of 8251 Microcontroller are split into two formats

1. Mode instruction
2. Command instruction

Mode Instruction:
Fig. 14.38 shows the mode instruction format of 8251.

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The instruction can be considered as four 2-bit fields. The first 2-bit field (D1-D0) determines
whether the USART is to operate in the synchronous (00) or asynchronous mode. In the
asynchronous mode, this field determines the division factor for clock to decide the baud rate.

For example, if D1 and D0 are both ones, the RxC and TxC will be divided by 64 to establish the
baud rate.

The second 2-bit field (D3-D2) determines number of data bits in one character. With this 2-bit
field we can set character length from 5-bits to 8 bits.

The third 2-bit field, (D5-D4), controls the parity generation. The parity bit is added to the data
bits only if parity is enabled.

The last field, (D7-D6), has two meanings depending on whether operation is to be in the
synchronous or asynchronous mode. For asynchronous mode, (i.e. D 1D0 ≠ 00), it controls the
number of STOP bits to be transmitted with the character.

In synchronous mode, (i.e. D1D0) = 00) this field controls the synchronizing process. It decides
whether to operate with external synchronization or internal synchronization and whether to
transmit single synchronizing character or two synchronizing characters.

Command Instruction:

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After the mode instruction, command character should be issued to the USART. It controls the
operation of the USART within the basic frame work established by the mode instruction. Fig.
14.39 shows command instruction format.

It does function such as : Enable Transmit/Receive; Error Reset and modem Control.

8251A Status Word:

In the data communication systems it is often necessary to examine the “status” of the transmitter
and receiver. It is also necessary for CPU to know if any error has occurred during
communication. The 8251 allow the programmer to read above mentioned information from the
status register any time during the functional operation. Fig. 14.40 shows the format of status
register.

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Error Definitions:
Parity Error : At the time of transmission of data an even or odd parity bit is inserted in the data
stream. At the receiver end, if parity of the character does not match with the pre-defined parity,
parity error occurs.
Overrun Error : In the receiver section received character is stored in the receiver buffer. The
CPU is supposed to read this character before reception of the next character. But if CPU fails in
reading the character loaded in the receiver buffer, the next the received character replaces the
previous one and the OVERRRUN Error occurs.
Framing Error : If valid stop bit is not detected at the end each character framing error occurs.
All these errors, when occur, set the corrosponding bits in the status register. These error bits are
reset by setting ER bit in the command instruction.

Need of 8259 PIC

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Intel 8259 is a Programmable Interrupt Controller (PIC). There are 5 hardware interrupts
and 2 hardware interrupts in Intel 8085 and Intel 8086 microprocessors respectively. But by
connecting Intel 8259 with these microprocessors, we can increase their interrupt handling
capability. Intel 8259 combines the multi-interrupt input sources into a single interrupt output.
Interfacing of single PIC provides 8 interrupts inputs from IR0-IR7. For example, interfacing
of 8085 and 8259 increases the interrupt handling capability of 8085 microprocessor from 5 to
8 interrupt levels.
Features of Intel 8259 PIC are as follows:
1. Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor.
2. It can be programmed either in level triggered or in edge triggered interrupt level.
3. We can mask individual bits of interrupt request register.
4. We can increase interrupt handling capability upto 64 interrupt level by cascading further
8259 PICs.
5. Clock cycle is not required.

3.6: 8259 Block Diagram:

Fig. 14.71 shows the internal 8259 Block Diagram. It includes eight blocks: data bus buffer,
read/write logic, control logic, three registers (IRR, ISR and IMR), priority resolver, and cascade
buffer.

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Data Bus Buffer:

The data bus buffer allows the 8085 to send control words to the 8259A and read a status word
from the 8259 Block Diagram. The 8-bit data bus buffer also allows the 8259A to send interrupt
Type and address of the interrupt service subroutine to the 8085.

Read/Write Logic:
The RD and WR inputs control the data flow on the data bus when the device is selected by
asserting its chip select (CS) input low.

Control Logic:
This block has an input and an output line. If the 8259A is properly enabled, the interrupt request
will cause the 8259A to assert its INT output pin high. If this pin is connected to the INTR pin of
an 8085/8086 and if the 8085/8086 Interrupt Enable (IE) flag is set, then this high signal will
cause the 8085/8086 to respond INTR as explained earlier.

Interrupt Request Register (IRR):

The IRR is used to store all the interrupt levels which are requesting the service. The eight
interrupt inputs set corresponding bits of the Interrupt Request Register upon service request.

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Interrupt Service Register (ISR):
The Interrupt Service Register (ISR) stores all the levels that are currently being serviced.

Interrupt Mask Register (IMR):

Interrupt Mask Register (IMR) stores the masking bits of the interrupt lines to be masked. This
register can be programmed by an Operation Command Word (OCW). An interrupt which is
masked by software will not be recognised and serviced even if it sets the corresponding bits in
the IRR.

Priority Resolver:
The priority resolver determines the priorities of the bits set in the IRR. The bit corresponding to
the highest priority interrupt input is set in the ISR during the INTA input.

Cascade Buffer Comparator:

This section generates control signals necessary for cascade operations. It also generates Buffer-
Enable signals. As stated earlier, the 8259 can be cascaded with other 8259s in order to expand
the interrupt handling capacity to sixty-four levels.

In such a case, the former is called a master, and the latter are called slaves. The 8259 can be
set up as a master or a slave by the SP/EN pin.

CAS 0 — CAS 2
For a master 8259, the CAS0-CAS2 pins are output pins,
and for slave 8259, these are input pins.
When the 8259 is a master (that is, when it accepts interrupt requests from other 8259s), the
CALL opcode is generated by the Master in response to the first INTA. The vector address must
be released by the slave 8259. The master sends an identification code of three-bits to select one
out of the eight possible slave 8259s on the CAS 0-CAS2 lines. The slave 8259s accept these three
signals as inputs (on their CAS0 – CAS2 pins) and compare the code sent by the master with the
codes assigned to them during initialization. The slave thus selected (which had originally placed
an interrupt request to the master 8259) then puts the address of the interrupt service routine
during the second and third INTA pulses from the CPU.
SP / EN (Slave Program /Enable Buffer):
The SP/EN signal is tied high for the master. However it is grounded for the slave.

3.7 8259 Programmable Interrupt Controller Command Words:

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The 8259 Programmable Interrupt Controller requires two types of command words.
Initialization Command Words (ICWs) and Operational Command Words (OCWs).

The 8259 Programmable Interrupt Controller can be initialized with four ICWs; the first two are
compulsory, and the other two are optional based on the modes being used. These words must be
issued in a given sequence.

After initialization, the 8259A can be set up to operate in various modes by using three different
OCWs; however, they are not necessary to be issued in a specific sequence

Initialization Command Word 1 (ICW1):

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Fig. 14.76 shows the Initialization Command Word 1(ICW1). A write command issued to the
8259 with A0 = 0 and D4 = 1 is interpreted as ICW1, which starts the initialization sequence. It
specifies,
1. Single or multiple 8259As in the system
2. 4 or 8 bit interval between the interrupt vector locations.
3. The address bits A7 – A5 of the CALL instruction. (3 bits of lower byte address of CALL
are given by user, rest bits are inserted by 8259A)
4. Edge triggered or level triggered interrupts.
5. ICW4 is needed or not.

Initialization Command Word 2 (ICW2):

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Fig. 14.77 shows the Initialization command Word 2 (ICW2).

A write command following ICW1, with A0 = 1 is interpreted as ICW2. This is used to load the
high order byte of the interrupt vector address of all the interrupts.

Initialization Command Word 3 (ICW3):

ICW3 is required only if there is more than one 8259 in the system and if they are
cascaded. An ICW3 operation loads a slave register in the 8259 Programmable Interrupt
Controller. The format of the byte to be loaded as an ICW3 for a master 8259 or a slave is shown
in the Fig. 14.78. For master, each bit in ICW3 is used to specify whether it has a slave 8259
attached to it on its corresponding IR (Interrupt Request) input. For slave, bits D 0 – D2 of ICW3
are used to assign a slave identification code (slave ID) to the 8259 Programmable Interrupt
Controller.

Initialization Command Word 4 (ICW4):

It is loaded only, if the D0 bit of ICW1 is seta The format of ICW4 is shown in Fig. 14.79.
It specifies,

 Whether to use special fully nested mode or non special fully nested mode.

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 Whether to use buffered mode or non buffered mode.
 Whether to use Automatic EOI or Normal EOI.
 CPU used, 8086/8088 or 8085.

Operation Command Words (OCWs):

After initialization, the 8259 Programmable Interrupt Controller is ready to process interrupt
requests. However, during operation, it might be necessary to change the mode of processing the
interrupts. Operation Command Words (OCWs) are used for this purpose. They may be loaded
anytime after the initialization of 8259 to dynamically alter the priority modes.

Operation Command Word 1 (OCW 1):

A Write command to the 8259 with A0 = 1 (after ICW2) is interpreted as OCW1. OCW1 is used
for enabling or disabling the recognition of specific interrupt requests by programming the IMR.
M = 1 indicates that the interrupt is to be masked, and M = 0 indicates that it is to be unmasked
as shown in Fig. 14.80.

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Operation Command Word 2 (OCW2):

A Write command with A0 = 1 and D4 D3 = 00 is interpreted as OCW2. The R (Rotate), SL
(Select-Level), EOI bits control the Rotate and End Of Interrupt Modes and combinations of the
two. Fig. 14.81 shows the Operation Command Word format. L2-L0 are used to specify the
interrupt level to be acted upon when the SL bit is active.

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Operation Command Word 3 (OCW3):
OCW3 is used to read the status of the registers; and to set or reset the Special Mask and Polled
modes. Fig. 14.82 shows format of operation command word 3.

8259 Status Read Operations:

The status of the Interrupt Request Register, the Interrupt-Service Register, and the Interrupt
Mask Regiter of the 8259 may be read by issuing appropriate Read commands as described
further.

IRR Status Read:

An OCW3 with RR (Read Register) = 1 and RIS (Read ISR) = 0 set up the 8259 for a status read
of the Interrupt Request Register.

When the 8259 is not in the Polled mode, after it is set up for. an IRR status read operation, all
Read commands with A0=1 cause the 8259 to send the IRR status word.

ISR Status Read:

An OCW3 with RR = 1 and ISR = 1 sets up the 8259 for a status read of the Interrupt-Service
Register. A subsequent read command issued to the 8259 will cause the 8259 to send the
contents of the ISR onto the data bus.

IMR Status Read:

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A Read command issued to the 8259 Programmable Interrupt Controller with A0 = 1 (with RD,
CS = 0 ) causes the 8259 to put the contents of the Interrupt Mask Register on the data bus.
OCW3 is not required for a status read of the IMR.
As described earlier, the sequence shown in flowchart must be followed to initialize 8259A.
According to this flow chart, an ICW1 and an ICW2 must be sent to any 8259A in the system. If
the system has any slave 8259As (cascade mode), then an ICW3 must be sent to the master, and
a different ICW3 must be sent to the slave. If the system is an 8086, or if you want to specify
certain special conditions; then you have to send an ICW4 to the master and to each slave.

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8257 DMA Controller:

In microprocessor based systems data transfer can be controlled by either software or hardware.
Upto this point we have used program instructions to transfer data from I/O device to memory or
from memory to I/O device. To transfer data by 8257 DMA Controller method microprocessor
has to do following tasks :

1. To fetch the instruction

2. To decode the instruction and
3. To execute the instruction.
To carryout these tasks microprocessor requires considerable time, so this method of data
transfer is not suitable for large data transfers such as data transfer from magnetic disk or optical
disk to memory. In such situations hardware controlled data transfer technique is used.

Software Controlled Data Transfer:

In this method programmer executes a series of instructions to carry out data transfer. The
sample flow chart and program required to transfer data from memory to I/O device is shown in
Fig. 14.59.

Hardware Controlled Data Transfer:

In this technique external device is used to control data transfer. External device generates
address and control signals required to control data transfer and allows peripheral device to

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directly access the memory. Hence this technique is referred to as Direct Memory
Access (DMA) and external device which controls the data transfer is referred to as DMA
controller. Fig. 14.60 shows that how DMA controller operates in a microprocessor system.

3.8 DMA interfacing and Need of DMA

1. In I/O data transfer, data is transferred by using microprocessor. The microprocessor will
read data from I/O device and then will write data to memory.
2. In this case, there are two operations for single data transfer. If the data is less then
microprocessor will not waste its time transferring data from I/O to memory or back.
3. But suppose data is huge then the transfer rate from I/O to memory or back will slow
down because of microprocessor intervention.
4. In such case, to speed up the process of transferring the data, I/O should have direct
access to memory.
5. It can have Direct Memory Access (DMA) but under supervision. The device which
supervises data transfer is named as DMA controller.

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1. The sequence of DMA transfer is as follows:

 Microprocessor initializes the DMAC (DMA controller) by giving the starting

address and the number of bytes to be transferred.
 An I/O device requests the DMAC to perform DMA transfer through the DREQ
line.
 The DMAC in turn sends a request signal to the microprocessor through the
HOLD line.
 The microprocessor finishes the current machine cycle and releases the system
bus (gets disconnected from it). It also acknowledges receiving the HOLD signal
through the HLDA line.
 The DMAC acquires control of the system bus. The DMAC sends the DACK
signal to the I/O peripheral and the DMA transfer begins.
 After every byte is transferred, the address register is incremented (or
decremented) and the count register is decremented.
 This continues till the count reaches zero (Terminal count). Now the DMA
transfer is completed.
 At the end of the transfer, the system bus is released by the DMAC by making
HOLD = 0. Thus microprocessor takes control of the system bus and continues its
operation.

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3.9 Block Diagram of 8237 DMA

Block Diagram of 8237 Direct Memory Access (DMA) controller

This block diagram visually represents the major functional components of the 8237
DMA controller and their interactions.

What is DMA and why is it useful?

Imagine transferring a bucket full of books from one shelf to another. Conventionally,
you’d pick up each book individually (CPU’s task), a slow and inefficient process.
Alternatively, you could grab the entire bucket in one go (DMA’s task), minimizing
individual movements and accelerating the process. In a computer system, the CPU
frequently engages in data transfers between memory and peripherals, consuming valuable
processing power. The 8237 DMA controller acts as the efficient “bucket carrier,”
streamlining data transfer and enhancing overall system performance.

How does the 8237 DMA controller work?

Let’s break down the key steps involved:

1. Channel Initialization:
o The CPU configures the 8237 by programming its registers, setting parameters like
source/destination memory addresses, transfer size, and transfer mode.
2. DMA Request:
o A peripheral device triggers a DMA transfer by sending a signal to the 8237, typically
when data is ready to be sent or received.

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3. Channel Arbitration:
o In case of simultaneous DMA requests from multiple devices, the 8237 prioritizes
channels based on pre-programmed settings.
4. Data Transfer:
o Upon access approval, the 8237 seizes control of system buses, retrieves data from the
source memory, increments the address, and writes the data to the destination memory
until the transfer size is reached.
5. DMA Acknowledgment:
o Upon completion, the 8237 signals the CPU and the peripheral device, relinquishing
control of the buses.
Benefits of using the 8237 DMA controller:
 Increased System Performance:
 By offloading data transfer tasks from the CPU, the 8237 significantly enhances overall
system responsiveness.
 Reduced CPU Load:
 The CPU can focus on other tasks while the DMA controller efficiently handles data
transfers, optimizing system efficiency.
 Improved Data Transfer Rates:
 Direct access to system buses enables faster data transfer compared to CPU-mediated
methods.
In conclusion, the 8237 DMA controller remains a powerful relic that played a pivotal role
in early computer systems, accelerating data transfer and improving overall performance.
While its significance has waned in modern architectures with integrated DMA
capabilities, understanding its workings provides valuable insights into the evolution of
computer architecture and the perpetual quest for efficient data movement

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3.10 8255 INTERFACING

INTERFACING OF STEPPER MOTOR

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Stepper motor in clockwise direction

PROGRAM

MOV AL, 80

OUT 0FFE6, AL // writing to CWR to make port as a output port

MOV AL, 88

START: OUT 0FFE0, AL

CALL DELAY

ROR AL, 01

JMP START

DELAY: MOV BX, 0FFF

GO: DEC BX

JNZ GO

RET

Stepper motor in clockwise direction with required no.of rotations

PROGRAM

MOV AL, 80 //

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OUT 0FFE6, AL // writing to CWR to make port as a output port

MOV AL, 88

MOV CX, 3E8H (// =1000D )

START: OUT 0FFE0, AL //send to port A

CALL DELAY

ROR AL, 01

JMP START

DELAY: MOV BX, 0FF0

GO : DEC BX

JNZ GO

LOOP RET

HLT

INTERFACING OF DIGITAL TO ANALOG CONVERYTER

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a) Sawtooth wave generation

PROGRAM

MOV AL, 80

MOV DX, 0FFE6

OUT DX, AL

MOV DX, 0FFE0

START: MOV AL, 00

BACK: OUT DX, AL

INC AL

CMP AL, 0FFH

JB BACK

JMP START

b) Triangular Waveform

MOV AL, 80

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OUT 0FFE6, AL

MOV AL, 00
DO1: OUT 0FFE0, AL
INC AL
CMP AL, 0FFH
JB DO1 //(AL<FF)
DO: OUT DX, AL

DEC AL
CMP AL, 00H
JA DO //(AL>00)
JMP DO1

c) Square Waveform generation

MOV AL, 80

OUT 0FFE6, AL

AGAIN: MOV AL, 00

OUT 0FFE0, AL

CALL DELAY

MOV AL, FF

OUT DX, AL

CALL DELAY

JMP AGAIN

DELAY: MOV CX, 00FFH

BACK: LOOP BACK

RET

INTERFACING OF DAC

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Interface an 8255 with 8086 to work as an I/O port. Initialize port A as output port, port B
as input port and port C as output port. Port A address should be 0740H. Write a program
to sense switch positions SW0-SW7 connected at port B. The sensed pattern is to be
displayed on port A, to which 8 LEDs are connected, while the port C lower displays
number of on switches out of the total eight switches.

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MOV DX, 0746 H // cwr add

MOV AL, 82 H

OUT DX, AL

MOV DX, 0742 H // port B add

IN AL, DX // read pB switch status

MOV DX, 0740 H // port A

OUT DX, AL // write to pA to glow leds

MOV BL, 00 H

MOV CH, 08H // count for no.of rotations

L1: ROL AL, 01 // rotate data to count on off switchs

JNC L2

INC BL

L2: DEC CH

JNZ L1

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MOV AL, BL

MOV DX, 0744H //port c address

OUT DX, AL // send to port c

HLT

Interfacing ADC-0808/0809,

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Analog to Digital Converter (ADC) • The ADC is an input device to microprocessor, that sends
an initializing signal to the ADC to start the analog signal to digital conversion process. The start
of conversion signal is a pulse of a specific duration

• The process of analog to digital conversion is a slow process and the processor has to wait for
the digital data till the conversion is over.

• After the conversion, the ADC sends the End of Conversion (EoC) signal to inform the
processor about it and the result is ready at the output buffer of the ADC. The tasks of issuing
SOC pulse to ADC, reading EOC signal from the ADC and reading the digital output of the
ADC are carried out by the CPU using 8255 I/O ports

• The time taken by the ADC to calculate the equivalent digital data output from the moment of
the start of conversion is called conversion delay of the ADC

• It may range anywhere from a few microseconds, in case of fast ADCs, to even a few hundred
milliseconds in case of slow ADCs.

• Irrespective of the techniques used for conversion, general algorithm for ADC interfacing
contains the following steps

1. Ensure the stability of analog input, applied to the ADC.

2. Issue Start of Conversion (SOC) pulse to ADC

3. Read End of Conversion (EOC) signal to mark the end of conversion process

4. Read digital data output of the ADC as equivalent digital output

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PROBLEM ON 8251
1. Write the mode control word for a case of asynchronous transmission, with an 8-bit data
format, one stop bit, odd parity and 10000 baud rate. TxC clock is 150 KHz.

ANS: 01 01 11 10

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