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Lecture #03, Microprocessor_Architecture

The document provides an overview of the 8086 microprocessor architecture, highlighting its two main functional units: the Bus Interface Unit (BIU) and the Execution Unit (EU). It explains the roles of these units, including memory segmentation, instruction fetching, and execution processes. The 8086 architecture supports parallel processing, allowing both units to operate simultaneously.

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Shohag Hawlader Shanto
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4 views9 pages

Lecture #03, Microprocessor_Architecture

The document provides an overview of the 8086 microprocessor architecture, highlighting its two main functional units: the Bus Interface Unit (BIU) and the Execution Unit (EU). It explains the roles of these units, including memory segmentation, instruction fetching, and execution processes. The 8086 architecture supports parallel processing, allowing both units to operate simultaneously.

Uploaded by

Shohag Hawlader Shanto
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EEE-3103: Microprocessor and Interfacing

Lecture #3: 8086 Microprocessor

Dr. Sharnali Islam


Department of Electrical and Electronic Engineering
University of Dhaka
[email protected]

Some slides used resources from:


Prof. Sazzad M.S. Imran, PhD, EEE DU
Web resources 1
Basic Architecture of 8086
8086 microprocessor has 2 separate functional units.
- Bus Interface Unit (BIU) and
- Execution Unit (EU).

8086 architecture employs parallel processing.

BIU has
- segment registers,(CS , DS , SS ,ES)
- instruction pointer, (IP)
- address generation and bus control logic block,
- instruction queue.

EU has
- general purpose registers,(AX , BX , CX , DX)
- ALU,
- control unit,
- instruction register, (BP, DI , SI , SP)
- flag (or status) register.
2
Bus Interface Unit (BIU)

3
EU BIU
Memory Segmentation of 8086
Stack --- Interrupt & Subroutine address

Code segment → instruction codes of program.


Data segment → data, variables and constants.
Stack segment → interrupt and subroutine return addresses.
Extra segment → destination of data for string instructions.

• 8086’s 1-megabyte memory is divided into segments of


up to 64K bytes each.
msg1
• The 8086 can directly address four segments (256 K msg2

bytes within the 1 M byte of memory) at a particular result

time.

• Programs obtain access to code and data in the


segments by changing the segment register content to
point to the desired segments.
4
Execution Unit (EU)

Pointer
Register
Index
register

5
6
Base value ,not
the base adress

value of

7
value of
Basic Architecture of 8086 8086 architecture employs
Main jobs performed by BIU are- parallel processing—i.e., both the
units (BIU and EU) work
at the same time
(i) All external bus operations.
(ii) Instruction fetching,
(iii) Reading/writing of data/operands for
memory,
(iv) Inputting/outputting of data for
peripheral devices.
(v) Filling instruction queue.
(vi) Address generation.

1) BIU is the 8086’s interface to the outside world, i.e., all External bus operations
are done by BIU.

2) It does the job of instruction fetching, reading/writing of data/operands for


memory and also the inputting/outputting of data for peripheral devices.

3) It does the job of filling the instruction queue.

4)Does the job of address generation.


8
Basic Architecture of 8086
Main jobs performed by EU are-
(i) Decoding/execution of instructions.
(ii) It accepts instructions from output end
of instruction queue and
data from general purpose registers or
memory.
(iii) It generates operand addresses when
necessary, hands them over to BIU to perform
read or write cycle to memory or I/O devices.
(iv) EU tests status of flags in control register
and updates them when executing
instructions.
(v) EU waits for instructions from
instruction queue, when it is empty.

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