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Lecture #08, Microprocessor-Memory Segmentation-organization

The document provides an overview of the 8086 microprocessor's memory segmentation, detailing its ability to address 1MB of memory through 16 segments, each 64kB in size. It explains the roles of various segment registers (CS, DS, SS, ES) and the advantages of memory segmentation for multitasking environments. Additionally, it covers logical and physical addressing, as well as bus timing and data transfer rates associated with the 8086 microprocessor.

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Shohag Hawlader Shanto
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3 views

Lecture #08, Microprocessor-Memory Segmentation-organization

The document provides an overview of the 8086 microprocessor's memory segmentation, detailing its ability to address 1MB of memory through 16 segments, each 64kB in size. It explains the roles of various segment registers (CS, DS, SS, ES) and the advantages of memory segmentation for multitasking environments. Additionally, it covers logical and physical addressing, as well as bus timing and data transfer rates associated with the 8086 microprocessor.

Uploaded by

Shohag Hawlader Shanto
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EEE-3103: Microprocessor and Interfacing

Lecture #8: 8086 Microprocessor


Memory Segmentation of 8086

Dr. Sharnali Islam


Department of Electrical and Electronic Engineering
University of Dhaka
[email protected]

Slides used resources from:


Prof. Sazzad M.S. Imran, PhD, EEE DU
Web resources UNDERSTANDING 8085/8086 MICROPROCESSORS - Sen 221
Address Capability and Memory Map of 8086
8086 can address 220 = 1,048,576 bytes = 1MB of different 4 bytes

memory locations.

Whole memory space → 12 bytes

address = 00000H to FFFFFH.


blocks = 16 (CS- 4ta , DS- 4ta, SS- 4ta, ES-4ta)
each block = 64kB.
most significant hex digit increases by 1.

Reserved locations → future hardware and software needs.

Dedicated locations → specific system interrupts and 108 bytes


reset functions.

20 bytes
Memory Segmentation of 8086
1MB memory = 16 segments.
each segment = 64kB.
5 bytes

4 segments can be active at any given instant of time.


11 bytes

Currently active segments.


- Code segment,
- Stack segment,
- Data segment and
- Extra segment.

Corresponding segment registers are


- Code Segment Register (CS),
- Data Segment Register (DS),
- Stack Segment Register (SS) and
- Extra Segment Register (ES).
109 byttes

19 bytes

CS, DS, SS, ES = 16-bits wide


user accessible.
Memory Segmentation of 8086
Code segment → instruction codes of program.
Data segment → data, variables and constants.
Stack segment → interrupt and subroutine return addresses.
Extra segment → destination of data for string instructions.

Maximum size of active memory for 8086 = 64×4 = 256kB.


Program storage → 64kB in CS
Stack → 64kB in SS.
Data storage → 128kB in DS and ES.

Base address of segment = segment address


reside on 16-bit address memory.
00000H, 00010H or 00020H, etc.

What is the minimum size of a segment?


Memory Segmentation of 8086

• A memory segment can touch or even overlap if 64K bytes of


memory are not required for a segment.

• Suppose that an application program requires 1000H bytes of


memory for its code, 190H bytes of memory for its data, and
200H bytes of memory for its stack. This application does not
require an extra segment.

FIGURE 2–5 An application


program containing a code,
data, and stack segment
loaded into a DOS system
memory.
B. B. Brey: chapter 2
Memory Segmentation of 8086
Time share multitasking environment
Advantages of memory segmentation-
(i) Address bus = 20-bits,
Memory segmentation allows to work with 16-bits registers. Time share multitasking environment

(ii) More than one code, data, extra and stack segment can be used.
This makes code, data, stack and extra segment > 64kB long.
Time share multitasking environment

(iii) Time-shared multitasking environment → Time share multitasking environment

program moves over from one user’s program to another =


CPU reload four segment registers.
Segment registers = segment starting addresses assigned to current user’s program.

(iv) User’s program (code) and data can be stored separately.

(v) Logical address range = 0000H to FFFFH, can be loaded at any place in memory.
Logical Address, Base Segment
Address and Physical Address

SP, BP, SI, DI


Logical address = Offset address = Effective address = 16-bit → IP, BP, SP, BX, SI or DI. BX, IP
Base segment address = 16-bit → segment registers (CS, DS, ES, SS).
Physical address = Real address = Segment address × 10H + logical address
Logical Address, Base Segment
Address and Physical Address
8086 = 16-bit microprocessor,
Deals with 8-bit memory (=byte-width memory) →
(i) Microprocessor can work with both bytes and words.

(ii) 8086 can handle varied opcodes (1 to 6 bytes).


Memory Organization
(Higher bank) (Lower bank)
sen 227

Byte and Word Transfer by 8086


odd bank even bank odd bank even bank odd bank even bank

odd bank even bank odd bank even bank


(a) even-addressed byte
transfer,
(b) odd-addressed byte
transfer,
(c) even-addressed word
transfer,
(d) odd-addressed word
transfer.
(d)
Fig. 12.7 shows the Read and Write bus cycles for 8086 µP in the

Bus Timing of 8086


Minimum mode.
The bus cycle consists of 4T states. ALE signal stays high for T1 state
at the end of
which it goes low which is utilised by latches to latch the address.
Hence, during
T2 – T4 states, AD15 – AD0 lines act as data lines. The M/ IO , RD and
WR signals can
be combined to generate individual IOR, IOW and MEMR, MEMW
signals.
The Read and Write cycles show that data are made available during
T3 and T2 states
respectively.
Bus Timing of 8086
Bus Timing of 8086

8086 uses memory and I/O in periods = bus cycles.


1 bus cycle = 4 system-clocking periods.
1 clock period = 5MHz = 200ns → 1 bus cycle = 800ns.

Maximum data read or write rate = 1.25 million per second.

Internal queue → execution rate = 2.5 MIPS

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