Fusion Compiler™ User

Guide Version V-2023.12-SP3, May

2024
Copyright and Proprietary Information Notice
© 2024 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All
other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is
strictly prohibited.
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Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader’s responsibility to
determine the applicable regulations and to comply with them.
Disclaimer
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WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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at https://www.synopsys.com/company/legal/trademarks-brands.html.
All other product or company names may be trademarks of their respective owners.
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www.synopsys.com
Fusion Compiler™ User Guide
2
V-2023.12-SP3
Feedback

Contents
New in This Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Related Products, Publications, and Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.29 Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 30 Statement on Inclusivity and Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 31

1. Working With the Fusion Compiler Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Physical Synthesis Design Flow Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Formal Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
 Place and Route Design Flow Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Fusion Compiler Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Power Intent Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38 UPF Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39 Multiple-Patterning Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41 Mask Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Working With the 3DIC Compiler User Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Starting the CLI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Exiting the Fusion Compiler Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Entering fc_shell Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Interrupting or Terminating Command Processing . . . . . . . . . . . . . . . . . . . . . . . 47
Getting Information About Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Displaying Command Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Using Application Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Using Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Viewing Man Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Using Tcl Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Adding Changes to a Script With Checkpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Defining Checkpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Configuring Checkpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Defining Checkpoint Behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Associating Checkpoints and Checkpoint Behaviors . . . . . . . . . . . . . . . . . .56

3
Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents . . . . 66 Removing Multicore Configurations . . . . . . .

Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Running Tasks
in Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . .68 Running Commands in Parallel on Your
Local Host . . . . . . . . . . . . . . . . . . . . . 69 Running
Querying Checkpoints and Checkpoint Behaviors . .
Commands in the Background . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 60 Viewing Your
. . . . . . . . . . 69 Running Commands in Parallel . . . .
Checkpoint History . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
. . . . . . . . . 61 Using Setup Files . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Using
the Command Log File . . . . . . . . . . . . . . . . . . . . . . . 2. Preparing the Design . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 63 Enabling Multicore . . . . . . . . . . . . . . . . . . . . . . . . . 72 Defining the
Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Search Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 63 Configuring Multithreading . . . . . . . . . . . . . . . . . . . . . . . 73 Setting Up Libraries . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Configuring Distributed Processing . . . . . . . . . . . . . .
Working With Design Libraries . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 66 Reporting Multicore
. . . . . . . . . . . . . . . . . . . . . 74 Setting Up Reference
Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 75 Library Configuration . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . .76 Restricting
Library Cell Usage . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 77 Restricting the Target Libraries
Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Specifying Library Subset Restrictions . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . .80
Using Pin Access Checker Utility . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 81 Analyzing Libraries .
..........................................
. . . . . . . 83
Introduction to Redundancies, Outliers,
Equivalences, and Gaps in Library Cell Families . . .
..........................................
. . . . . . . . . . . 84 Identifying Redundancies, Outliers,
Equivalences, and Gaps in Library Cell Families . . .
..........................................
. . . . . . . . . . . 89 Comparing Libraries . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Reading the Design . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . .98 Reading RTL Files
in SystemVerilog, Verilog, or VHDL Format . . . . . . . .
. . . . .99 Reading Designs Using the -autoread
Option . . . . . . . . . . . . . . . . . . . . . . . . . 100 Reading
Designs Using the VCS Command-line Options . . . .
. . . . . . . . . . . . 101 Reading Verilog Gate-Level
Netlist Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Reading Mixed Gate-Level Netlists and RTL Files . .
. . . . . . . . . . . . . . . . . . . .102 Embedding Tcl
Commands in RTL Code . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 102

4
 Physical-Feedthrough Nets in Voltage Areas . . . . . .
. . . . . . . 127 Removing Voltage Areas . . . . . . . . . . .
Contents
Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Inserting
Multivoltage Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . .131 Inserting Level Shifters . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 Inserting
Mitigating Design Mismatches . . . . . . . . . . . . . . . . . . Isolation Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 103 Importing the . . . . . . . . . 131 Associating Power Strategies With
Floorplan Information . . . . . . . . . . . . . . . . . . . . . . . . . Existing Multivoltage Cells . . . . . . . . . 132
. . . . . . . . . . . 103 Reading DEF Files . . . . . . . . . . . . Controlling the Placement of Multivoltage Cells . . . .
. . . . . . . . . . . . . . . . . . . .132 Enabling Improved
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Buffering for Multivoltage Nets . . . . . . . . . . . . . . . . . .
Fixing Site Name Mismatches . . . . . . . . . . . . . . . . . .
. . . 132 Analyzing Multivoltage Information . . . . . . . .
. . . . . . . . . . . . . . . . 106 Validating DEF Files . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . .132 Specifying
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Timing Constraints and Settings . . . . . . . . . . . . . . . .
Physical Constraints Extracted From the DEF File . .
. . . . . . . . . . . . . . 133 Specifying Logical Design
. . . . . . . . . . . . . . . . 106 Using Automatic
Rule Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Floorplanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Specifying Clock Gating Constraints . . . . . . .
. . . . . .110 Creating Constraints for Auto . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Specifying
Floorplanning . . . . . . . . . . . . . . . . . . . . . . . 111 Physical Constraints for Placement and Legalization
Setting Up Multivoltage Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Defining Keepout Margins . . .
. . . . . . . . . . . . . . . . . . . . . . .113 Applying the . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Multivoltage Power Intent . . . . . . . . . . . . . . . . . . . . . Defining an Outer Keepout Margin . . . . . . . . . . . . . .
. . . . . . . . . 114 Loading and Applying UPF . . . . . . . . . . . . . . . . 138
Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Using Incomplete UPF Information . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 115 Specifying UPF Constraints
for Physical-Only Cells . . . . . . . . . . . . . . . . . 116
Saving UPF Information . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 116 Preparing the Power
Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 117 Creating Logical Power and Ground
Connections . . . . . . . . . . . . . . . . . . .117 Creating
Floating Logical Supply Nets . . . . . . . . . . . . . . . . . . .
. . . . . . . . .119 Defining Voltage Areas . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Merging
Voltage Area Shapes . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 121 Resolving Overlapping Voltage
Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Modifying the Stacking Order . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . .124 Defining Guard Bands . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Defining Gas Stations . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 126 Querying Voltage Areas . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Modifying Voltage Areas . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 127 Controlling
 Contents
Feedback

Defining an Inner Keepout Margin . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . 139 Defining Area-Based
Placement Blockages . . . . . . . . . . . . . . . . . . . . . . . .
. . .139 Defining a Hard Placement Blockage . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 140 Defining a Hard
Macro Placement Blockage . . . . . . . . . . . . . . . . . . . .
. . . 141 Defining a Soft Placement Blockage . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 141 Defining a Partial
Placement Blockage . . . . . . . . . . . . . . . . . . . . . . . . .
. . 142 Define a Blockage of a Predefined Category .
. . . . . . . . . . . . . . . . . . . . . .142 Defining Blockages
That Exclude Registers . . . . . . . . . . . . . . . . . . . . . . .
143 Defining Blockages That Exclude Relative
Placement Groups . . . . . . . . . 144 Defining
Blockages That Allow Relative Placement Cells Only
. . . . . . . . . 144 Defining Blockages That Allow
Buffers Only . . . . . . . . . . . . . . . . . . . . . . . 144
Querying Placement Blockages . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 145 Removing Placement
Blockages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
145 Defining Placement Bounds . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 145 Defining Move
Bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . .146 Defining Group Bounds . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 148 Querying
Placement Bounds . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 148 Removing Placement Bounds . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Defining
Placement Attractions . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . .149 Specifying Locations for
Unmapped Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . .
150 Defining Cell Spacing Constraints for
Legalization . . . . . . . . . . . . . . . . . . . . . 151
Reporting Cell Spacing Constraints . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 153 Removing Cell Spacing
Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Specifying Placement Settings . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 153 Performing
Placement With Inaccurate Constraints at Early
Stages . . . . . . . . 154 Generating Automatic Group
Bounds for Clock Gating Cells . . . . . . . . . . . . . .154
Controlling the Placement Density . . . . . . . . . . . . . . .
5
. . . . . . . . . . . . . . . . . . . 155 Controlling
Congestion-Driven Restructuring During Placement .
. . . . . . . . . . 156 Reducing Congestion . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Considering Wide Cell Density During Placement . . .
. . . . . . . . . . . . . . . . . . . 157 Considering the Effects
of Cell Pins During Placement . . . . . . . . . . . . . . . . . .
157 Considering the Congestion Effects Due to the
Nondefault Routing Rules of
Clock Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .158 Considering the Effects
of Clock Gating Cells of Sequential Arrays During
Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 158 Considering
Legalization Effects During Placement . . . . . . . . . . .
. . . . . . . . . .158 Considering DFT Connections
During Placement . . . . . . . . . . . . . . . . . . . . . . 159
Considering the Dynamic Power QoR During
Placement . . . . . . . . . . . . . . . . 159 Performing
IR-Drop-Aware Placement . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 159
Controlling IR-Drop-Aware Placement . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 160 Spreading Repeater Cells
During Placement . . . . . . . . . . . . . . . . . . . . . . . . .
.162

6
 Estimation Settings for the Preroute Optimization . . .
. . . 180 Enabling Global-Route-Layer-Based (GRLB)
Contents
Feedback Preroute Optimization . . . . .180 Enabling
Route-Driven Estimation (RDE) for Preroute
Optimization . . . . . 180 Specifying Automatic Via
Ladder Insertion Settings for Preroute
Specifying Legalization Settings . . . . . . . . . . . . . . . . Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 162 Minimizing Large . . . . . . . . . . . . . . . . . . . 181 Specifying Via Ladder
Displacements During Legalization . . . . . . . . . . . . . . Candidates for Library Pins . . . . . . . . . . . . . . . . . .
. . . . . 163 Optimizing Pin Access During 181 Assigning Nondefault Routing Rules to Critical
Legalization . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Nets . . . . . . . . . . . . . . . . . . . . 183 Enabling Area
Enabling Advanced PG Net Checks . . . . . . . . . . . . . Recovery in Regions of High Utilization . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .163 Enabling Advanced . . . . . . . 184 Enabling Advanced Logic Restructuring
Legalization Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 Setting Up
. . . 164 Setting Up for Variant-Aware Legalization . . for Power-Related Features . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 165 . . . . . . . . . . . . . 185 Annotating the Switching
Defining Equivalent Cell Groups . . . . . . . . . . . . . . . . Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 166 Enabling Variant-Aware 185 Using RTL Switching Activity With a
Legalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167Name-Mapping File . . . . . . . . . . . . . 186 Scaling the
Checking if Library Cells Are Legally Placeable . . . . Switching Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .167 Controlling the . . . . . . 187 Specifying Switching Probability for
Optimization of Cells, Nets, Pins, and Ports . . . . . . . Supply Nets . . . . . . . . . . . . . . . . . . . .188 Enabling
. . . . . . . . . . .169 Resolving Multiple References Leakage Power Optimization for the compile_fusion
With the Uniquify Process . . . . . . . . . . . . . . . .169 Command . . . . 189
Preserving Cells and Nets During Optimization . . . . .
. . . . . . . . . . . . . . . . . . . 170 Restricting Optimization
to Cell Sizing Only . . . . . . . . . . . . . . . . . . . . . . . . . .
.171 Preserving Networks During Optimization . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 172 Marking the Clock
Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . .172 Disabling Design Rule Checking (DRC) . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . .173 Preserving
Pin Names During Sizing . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 174 Preserving Ports of Existing
Hierarchies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Isolating Input and Output Ports . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .175 Fixing Multiple-Port
Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . .176 Controlling the Addition of New Cells to
Modules, Hierarchical Cells, and Voltage Areas . . . .
..........................................
. . . . . . . . . . . 178 Specifying a Cell Name Prefix for
Optimization . . . . . . . . . . . . . . . . . . . . . . . . 179
Specifying Settings for Preroute Optimization . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 179 Specifying Parasitic
 Contents
Feedback

Reporting Leakage Power . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . 190 Enabling Power
Optimization for the clock_opt Command . . . . . . . . .
. . . . . . 191 Performing Conventional
Leakage-Power Optimization . . . . . . . . . . . . . . .191
Performing Dynamic-Power Optimization . . . . . . . . .
. . . . . . . . . . . . . . . . 192 Performing Total-Power
Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
Improving Yield By Limiting the Percentage of
Low-Threshold-Voltage (LVT) Cells . . . . . . . . . . . . .
..........................................
. . 192 Updating Activity for Improved Power
Optimization . . . . . . . . . . . . . . . . . . . . . 193 Enabling
the Power Integrity Features . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 195
Setting Up for Dynamic Power Shaping . . . . . . . . . .
. . . . . . . . . . . . . . . . 197 Setting Up for
Voltage-Drop-Aware Placement . . . . . . . . . . . . . . . .
. . . . . 198 Manually Enabling Dynamic Power
Shaping and Voltage-Drop-Aware Placement . . . . .
..........................................
. . .198
Specifying the Routing Resources . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 199 Specifying the
Global Layer Constraints . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 199 Reporting Global Layer Constraints . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . .200 Removing
Global Layer Constraints . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 201 Specifying Net-Specific Layer
Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Removing Net-Specific Routing Layer Constraints . .
. . . . . . . . . . . . . . . . 202 Specifying Clock-Tree Layer
Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Enabling Level-Based Clock Nondefault Routing
Rule . . . . . . . . . . . . . . . . . . 205 Setting the
Preferred Routing Direction for Layers . . . . . . . . . . .
. . . . . . . . . . 206 Handling Design Data Using the
Early Data Check Manager . . . . . . . . . . . . . . . . 207
Applying Mega-Switch Command Settings . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .208 Applying Required
7 Settings for Advanced Technology Nodes . . . . . . . . .
. . . . 208 Applying Required Settings for High
Performance Cores . . . . . . . . . . . . . . . . 209
Applying Required Settings for Improving Specific
QoR Metrics . . . . . . . . . . . 210

3. Physical Synthesis . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 212 Performing
Unified Physical Synthesis . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 212 Using the compile_fusion
Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
213 Performing Prechecks . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . .215 Generating
Verification Checkpoints During Compilation . . . . . . .
. . . . . . . . . .217 Controlling Mapping and
Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 217 Ungrouping or Preserving Hierarchies During
Optimization . . . . . . . . . . . . . . .218 Controlling
Boundary Optimization . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 219 Controlling Datapath Optimization
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Datapath Extraction . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 222

8
 Performed . . . . . . . . . . . . . . . . . . . . . 250 Improving
the Banking Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
Feedback . . . . . . . . 252 Viewing Multibit Components in the
GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Mapping Combinational Multibit Cells . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 253 Running Concurrent
Datapath Implementation . . . . . . . . . . . . . . . . . . . . . .Clock and Data Optimization . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 224 Optimizing Datapaths . . . . . . . . . . . 255 Useful Skew . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Controlling
Controlling MUX Optimization . . . . . . . . . . . . . . . . . . Concurrent Clock and Data Optimization . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .226 Selecting and . . . . . . . . . . .256 Controlling Clock Latencies, Path
Multiplexing Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . Groups, and Boundary Paths . . . . . . . . . . . 256
. . . . . 227 Library Requirements . . . . . . . . . . . . . . . . Reducing Dynamic Voltage Drop . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 229 Controlling . . . . . . . . . . . . . . . . . . . 257 Specifying Optimization
Sequential Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . Targets at the Preroute Stage . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 230 Mapping Sequential Elements 257 Transferring to Back End . . . . . . . . . . . . . . . . . .
Exactly as Described in RTL . . . . . . . . . . . 232 . . . . . . . . . . . . . . . . . . . . . . . 258 Performing Test
Mapping of Scan Cells . . . . . . . . . . . . . . . . . . . . . . . . Insertion and Scan Synthesis . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . .232 Mapping of Synchronous . . . . . . . . . .258 Scan Synthesis Flow . . . . . . . . . . . .
Reset or Preset Registers . . . . . . . . . . . . . . . . .233 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Specifying Synchronous Input Types for Library Cell Minimizing Glitches on Asynchronous Set and Reset
Pins . . . . . . . . . . . . 235 Controlling Sequential Lines of Scan Registers . . . . . . . . . . . . . . . . . . . . . .
Output Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
.235 Preventing Connections to Register QN Pins . .
. . . . . . . . . . . . . . . . . . . . 236 Mapping of
Synchronous Enable Logic to a MUX . . . . . . . . . . . .
. . . . . . . 236 Identification of Shift Registers . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 237 Controlling
Register Replication . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 238 Controlling Register Merging . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Selectively Removing or Preserving Constant and
Unloaded Registers . . . . . 240 Reporting
Cross-Probing Information for Optimized Registers .
. . . . . . . . . . . .242 Controlling High-Fanout-Net
Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Performing Multibit Optimization . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 243 Performing
Integrated Multibit-Register Optimization . . . . . . . . . .
. . . . . . . . . .245 Creating a Multibit Register Bank
From Specific Single-Bit Registers . . . . . . . 247
Specifying Naming Styles for Multibit Registers . . . .
. . . . . . . . . . . . . . . . . . . .248 Reporting Multibit
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 250 Identifying Why Multibit Banking Is Not
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Feedback

Specifying Settings for Performance, Power, and

Area Improvement . . . . . . . . . . 261 Enabling
High-Effort Timing Mode . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 261 Enabling Enhanced Delay
Optimization to Improve Total Negative Slack . . . .
261 Enabling High-Effort Area Mode . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .261 Enabling the
Embedded Area Optimization Flow . . . . . . . . . . . . . .
. . . . . . . . .262
Performing Design Analysis . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 262 Reporting
Commands and Examples . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . .262 Measuring Quality of Results . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Comparing QoR Data . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 269
Setting Your Baseline Run . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 271 Changing the QoR Display
Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Sorting and Filtering the Data . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 274 Exploring the Detailed
Comparison Data . . . . . . . . . . . . . . . . . . . . . . . . .
.279
Reporting Logic Levels in Batch Mode . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .282 Querying Specific
Message IDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 284

4. Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 285 Introduction to
Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 286 Naming Convention for
Tool-Inserted Clock Gates . . . . . . . . . . . . . . . . . . . . .
288 Clock Gating in the Compile Log File . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 289 Clock-Gate Levels
and Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . .290 Clock-Gating Prerequisite Conditions . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
9
Clock-Gating Enable Condition . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .293 Clock-Gating Setup
Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 293 Setting Up Clock Gating . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 Setting the
Clock-Gating Style . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 294 Setting Clock-Gating Options . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Enabling or Disabling Clock Gating on Design
Objects . . . . . . . . . . . . . . . . . . 295 Clock-Gating
Enable Source Selection . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 296 User-Driven Enable Exclusion . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 Report
Clock Gating Options . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 299 Clock Gating Flows . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Inserting Clock Gates in Multivoltage Designs . . . . .
. . . . . . . . . . . . . . . . . . . .302 Inserting Clock Gates in
an RTL Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
302 Replacing Clock Gates . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 303 Controlling
Clock-Gate Latencies . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 303 Integrated Clock-Gate Latency
Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

10
 . . . . . . . . . . 332 Controlling the Selection of

Contents Self-Gating Objects . . . . . . . . . . . . . . . . . . . . 333

Feedback Reporting and Querying Self-Gating Cells . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 333 Special Naming and
Querying for DFT Wrapper Clock Gates . . . . . . . . . .
. . . . . . 334
User-Specified Clock-Gate Latency . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 305 Controlling the Number
of Clock-Gate Levels . . . . . . . . . . . . . . . . . . . . . . . . . 5. Clock Tree Synthesis . . . . . . . . . . . . . . . . . . . . . .
. . . 309 Clock-Gate Multilevel Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 Prerequisites for
. . . . . . . . . . . . . . . . . . . . . . . . . . 310 Clock-Gate Clock Tree Synthesis . . . . . . . . . . . . . . . . . . . . . . . . .
Collapsing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338 Defining the Clock Trees . . . . . . . . . .
. . . . . . . . . . 311 Controlling Tool-Inserted
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339
Clock-Gate Levels . . . . . . . . . . . . . . . . . . . . . . . . . .
Deriving the Clock Trees . . . . . . . . . . . . . . . . . . . . . .
311 Activity-Based Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 Identifying the Clock
. . . . . . . . . . . . . . . . . . . . . . . 312 Merging Clock Roots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 Identifying the Clock Endpoints . . . . . . . . . . . . .
. . . . . . . . . . .313 Setting Clock Gating . . . . . . . . . . . . . . . . . . . . 342
Defining Clock Tree Exceptions . . . . . . . . . . . . . . . . .
Transformations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 344 Defining Sink Pins . . . . .
. . . . . 314 Setting Routing Rules for Clock Gates . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315 Clock Defining Insertion Delay Requirements . . . . . . . . . . .
Gating and Multibit Registers . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 345 Defining Ignore Pins . . . . . .
. . . . . . . . . . . . . . . . . 316 Placement-Aware Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346
Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 316 Fanin-Based Sequential Clock Gating . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 Setting
Sequential Clock Gating Options . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 319 Reporting Sequential Clock
Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
320 Reporting Clock-Gating Results . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 321 Reporting
Clock-Gate Enable Signals . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 323 Clock Gate Efficiency
Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 323 Self-Gating Optimization . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Self-Gating Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 330 Library Requirements
for Self-Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. .331 Setting Up for Self-Gating . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 332 Setting
Self-Gating Options . . . . . . . . . . . . . . . . . . . . . . . . . .
 Contents
Feedback

Ensuring Clock Tree Exceptions are Valid . . . . . . . . .

. . . . . . . . . . . . . . . .347 Restricting Optimization on
the Clock Network . . . . . . . . . . . . . . . . . . . . . . . . 349
Setting Don’t Touch Settings . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 349 Setting Size-Only Settings .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Copying Clock Tree Exceptions Across Modes . . . . .
. . . . . . . . . . . . . . . . . . . 350 Deriving Clock Tree
Exceptions From Ideal Clock Latencies . . . . . . . . . . .
. . .351 Handling Endpoints With Balancing Conflicts
. . . . . . . . . . . . . . . . . . . . . . . . . 352 Verifying the
Clock Trees . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 354 Setting Clock Tree Design Rule
Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Specifying the Clock Tree Synthesis Settings . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 357 Specifying the Clock
Tree References . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 358 Deriving Clock Tree References for
Preexisting Gates . . . . . . . . . . . . . . . 358 Restricting
the Target Libraries Used . . . . . . . . . . . . . . . . . . . . . .
. . . . . . .359 Setting Skew and Latency Targets . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360 Enabling
Local Skew Optimization . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 360 Specifying the Primary Corner for
Clock Tree Synthesis . . . . . . . . . . . . . . . . . 361
Preventing Specific Clocks From Being Synthesized
. . . . . . . . . . . . . . . . . . . .361 Preserving Preexisting
Clock Trees . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 361 Enabling Clock Tree Power Reduction
Techniques . . . . . . . . . . . . . . . . . . . . . 361 Enabling
Wire Length Aware Power-Driven Relocation . . . . . .
. . . . . . . . . . . . 362 Reducing Electromigration . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Handling Inaccurate Constraints During Clock Tree
Synthesis . . . . . . . . . . . . 363 Defining Clock Cell
Spacing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . .363 Creating Skew Groups . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 364 Defining a
11 Name Prefix for Clock Cells . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 365 Using the Global Router During
Initial Clock Tree Synthesis . . . . . . . . . . . . . . 365
Specifying Constraints for Clock Nets . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 365 Constructing Faster
Clock Tree to Specific Endpoints . . . . . . . . . . . . . . . .
. . . 366 Improving Latency-Driven Clock-Gate
Splitting . . . . . . . . . . . . . . . . . . . . . . . . 368
Improving the Repeater Levels in Clock Tree . . . . . .
. . . . . . . . . . . . . . . . . . . 368 Reducing Signal
Integrity Effects on Clock Nets . . . . . . . . . . . . . . . . . .
. . . . . 368 Specifying Settings for Clock Latency
Adjustments . . . . . . . . . . . . . . . . . . . . . 369 Timing
Driven Sink Transition Target . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 370 Reporting the Clock Tree
Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
370 Implementing Clock Trees and Performing
Post-CTS Optimization . . . . . . . . . . . . 370
Performing Standalone Clock Trees Synthesis . . . . .
. . . . . . . . . . . . . . . . . . . 371
Synthesizing, Optimizing, and Routing Clock Trees
With the clock_opt Command . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

12
 . . . . . . .388 Running Interclock Delay Balancing . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 388 Performing
Contents
Feedback Global-Route-Based Optimization Using Machine
Learning Data . 389 Routing Clock Trees . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Inserting Via Ladders During Clock Tree Synthesis,
Considering Voltage Drop Information During Clock Optimization, and Clock Routing . . . . . . . . . . . . . . .
Tree Synthesis . . . . . 372 Using Nondefault Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rules for Critical Nets During Optimization . . . 373 391 Marking Clocks as Propagated After Clock Tree
Performing Concurrent Clock and Data Optimization Synthesis . . . . . . . . . . . . . . . 392 Performing
During the clock_opt Command . . . . . . . . . . . . . . . .
Postroute Clock Tree Optimization . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
. . . . . . . . . . 392 Performing Voltage Optimization . .
Controlling Multibit Optimization Performed During
the clock_opt Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 Performing Marking Clock Trees as Synthesized . . . . . . . . . . . .
Power or Area Recovery on the Clock Network . . . . . . . . . . . . . . . . . . . . . . . . 394 Removing Clock Trees
. . . . . . . 374 Performing IR-Drop-Aware Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
During the clock_opt Command . . 375 . 394
Controlling Concurrent Clock and Data Optimization Implementing Multisource Clock Trees . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .376 Limiting the Latency
. . . . . . . . . . . . . . . . . . . . . . .396 Introduction to
Adjustment Values . . . . . . . . . . . . . . . . . . . . . . . . . .
377 Excluding Boundary Paths . . . . . . . . . . . . . . . . . Multisource Clock Trees Structures . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 377 Excluding Specific . . . . . . . 397 Implementing a Regular Multisource
Path Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Clock Tree . . . . . . . . . . . . . . . . . . . . . . . 399
.378 Excluding Specific Scenarios . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 378 Excluding Specific
Sinks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 378 Controlling Timing Optimization Effort . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 379 Controlling Hold Time
Optimization Effort . . . . . . . . . . . . . . . . . . . . . . . . .
379 Controlling the Adjustment of I/O Clock
Latencies . . . . . . . . . . . . . . . . . . .379 Performing
Dynamic-Voltage-Drop-Driven Concurrent Clock and
Data
Optimization During the route_opt Command . . . . . .
. . . . . . . . . . . . . . . . 380 Specifying Optimization
Targets at the Preroute Stage . . . . . . . . . . . . . . . 380
Specifying Optimization Targets at the Postroute
Stage . . . . . . . . . . . . . . 381 Enabling Buffer
Removal at the Postroute Stage . . . . . . . . . . . . . . . .
. . . 383 Reporting Concurrent Clock and Data
Timing . . . . . . . . . . . . . . . . . . . . . . 383 Scaling CCD
Offsets to New Scenarios for Reporting Timing . . . . .
. . . . . 385 Skewing Latch and Discrete Clock Gates .
. . . . . . . . . . . . . . . . . . . . . . . . 385
Splitting Clock Cells . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 385 Balancing Skew
Between Different Clock Trees . . . . . . . . . . . . . . . . .
. . . . . . 386 Defining the Interclock Delay Balancing
Constraints . . . . . . . . . . . . . . . . . 386 Generating
Interclock Delay Balancing Constraints Automatically
 Contents
Feedback

Implementing a Regular Multisource Clock Tree

Using Integrated Tap Assignment . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Implementing a Regular Multisource Clock Tree With
an H-Tree-Only Global Clock Tree Structure . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402
Implementing MSCTS Multiple H-Tree . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .403 Implementing Power
Aware Flexible H-Tree . . . . . . . . . . . . . . . . . . . . . . . .
. . 404 Implementing a Structural Multisource Clock
Tree . . . . . . . . . . . . . . . . . . . . . .405 Implementing a
Structural Multisource Clock Tree Using Integrated
Subtree Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . .406 Improving the
Correlation Between the SMSCTS and CCD . . . . . .
. . . . . . . . 409 Inserting Clock Drivers . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 Inserting
Clock Drivers for Designs With Multiple Levels of
Physical
Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . .412 Synthesizing the Global
Clock Trees . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
413 Inserting Clock Drivers for Designs With Multiple
Levels of Physical
Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . .415 Creating Clock Straps . . . .
.......................................
.415 Routing to Clock Straps . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 419 Analyzing the
Clock Mesh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 423 Performing Automated Tap Insertion
and H-Tree Synthesis . . . . . . . . . . . . . . 425
Specifying Tap Assignment Options and Settings . . .
. . . . . . . . . . . . . . . . . . . 427 Building the Local Clock
Subtree Structures . . . . . . . . . . . . . . . . . . . . . . . . . .
429
Analyzing the Clock Tree Results . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .432 Generating Clock
Tree QoR Reports . . . . . . . . . . . . . . . . . . . . . . . . . . .
13 . . . . . 432 Reporting Clock Tree Power . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 435 Creating
Collections of Clock Network Pins . . . . . . . . . . . . . . .
. . . . . . . . . . . .436 Analyzing Clock Timing . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
Analyzing Clock Trees in the GUI . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 437

6. Routing and Postroute Optimization . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . .438 Introduction to
Zroute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 439 Basic Zroute Flow . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Prerequisites for Routing . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .442 Defining Vias . . . . .
..........................................
. . . . . . . 443
Reading Via Definitions from a LEF File . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 444 Creating a Via Definition
.........................................
.444 Defining Simple Vias . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 444 Defining Custom Vias .
.......................................
.445

14
 the Nonpreferred Direction . . . . . 476 Using Routing
Guides to Control the Routing Density . . . . . . . . . . .
Contents
Feedback . . . . .477 Using Routing Guides to Prioritize Routing
Regions . . . . . . . . . . . . . . . . . 477 Using Routing
Guides to Encourage River Routing . . . . . . . . . . . . .
. . . . .478 Querying Routing Guides . . . . . . . . . . . . .
Inserting Via Ladders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .479 Removing
. . . . . . . . . . . . . . . . . . . . . . 446 Defining Via Ladder Routing Guides . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 Deriving Routing Guides . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .479 Deriving
. . . 447 Generating Via Ladder Rules for
Pin Access Routing Guides . . . . . . . . . . . . . . . . . . . .
Electromigration Via Ladders . . . . . . . . . . . .449
. . . . . . . . . 480 Deriving Metal Cut Routing Guides .
Generating Via Ladder Rules for Performance Via
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 Controlling
Ladders . . . . . . . . . . . . . . 451
Routing Around the Block Boundary . . . . . . . . . . . . .
Via Ladder Rule Files . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 481 Inserting Metal Shapes in the
. . . . . . . . . . . . . . . . .453 Via Ladder Association File
Preferred Direction . . . . . . . . . . . . . . . . . . . 482
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
Inserting Routing Guides Along the
Constraint-Based Via Ladder Insertion . . . . . . . . . . .
Nonpreferred-Direction Edges . . . . . .486 Inserting
. . . . . . . . . . . . . . . . . . . .454 Defining Via Ladder
Routing Blockages Along the Boundary Edges . . . . .
Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . .488 Removing Perimeter Constraint
. . .455 Defining Global Via Ladder Constraints . . . . .
Objects . . . . . . . . . . . . . . . . . . . . . . . . . . 490
. . . . . . . . . . . . . . . . . . . . . .455 Defining
Routing Nets Within a Specific Region . . . . . . . . . . .
Instance-Specific Via Ladder Constraints . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 490 Defining Routing
. . . . . . . . . 456 Inserting Via Ladders . . . . . . . . . . . .
Corridors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
. . .491
Protecting Via Ladders . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 459 Verifying Via Ladders .
..........................................
. 460 Updating Via Ladders . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 461 Manual Via
Ladder Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . .463 Querying Via Ladders . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .464
Removing Via Ladders . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 464 Checking Routability . .
..........................................
. . . . 464 Routing Constraints . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .469 Defining
Routing Blockages . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 471 Reserving Space for Top-Level
Routing . . . . . . . . . . . . . . . . . . . . . . . . . . 473
Querying Routing Blockages . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 473 Removing Routing
Blockages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 473 Defining Routing Guides . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . .474 Using Routing
Guides to Control the Routing Direction . . . . . . . . . .
. . . . .475 Using Routing Guides to Limit Edges in
 Contents
Feedback

Assigning Nets to a Routing Corridor . . . . . . . . . . . .

. . . . . . . . . . . . . . . . 492 Verifying Routing Corridors .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
Modifying Routing Corridors . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . .493 Reporting Routing
Corridors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 494 Removing Routing Corridors . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 494
Using Nondefault Routing Rules . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 494 Defining Nondefault
Routing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
495 Assigning Nondefault Routing Rules to Nets . . .
. . . . . . . . . . . . . . . . . . . .506
Controlling Off-Grid Routing . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 510 Preventing Off-Grid
Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.510 Discouraging Off-Grid Routing for Vias . . . . . . .
. . . . . . . . . . . . . . . . . . . . 511
Routing Must-Join Pins . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .511 Controlling Pin
Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 513 Controlling Pin Tapering . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
Specifying the Tapering Method . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . .517 Controlling the Tapering
Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .518
Controlling Via Ladder Connections . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .518 Setting the Rerouting
Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 519 Routing Application Options . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 Routing
Clock Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 520 Routing Critical Nets . . . . . .
..........................................
521 Routing Secondary Power and Ground Pins . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 522 Verifying the
Secondary Power and Ground Pin Attributes . . . . . .
. . . . . . . . . 522 Setting the Routing Constraints . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 Routing
15 the Secondary Power and Ground Pins . . . . . . . . . .
. . . . . . . . . . . . . 524 Routing Signal Nets . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
Global Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 526 Global Routing During
Design Planning . . . . . . . . . . . . . . . . . . . . . . . . . .
529 Timing-Driven Global Routing . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 529 Crosstalk-Driven Global
Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
Incremental Global Routing . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 531 Track Assignment . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
Detail Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 533 Routing Signal Nets by
Using Automatic Routing . . . . . . . . . . . . . . . . . . . . . .
537 Shielding Nets . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 539 Defining the
Shielding Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 540 Performing Preroute Shielding . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 Soft
Shielding Rules During Signal Routing . . . . . . . . . . .
. . . . . . . . . . . . . . . .544 Performing Postroute
Shielding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 545

16
 Rule Checking in an External Tool . . . . . . . . . . . . . . .

Contents . . . 573 Performing Layout-Versus-Schematic

Feedback Checking . . . . . . . . . . . . . . . . . . . . . . . 573
Reporting the Routing Results . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 576 Reporting the Wire
Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shielding Example . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 576 Using the DRC Query Commands . . . . . . .
. . . . . . . . . . . . . . . . 545 Performing Incremental
. . . . . . . . . . . . . . . . . . . . . . . . . . . 577 Saving Route
Shielding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.546 Reporting Shielding Information . . . . . . . . . . . .
. . . . . . . . . . . 578 Deriving Mask Colors . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 546
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
Querying Shield Shapes . . . . . . . . . . . . . . . . . . . . . .
Inserting and Removing Cut Metal Shapes . . . . . . . .
. . . . . . . . . . . . . . . . 546 Reporting Shielding
. . . . . . . . . . . . . . . . . . . . . . 579
Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
547 Performing Shielding Checks . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 548 Performing 7. Chip Finishing and Design for Manufacturing .
Postroute Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 Inserting Tap
. . . . . . . . . . . . . . 548 Performing Postroute Logic Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .581 Using the create_tap_cells
549 Performing Postroute Optimization Using the Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
hyper_route_opt Command . . . 551 Fixing DRC 582 Using the create_cell_array Command . . . . . . .
Violations Caused by Pin Access Issues . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 586
. . . . . . . . . 552 Analyzing and Fixing Signal
Electromigration Violations . . . . . . . . . . . . . . . . . . . .
554 Loading the Signal Electromigration Constraints
. . . . . . . . . . . . . . . . . . . . . . . 555 Analyzing Signal
Electromigration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 555 Fixing Signal Electromigration Violations .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 Performing
ECO Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 558 Routing Nets in the GUI . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
Modifying Routed Nets . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 561 Cleaning Up Routed
Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 563 Analyzing the Routing Results . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
Generating a Congestion Report . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 564 Generating a
Congestion Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 566 Performing Design Rule Checking
Using Zroute . . . . . . . . . . . . . . . . . . . . . . . 569
Performing Signoff Design Rule Checking . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 572 Performing Design
 Contents
Feedback

Inserting Exterior Tap Walls . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . 588 Inserting Interior Tap
Walls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . .589 Inserting Tap Meshes . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 591 Inserting Dense
Tap Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 592
Performing Boundary Cell Insertion . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 593 Specifying the
Boundary Cell Insertion Requirements . . . . . . . . . . .
. . . . . . . .593 Specifying the Library Cells for
Boundary Cell Insertion . . . . . . . . . . . . . . 594
Specifying Boundary Cell Placement Rules . . . . . . .
. . . . . . . . . . . . . . . . .596 Specifying the Naming
Convention for Boundary Cells . . . . . . . . . . . . . . .
597 Creating Routing Guides During Boundary Cell
Insertion . . . . . . . . . . . . . 597 Creating Placement
Blockages During Boundary Cell Insertion . . . . . . . .
598 Reporting the Boundary Cell Insertion
Requirements . . . . . . . . . . . . . . . . . . . 598
Removing Boundary Cell Insertion Requirements . . .
. . . . . . . . . . . . . . . . . . . 599 Inserting Boundary Cells
.........................................
.599 Verifying the Boundary Cell Placement . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 599 Finding and Fixing
Antenna Violations . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 600 Defining Antenna Rules . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
Calculating the Maximum Antenna Ratio . . . . . . . . . .
. . . . . . . . . . . . . . . .601 Calculating the Antenna
Ratio for a Pin . . . . . . . . . . . . . . . . . . . . . . . . . . .612
Specifying Antenna Properties . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 616 Analyzing and Fixing
Antenna Violations . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 617 Inserting Diodes During Detail Routing . . . . . .
. . . . . . . . . . . . . . . . . . . . . 619 Inserting Diodes After
Detail Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.620
Inserting Redundant Vias . . . . . . . . . . . . . . . . . . . . .
17 . . . . . . . . . . . . . . . . . . . . . . . 621 Inserting
Redundant Vias on Clock Nets . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 622 Inserting Redundant Vias on
Signal Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
Viewing the Default Via Mapping Table . . . . . . . . . . .
. . . . . . . . . . . . . . . . 623 Defining a Customized Via
Mapping Table . . . . . . . . . . . . . . . . . . . . . . . . 625
Postroute Redundant Via Insertion . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 626 Concurrent Soft-Rule-Based
Redundant Via Insertion . . . . . . . . . . . . . . . .627
Near 100 Percent Redundant Via Insertion . . . . . . . .
. . . . . . . . . . . . . . . . 629 Preserving Timing During
Redundant Via Insertion . . . . . . . . . . . . . . . . . . 630
Reporting Redundant Via Rates . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 630
Optimizing Wire Length and Via Count . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 632 Reducing Critical
Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . .632 Performing Wire Spreading . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Performing Wire Widening . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 634 Inserting
Metal-Insulator-Metal Capacitors . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 635 Inserting Filler Cells . . . . . . .
.........................................
.636

18
 . . . . . . . . . . 672 Viewing the Violations in an ICV
Heat Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
Contents
Feedback Configuring an ICV Heat Map . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 676 Highlighting Violations From
the Error Browser Onto an ICV Heat Map . . 682
Automatically Fixing Signoff DRC Violations . . . . . . .
Standard Filler Cell Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 Creating an Autofix
. . . . . . . . . . . . . . . . . . . 637 Controlling Standard Configuration File . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Filler Cell Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . 684 Setting Options for Signoff DRC Fixing . . . . . . .
639 Checking for Filler Cell DRC Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 Running the
. . . . . . . . . . . . . . . . . . . . 642 Fixing Remaining signoff_fix_drc Command . . . . . . . . . . . . . . . . . . . . .
Mask Design Rule Violations . . . . . . . . . . . . . . . . . . . . . . . . . 687 Automatically Fixing Double-Patterning
. 643 Abutting Standard Cells With Specific Filler Odd-Cycle Violations . . . . . . . . . .691 Summary
Cells . . . . . . . . . . . . . . . . . . . 655 Report for Automatic Design Rule Fixing . . . . . . . . . .
Threshold-Voltage-Based Filler Cell Insertion . . . . . . . . . . . . . 691 Checking Signoff Design Rules
. . . . . . . . . . . . . . . . . . . 657 Controlling Interactively in the GUI . . . . . . . . . . . . . . . . . 693
Threshold-Voltage-Based Filler Cell Insertion . . . . . . Displaying Objects for Design Rule Checking . . . . . .
. . . . . . . 658 Removing the Threshold-Voltage Filler . . . . . . . . . . . . . . . . 694 DRC Toolbar . . . . . . . . . . . .
Cell Information . . . . . . . . . . . . . . 659 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .695
Removing Filler Cells . . . . . . . . . . . . . . . . . . . . . . . . . Setting Options for Interactive Design Rule Checking
. . . . . . . . . . . . . . . . . . . 659 Inserting Metal Fill . . . . .. . . . . . . . . . . . . . . . 697
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Improving Instance Voltage Drop by Augmenting the
. . .659 Power Grid . . . . . . . . . . . . . 699 Standard Power
Grid Augmentation . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . .700
8. IC Validator In-Design . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 660 Preparing to Run
IC Validator In-Design Commands . . . . . . . . . . . . . .
. . . . . . . . . 661 Setting Up the IC Validator
Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
661 Enabling IC Validator Multicore Processing . . . .
. . . . . . . . . . . . . . . . . . . . . . . 661 Running
IC Validator on Specific Hosts . . . . . . . . . . . . . . . . . .
. . . . . . . . . 662 Running IC Validator Using a Job
Scheduler . . . . . . . . . . . . . . . . . . . . . . .663 Running
IC Validator Using Hybrid Multicore Processing . . . .
. . . . . . . . . 664 Defining the Layer Mapping for
IC Validator In-Design Commands . . . . . . . . . 664
Performing Signoff Design Rule Checking . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 665 Running the
signoff_check_drc Command . . . . . . . . . . . . . . . . . .
. . . . . . . . . .665 Setting Options for Signoff Design
Rule Checking . . . . . . . . . . . . . . . . . . 667 Reading
Blocks for Signoff Design Rule Checking . . . . . . . . .
. . . . . . . . . 669 Signoff Design Rule Checking . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 Signoff
DRC Results Files . . . . . . . . . . . . . . . . . . . . . . . . . . .
 Contents
Feedback

Setting Options for Power Grid Augmentation . . . . . .

. . . . . . . . . . . . . . . .702 Timing-Driven Power Grid
Augmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
703 Guided Power Grid Augmentation . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 705 Removing PG
Augmentation Shapes . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . .706 ECO-Aware Removal of PG
Augmentation Shapes . . . . . . . . . . . . . . . . . . . . .706
Inserting Metal Fill With IC Validator In-Design . . . . .
. . . . . . . . . . . . . . . . . . . . . . 707 Setting Options for
Signoff Metal Fill Insertion . . . . . . . . . . . . . . . . . . . . .
. . . . 708 Performing Metal Fill Insertion . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 711
Pattern-Based Metal Fill Insertion . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 711 Track-Based Metal Fill
Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.716 Using an IC Validator Parameter File . . . . . . . .
. . . . . . . . . . . . . . . . . . . . .719 Typical Critical
Dimension Metal Fill Insertion . . . . . . . . . . . . . . . . . .
. . . . 724 Timing-Driven Metal Fill Insertion . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . .724 Incremental Metal
Fill Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 729 Foundry Fill and Track Fill Combined for
Different Flows of Foundry . . . . 731
Signoff Metal Fill Result Files . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .732 Querying Metal Fill . . . .
..........................................
732 Viewing Metal Fill in the GUI . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 733 Reporting the Metal
Density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 734
Viewing Density Heat Maps in the GUI . . . . . . . . . . .
. . . . . . . . . . . . . . . . 737 Removing Metal Fill . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
Removing Metal Fill With the IC Validator Tool . . . . .
. . . . . . . . . . . . . . . . 740 ECO-Aware Removal of
Track Based Metal Fill Shapes . . . . . . . . . . . . . . 741
Modifying Metal Fill . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .741 Performing Real Metal
19 Fill Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.741 Automatically Fixing Isolated Vias . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 742 Setting Options
for Fixing Isolated Vias . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 742 Running the signoff_fix_isolated_via
Command . . . . . . . . . . . . . . . . . . . . . . . .743
Checking for Isolated Vias . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 743 Checking and Fixing
Isolated Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.744

9. Routing Using Custom Router . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . .746 Using Custom
Router in the Fusion Compiler Tool . . . . . . . . . . . . . .
. . . . . . . . . . .747 Before Using Custom Router . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
Defining Routing Constraints . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 749
Defining the Bus Routing Style . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 750 Creating Differential
Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 752 Inserting Shields on the Nets . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 753

20
 Physical Datapath With Relative Placement . . . . . . .

Contents . . . . . . . . . . .781 Benefits of Relative Placement . . .

Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
Relative Placement Flow . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .783 Creating Relative
Placement Groups . . . . . . . . . . . . . . . . . . . . . . . . . . .
Defining the Net Priority . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 783 Adding Objects to a Group . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 755 Defining Minimum Wire
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding Leaf Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.755 Defining Matching Wire Lengths . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 785 Specifying Orientations
. . . . . . . . . . . . . . . . . . . . . . . 758
for Leaf Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
Managing Constraint Groups . . . . . . . . . . . . . . . . . . .
Adding Hard Macro Cells . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 763 Using Custom
. . . . . . . . . . . . . . . . . . . 786 Adding Relative
Routing Application Options . . . . . . . . . . . . . . . . . . .
Placement Groups . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 764 Bus Routing Options . . . . . . . . . . .
. . . . . . 786 Creating Hierarchical Relative
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .766
Placement Groups . . . . . . . . . . . . . . . . . . .787 Using
Corner Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hierarchical Relative Placement for Straddling . . . . .
. . . . . . . . . . . . . . . . 766 Intra-shield Placement . . . .
. . . . . . . . . . . 788 Using Hierarchical Relative
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
Placement for Compression . . . . . . . . . . . . . .790
Pin-Trunk Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding Blockages . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 768 Trunk Splitting . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 791 Adding Cells Within a
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .768
Predefined Relative Placement Area . . . . . . . . . . . . .
Tapoffs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 792
. . . . . . . . . . . . . . . . 769 Track Adherence Options . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
Differential-Pair Options . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 770 Shielding Options . . . . .
..........................................
770 Single-Loop Matching . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 771 Balance Mode
Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 772 Routing With the Custom Router . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
Shielding the Nets . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .774 Checking the
Routing Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . .775 Using a Hybrid Routing Flow . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
Using a DDR Routing Flow . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .776

10. Physical Datapath With Relative Placement . .

. . . . . . . . . . . . . . . . . . . . . . . . . .781 Introduction to
 Contents
Feedback

Specifying Options for Relative Placement Groups . .

. . . . . . . . . . . . . . . . . . . . . . 792 Anchoring Relative
Placement Groups . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . .793 Aligning Leaf Cells Within a Column . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 796
Aligning by the Left Edges . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . .796 Aligning by the Right Edges .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
Aligning by Pin Location . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . .797 Overriding the Alignment
When Adding Objects . . . . . . . . . . . . . . . . . . . . 799
Controlling the Tiling Within Relative Placement
Groups . . . . . . . . . . . . . . . . . 800 Applying
Compression to Groups With Straddling Leaf Cells .
. . . . . . . . . 801 Specifying the Orientation of Relative
Placement Groups . . . . . . . . . . . . . . . . 802
Specifying a Keepout Margin . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 804 Handling Fixed Cells
During Relative Placement . . . . . . . . . . . . . . . . . . . .
. . .804 Allowing Nonrelative Placement Cells . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 805 Controlling the
Optimization of Relative Placement Cells . . . . . . . . .
. . . . . . . 805 Controlling Movement When Legalizing
Relative Placement Groups . . . . . . . 806 Handling
Tap Columns and Relative Placement Group
Overlaps . . . . . . . . . . 806 Changing the Structures
of Relative Placement Groups . . . . . . . . . . . . . . . . . .
. . 807 Generating Relative Placement Groups for
Clock Sinks . . . . . . . . . . . . . . . . . . . . 808
Performing Placement and Legalization of Relative
Placement Groups . . . . . . . . .809 Relative
Placement in a Design Containing Obstructions . . . .
. . . . . . . . . . . . 809 Legalizing Relative Placement
Groups in a Placed Design . . . . . . . . . . . . . . . 810
Creating New Relative Placement Groups in a
Placed Design . . . . . . . . . . . . 811 Analyzing
Relative Placement Groups . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 812 Checking Relative Placement
21
Groups Before Placement . . . . . . . . . . . . . . . . 812
Analyzing the Placeability of a Relative Placement
Group . . . . . . . . . . . . . . . .813 Reporting Relative
Placement Constraint Violations . . . . . . . . . . . . . . . .
. . . . 813 Querying Relative Placement Groups . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 814 Analyzing
Relative Placement in the GUI . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 814 Saving Relative Placement
Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
815 Summary of Relative Placement Commands . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 815

11. Hierarchical Implementation . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . 817 Performing
Hierarchical Synthesis Using Abstracts . . . . . . . . . . .
. . . . . . . . . . . . . 818 Partitioning and Planning the
Full Chip Design . . . . . . . . . . . . . . . . . . . . . . . . 818
Hierarchical Synthesis Flow When Floorplans are
not Available . . . . . . . . 819 Hierarchical Synthesis
Flow When Floorplans are Available . . . . . . . . . . .
821 Synthesizing a Subblock . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 822

22
 . . . . . . . . . . . . . . .842 Checking Designs With

Contents Abstracts for Top-Level-Closure Issues . . . . . . . . . . .

Feedback . . . 843 Handling Design Data Using the Early Data
Check Manager . . . . . . . . . . . . . 846 Prerequisites
for Handling Early Design Data . . . . . . . . . . . . . . . . .
. . . . . . . . 846 Early Data Checks, Policies, and
Synthesizing the Top-Level . . . . . . . . . . . . . . . . . . . .
Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . 847
. . . . . . . . . . . . . . . . . . . .823 Performing Hierarchical
Setting the Policy for Early Data Checks . . . . . . . . . .
Synthesis Using ETMs . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 850 Reporting Early Data
. . . 824 Running the Hierarchical Synthesis
Check Records . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Feasibility Analysis Flow Using ETMs . . . 825
. . 851 Generating a Report of Early Data Check
Running the Hierarchical Synthesis Flow Using
Records . . . . . . . . . . . . . . . . . . . . . 853 Performing
ETMs . . . . . . . . . . . . . . . . . . 827 Example Script of
Top-Level Closure With Abstract Views . . . . . . . . . . .
Hierarchical Synthesis Using ETMs . . . . . . . . . . . . . .
. . . . . . . . . . . . . 854 Creating ETMs and ETM Cell
. . . . 829 Performing Prechecks for Hierarchical
Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synthesis Flows . . . . . . . . . . . . . . . . . . . . 829
855 Creating ETMs and ETM Cell Libraries in the
Providing Block-Level Test Models . . . . . . . . . . . . . .
Fusion Compiler Tool . . . . . . . . 856 Creating ETMs
. . . . . . . . . . . . . . . . . . . . . . . 829 Specifying
in the PrimeTime Tool . . . . . . . . . . . . . . . . . . . . . . . .
Block-Level Power Intent . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 856 Creating ETM Cell Libraries in the
. . . . . . . . . . . . . .830 Overview of Abstract Views . . .
Library Manager Tool . . . . . . . . . . . . . . . . 858
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
Linking to ETMs at the Top Level . . . . . . . . . . . . . . . .
Creating Abstract Views . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . .859
. . . . . . . . . . . . . . . . . . . . . . . 833 Creating Abstracts
With Power Information . . . . . . . . . . . . . . . . . . . . . . .
. . . . 834 Creating Abstracts for Signal
Electromigration Analysis . . . . . . . . . . . . . . . . . 835
Handling Multiple Levels of Physical Hierarchy . . . . .
. . . . . . . . . . . . . . . . . . . 835 Creating Abstracts for
Minimum Pulse Width Analysis . . . . . . . . . . . . . . . . .
. 836 Reporting Abstract Inclusion Reasons . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 836 Making
Changes to a Block After Creating an Abstract . . . . .
. . . . . . . . . . . . . . . . 837 Creating a Frame View . . . .
..........................................
838 Linking to Abstract Views at the Top-Level . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . .838 Changing the
Block From Abstract to Design View . . . . . . . . . . . . .
. . . . . . . . . . . 839 Linking to Subblocks With Multiple
Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
Specifying the Editability of Blocks From the
Top-Level . . . . . . . . . . . . . . . . . . . . . 841 Preparing
for Top-Level Closure With Abstracts . . . . . . . . . . . .
 Contents
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Performing Top-Level Closure With ETMs . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . 860 Transparent
Hierarchy Optimization . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 860 Accessing Libraries . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .862
Setting up Transparent Hierarchy Optimization . . . . .
. . . . . . . . . . . . . . . . . . . 863 Performing THO During
compile_fusion final_place Stage . . . . . . . . . . . . . . .
863 Performing THO During compile_fusion
final_opto Stage . . . . . . . . . . . . . . . . 865
Rebudgeting After compile_fusion . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 865 Performing THO During
route_opt or hyper_route_opt . . . . . . . . . . . . . . . . . .
865

12. RedHawk and RedHawk-SC Fusion . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . 867 Running Rail
Analysis Using RedHawk-SC Fusion . . . . . . . . . . . . .
. . . . . . . . . . . 868 An Overview for RedHawk Fusion
and RedHawk-SC Fusion . . . . . . . . . . . . . . . . 870
RedHawk Fusion and RedHawk-SC Fusion Data
Flow . . . . . . . . . . . . . . . . . . 872
RedHawk/RedHawk-SC Fusion Analysis Flow . . . . .
. . . . . . . . . . . . . . . . . . . .873 Running RedHawk
Fusion Commands in the Background . . . . . . . . . . . .
. . . 874
Setting Up the Executables . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .875 Specifying
RedHawk and RedHawk-SC Working Directories . . .
. . . . . . . . . . . . . .875 Preparing Design and Input
Data for Rail Analysis . . . . . . . . . . . . . . . . . . . . . . . .
877
Generating Rail Analysis Script Files . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 880 Supporting
RedHawk-SC Customized Python Script Files . . . . .
23
. . . . . . . . . . 881 Specifying Ideal Voltage Sources
as Taps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885
Validating the Taps and Finding Invalid Taps . . . . . . .
. . . . . . . . . . . . . . . . . . . 888 Tap Attributes . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
Finding Invalid Taps . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 889 Finding Substitute Locations
for Invalid Taps . . . . . . . . . . . . . . . . . . . . . . 889
Removing Taps . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 890 Missing Via and
Unconnected Pin Checking . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 890 Setting Checking Options . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
Checking Missing Vias and Unconnected Pins . . . . .
. . . . . . . . . . . . . . . . . . . 892 Viewing Error Data . . . .
..........................................
894 Fixing Missing Vias . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .895 Running Rail
Analysis with Multiple Rail Scenarios . . . . . . . . . . . .
. . . . . . . . . . . . 896 Specifying a Design Scenario for
Rail Analysis . . . . . . . . . . . . . . . . . . . . . . . . 897
Creating and Specifying Rail Scenarios for Rail
Analysis . . . . . . . . . . . . . . . . 897 Performing Voltage
Drop Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 900 Viewing Voltage Drop Analysis Results .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902

24
 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940

Contents Reporting Hotspots . . . . . . . . . . . . . . . . . . . . . . . . . .

Feedback . . . . . . . . . . . . . . . . . . . . 941 Removing Hotspots . .
..........................................
. .943 Voltage Hotspot Analysis Examples . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . .944 Querying
Performing PG Electromigration Analysis . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .903 Viewing PG Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electromigration Analysis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
. . . . . . . . . 904 Displaying the PG Electromigration
Map . . . . . . . . . . . . . . . . . . . . . . . . . . 904 Checking
13. ECO Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PG Electromigration Violations . . . . . . . . . . . . . . . . .
. . . . . . . . 905 . . . . . . . . . . . . . . . . . . . . . . . . . . 948 Generic ECO

Performing Minimum Path Resistance Analysis . . . . Flow for Timing or Functional Changes . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 908 Viewing Minimum . . . . . . . . . . . 949 Freeze Silicon ECO Flow . . . . . . .
Path Resistance Analysis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
. . . . .909 Tracing Minimum Path Resistance Using Signoff ECO Flow . . . . . . . . . . . . . . . . . . . . . . . . . . .
the Mouse Tool . . . . . . . . . . . . . . . . 911
. . . . . . . . . . . . . . . . . . . . . . . 950 Incremental Signoff
Performing Effective Resistance Analysis . . . . . . . . . ECO Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .914 Performing
. . . . . . . 952 ECO Fusion Flow . . . . . . . . . . . . . . . . .
Distributed RedHawk Fusion Rail Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954 ECO
. . . . . . . . . . . . . 915 Voltage Driven Power Switch Fusion Power Integrity Flow . . . . . . . . . . . . . . . . . . .
Cell Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .955
918 Working With Macro Models . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . .920
Generating Macro Models . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 920 Creating Block Contexts
..........................................
922 Performing Signoff Analysis . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 924 Writing
Analysis and Checking Reports . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 925 Displaying Block-Level Rail
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
929 Generating Instance-Based Analysis Reports . .
. . . . . . . . . . . . . . . . . . . . . . . 929 Generating
Geometry-Based Analysis Reports . . . . . . . . . . . . . .
. . . . . . . . . . 931 Displaying Maps in the GUI . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932
Displaying ECO Shapes in the GUI . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 938 Voltage Hotspot
Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 939 Generating Hotspots . . . . . . . . . . . . .
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Manually Instantiating Spare Cells . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . 956 Automatically
Adding Spare Cells . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . .958 Adding Programmable Spare
Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.960 Making ECO Changes Using the eco_netlist
Command . . . . . . . . . . . . . . . . . . . . 961 Making
ECO Changes Using Netlist Editing Commands . . . .
. . . . . . . . . . . . . . . . 962
Using ECO Scripts for Netlist Editing . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . .962 Resizing Cells . . . . . . . .
..........................................
. . . 962 Reverting Changes Made During Resizing . .
. . . . . . . . . . . . . . . . . . . . . . . . . 963 Adding Buffers
on Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . .963 Adding Buffers on Routed Nets . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
Specifying the Net Names, Buffers Types, and Their
Locations . . . . . . . . . . . 964 Adding Buffers in a
Specified Configuration . . . . . . . . . . . . . . . . . . . . . . .
965 Adding Buffers at Specified Locations . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 965 Adding Buffers at a
Specified Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . .
966 Adding Buffers at an Interval That is a Ratio of
the Net Length . . . . . . . . .967 Adding Buffers on a
Bus in a Specified Pattern . . . . . . . . . . . . . . . . . . . .
.967 Controlling How Buffers are Added . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 970 Specifying Settings
for Multivoltage Designs . . . . . . . . . . . . . . . . . . . . . .
. . . . 970 Specifying Settings for the Freeze Silicon
ECO Flow . . . . . . . . . . . . . . . . . . . 971 Optimizing
the Fanout of a Net . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . .971 Reporting Available Sites for
Placing ECO Cells . . . . . . . . . . . . . . . . . . . . . . . . . .
972 Identifying and Reverting Nonoptimal ECO
25 Changes . . . . . . . . . . . . . . . . . . . . . . .972 Placing
ECO Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . .973 Controlling Placement
When Using the place_eco_cells Command . . . . . . .
. 973 Controlling Legalization When Using the
place_eco_cells Command . . . . . . . 975 Placing
ECO Cells With Minimal Physical Impact (MPI) . . . .
. . . . . . . . . . . . . 977 Placing and Mapping ECO
Cells to Spare Cells . . . . . . . . . . . . . . . . . . . . . . . . . .
977 Specifying Mapping Rules for Programmable
Spare Cells . . . . . . . . . . . . . . . .978 Mapping ECO
Cells to Specific Spare Cells . . . . . . . . . . . . . . . . . . .
. . . . . . . 978 Mapping ECO Cells to Logically
Equivalent Spare Cells . . . . . . . . . . . . . . . . . 979
Updating Supply Nets for ECO Cells . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 979 Recording the
Changes Made to a Layout . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . .980 Performing Prerequisite Check for
Group Repeater Insertion and Placement . . . . 980
Adding a Group of Repeaters . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .981 Defining a group of
repeaters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . .982 Grouping a list of repeaters . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 983

26
 . . . . . . . . . . . . . . . . . . . . . . . . . . . 992 Grouping
Variant Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
Feedback . . . . . . . . . . . . 993 Running and Placing Group
Repeaters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999
Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .999
Setting Constraints for a Group of Repeaters . . . . . .
Fixing Multivoltage Violations . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 983 Adding Voltage Area
. . . . . . . . . . . . . . . . . . . . . . 1006 Fixing Buffers . . . .
Aware Group Repeaters . . . . . . . . . . . . . . . . . . . . . .
..........................................
. . .983 Reporting the Constraints Assigned to a
. . . 1007 Fixing Diodes . . . . . . . . . . . . . . . . . . . . . . .
Group of a Repeaters . . . . . . . . . . . 984 Removing
. . . . . . . . . . . . . . . . . . . . . . . . . . 1008
Constraints for a Group of Repeaters . . . . . . . . . . . .
. . . . . . . . . . . 984 Placing Group Repeaters Before
Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984
Performing On Route Placement of Repeaters . . . . .
. . . . . . . . . . . . . . . . . . . 985 Placing Group
Repeaters For Multibit Registers . . . . . . . . . . . . . . . .
. . . . . . . 985 Specifying Locations for Repeater
Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . .986
Allowing Repeater Groups Over Macros . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 986 Specifying Cut Space
and Cut Distance for Repeater Groups . . . . . . . . . . .
. .987 Specifying Horizontal and Vertical Spacing for
Repeater Groups . . . . . . . . . . 987 Specifying Library
Cells as Repeaters . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 987 Avoiding Overlapping Repeaters With
Existing Tap Cells . . . . . . . . . . . . . . . . 987 Avoiding
Crosstalk During Group Repeater Insertion . . . . . . . .
. . . . . . . . . . . .987 Previewing Repeater Groups . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988
Unplacing the Repeaters . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 989 Removing Repeater
Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . .989
Querying Group Repeater . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .989 Performing Auto
Grouping Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 990 Performing Manual Grouping Flow . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .990 Cell Input
Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 991
Swapping Variant Cell . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 991 Setting Constraints
of Variant Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 992 Setting Application Option . . . . . . . . . . . . .
27
 Feedback

About This User Guide

The Synopsys Fusion Compiler tool provides a complete netlist-to-GDSII or netlist-to
OASIS® design solution, which combines proprietary design planning, physical synthesis,
clock tree synthesis, and routing for logical and physical design implementation throughout
the design flow.
This guide describes the Fusion Compiler implementation and integration flow. For more
information about the Fusion Compiler tool, see the following companion volumes:
• Library Manager User Guide
• Fusion Compiler Design Planning User Guide
• Fusion Compiler Data Model User Guide
• Fusion Compiler Timing Analysis User Guide
• Fusion Compiler Graphical User Interface User Guide
• Fusion Compiler Multivoltage User Guide
• Fusion Compiler Power Analysis User Guide
This user guide is for design engineers who use the Fusion Compiler tool to implement
designs.
To use the Fusion Compiler tool, you need to be skilled in physical design and synthesis
and be familiar with the following:
• Physical design principles
• The Linux operating system
• The tool command language (Tcl)
This preface includes the following sections:
• New in This Release
• Related Products, Publications, and Trademarks
• Conventions
• Customer Support
• Statement on Inclusivity and Diversity
 New in This Release

Fusion Compiler™ User Guide V-2023.12-SP3

New in This Release
Feedback
28

About This User Guide

Information about new features, enhancements, and changes, known limitations, and
resolved Synopsys Technical Action Requests (STARs) is available in the Fusion Compiler
Release Notes on the SolvNetPlus site.

Related Products, Publications, and Trademarks

For additional information about the Fusion Compiler tool, see the documentation on the
Synopsys SolvNetPlus support site at the following address:
https://solvnetplus.synopsys.com
You might also want to see the documentation for the following related Synopsys products:
®
• Design Compiler

• IC Validator
®
• PrimeTime Suite
• StarRC™

Conventions
The following conventions are used in Synopsys documentation.

Convention Description

Courier Indicates syntax, such as write_file

Courier italic Indicates a user-defined value in syntax, such as

write_file design_list

Courier bold Indicates user input—text you type verbatim—in examples, such as
prompt> write_file top

Purple • Within an example, indicates information of special interest. • Within a command-syntax

section, indicates a default, such as
include_enclosing = true | false

[ ] Denotes optional arguments in syntax, such as

 write_file [-format fmt]

About This User Guide

Customer Support

Fusion Compiler™ User Guide V-2023.12-SP3 Convention Description

29 Feedback

... Indicates that arguments can be repeated as many times as needed, such as
pin1 pin2 ... pinN.

| Indicates a choice among alternatives, such as low | medium | high

\ Indicates a continuation of a command line.

/ Indicates levels of directory structure.

Bold Indicates a graphical user interface (GUI) element that has an action associated with it.

Edit > Copy Indicates a path to a menu command, such as opening the Edit menu and
choosing Copy.

Ctrl+C Indicates a keyboard combination, such as holding down the Ctrl key and pressing C.

Customer Support
Customer support is available through SolvNetPlus.

Accessing SolvNetPlus
The SolvNetPlus site includes a knowledge base of technical articles and answers to
frequently asked questions about Synopsys tools. The SolvNetPlus site also gives you
access to a wide range of Synopsys online services including software downloads,
documentation, and technical support.
To access the SolvNetPlus site, go to the following address:
https://solvnetplus.synopsys.com
If prompted, enter your user name and password. If you do not have a Synopsys user
name and password, follow the instructions to sign up for an account.
If you need help using the SolvNetPlus site, click REGISTRATION HELP in the top-right
menu bar.

Contacting Customer Support

 To contact Customer Support, go to https://solvnetplus.synopsys.com.
30

Fusion Compiler™ User Guide V-2023.12-SP3

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About This User Guide
Statement on Inclusivity and Diversity

Statement on Inclusivity and Diversity

Synopsys is committed to creating an inclusive environment where every employee,
customer, and partner feels welcomed. We are reviewing and removing exclusionary
language from our products and supporting customer-facing collateral. Our effort also
includes internal initiatives to remove biased language from our engineering and working
environment, including terms that are embedded in our software and IPs. At the same
time, we are working to ensure that our web content and software applications are usable
to people of varying abilities. You may still find examples of non-inclusive language in our
software or documentation as our IPs implement industry-standard specifications that are
currently under review to remove exclusionary language.
Fusion Compiler™ User Guide
31
V-2023.12-SP3
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1
Working With the Fusion Compiler Tool
The Fusion Compiler tool supports the following functionality:
 • Extraction and timing analysis
• Physical synthesis and optimization
• Placement and optimization, including relative placement
• Clock tree synthesis
• Routing
• Chip finishing
• Top-level closure for hierarchical designs
• Engineering change orders (ECO)
• Reporting
• ASCII output interfaces
It takes as input a Verilog netlist, timing constraints, logic and physical libraries, and
foundry-process data. It generates as output an OASIS- or GDSII-format file of the layout
or a Design Exchange Format (DEF) file of placed netlist data ready for a third-party
router. The Fusion Compiler tool can also output the design at any time as a binary design
database or as ASCII files (Verilog, DEF, and timing constraints).
The Fusion Compiler tool provides a unified
• Data model, which enables sharing of libraries, design data, constraints, and design
intent throughout the entire implementation flow and is architected to support ultra
large designs with a small memory footprint
• Graphical user interface (GUI), which enables seamless visual analysis of timing paths,
power intent, schematic, and layout, with full cross-probing between the RTL and netlist
• Design mismatch mitigation infrastructure, which provides user controls to mitigate
incomplete or mismatched library and design data
• Fusion Compiler Concepts
• Working With the 3DIC Compiler User
Interfaces
Fusion Compiler™ User Guide V-2023.12-SP3 • Entering fc_shell Commands
32
• Using Application Options
Chapter 1: Working With the Fusion Compiler Tool
Physical Synthesis Design Flow Overview • Using Variables
• Viewing Man Pages
The following topics describe how to use the
• Using Tcl Scripts
Fusion Compiler tool: • Physical Synthesis
• Adding Changes to a Script With Checkpoints
Design Flow Overview
• Using Setup Files
• Formal Verification
• Using the Command Log File
• Place and Route Design Flow Overview
 Feedback
• Enabling Multicore Processing

For information about working with design data in the Fusion Compiler tool, see the Fusion
Compiler Data Model User Guide.

Physical Synthesis Design Flow Overview

Figure 1shows the basic physical synthesis design flow.
 33

Chapter 1: Working With the Fusion Compiler Tool

Formal Verification

Figure 1 Fusion Compiler Physical Synthesis

Flow

Tech.

data TLU+ files UPF files DEF/Tcl

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Handle design

mismatches and

Ref. lib (NDM)

Design (NDM) black boxes

Apply

multivoltage

power intent

Apply timing and

physical

constraints Set

up clock-gating

cells

Set up DFT and

insert DFT

structures Insert
RTL/ Set up the Read RTL files
netlist
libraries
multivoltage design

(Optional)
cells SDC files (Optional)

Compile the
design

Analyze and
report QoR

Export the
 Verilog UPF files DEF/
Design
SDC files SCANDEF
(NDM)

Formal Verification

The Formality tool uses formal techniques to prove or disprove the functional equivalence
of two designs. It performs RTL-to-RTL, RTL-to-gate, and gate-to-gate verifications.
Functional equivalence checking does not take into account static timing verification. The
Chapter 1: Working With the Fusion Compiler Tool
Place and Route Design Flow Overview
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34
 following figure shows an overview of the design flow from the Fusion Compiler tool to the
Formality tool:

Tech.

data TLU+ files UPF files DEF/Tcl

Ref. lib (NDM)
RTL/ (Optional)
netlist SDC files (Optional)

Synthesis

Design
SVF files
Verilog UPF files
(NDM)

Formality

Place and Route Design Flow Overview

Figure 2shows the basic place and route design flow using the Fusion Compiler tool.
Fusion Compiler™ User Guide
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V-2023.12-SP3
Chapter 1: Working With the Fusion Compiler Tool
Place and Route Design Flow Overview

Figure 2 Fusion Compiler Place and Route

Flow

To run the Fusion Compiler place and route

flow, Feedback

1. Set up the libraries and prepare the design data, as described in Preparing the
Design. 2. Perform design planning and power planning.

When you perform design planning and power planning, you create a floorplan to
determine the size of the design, create the boundary and core area, create site rows
for the placement of standard cells, set up the I/O pads, and create a power plan.
For more information about design planning and power planning, see the Fusion
Compiler Design Planning User Guide.
3. Perform placement and optimization.
To perform placement and optimization, use the place_opt command.
The place_opt command addresses and resolves timing closure for your design.
This iterative process uses enhanced placement and synthesis technologies to
generate
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36

legalized placement for leaf cells and an optimized design. You can supplement
this functionality by optimizing for power, recovering area for placement, minimizing
congestion, and minimizing timing and design rule violations.
4. Perform clock tree synthesis and optimization.
To perform clock tree synthesis and optimization, use the clock_opt command.
Fusion Compiler clock tree synthesis and embedded optimization solve complicated
clock tree synthesis problems, such as blockage avoidance and the correlation
between preroute and postroute data. Clock tree optimization improves both clock
skew and clock insertion delay by performing buffer sizing, buffer relocation, gate
sizing, gate relocation, level adjustment, reconfiguration, delay insertion, dummy load
insertion, and balancing of interclock delays.
For more information about clock tree synthesis and optimization, see Clock Tree
Synthesis.
5. Perform routing and postroute optimization, as described in Routing and Postroute
Optimization.
The Fusion Compiler tool uses Zroute to perform global routing, track assignment,
detail routing, topological optimization, and engineering change order (ECO) routing.
To perform postroute optimization, use the route_opt command. For most designs,
the default postroute optimization setup produces optimal results. If necessary, you can
supplement this functionality by optimizing routing patterns and reducing crosstalk or
by customizing the routing and postroute optimization functions for special needs.
6. Perform chip finishing and design for manufacturing tasks, as described in Chip
Finishing and Design for Manufacturing.
The Fusion Compiler tool provides chip finishing and design for manufacturing and
design for yield capabilities that you can apply throughout the various stages of the
design flow to address process design issues encountered during chip
manufacturing.
7. Save the design.

Fusion Compiler Concepts

This topic introduces the following concepts used in the Fusion Compiler
tool: • Power Intent Concepts

• UPF Flows
• Multiple-Patterning Concepts
 Fusion Compiler Concepts

Power Intent Concepts

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Chapter 1: Working With the Fusion Compiler Tool

The UPF language establishes a set of commands to specify the low-power design intent
for electronic systems. Using UPF commands, you can specify the supply network,
switches, isolation, retention, and other aspects relevant to power management of a chip
design. The same set of low-power design specification commands is to be used
throughout the design, analysis, verification, and implementation flow. Synopsys tools are
designed to follow the official IEEE 1801 UPF standard.
The UPF language provides a way to specify the power requirements of a design, but
without specifying explicitly how those requirements are implemented. The language
specifies how to create a power supply network for each design element, the behavior of
supply nets with respect to each other, and how the logic functionality is extended to
support dynamic power switching to design elements. It does not contain any placement or
routing information.
In the UPF language, a power domain is a group of elements in the design that share a
common set of power supply needs. By default, all logic elements in a power domain use
the same primary supply and primary ground. Other power supplies can be defined for a
power domain as well. A power domain is typically implemented as a contiguous voltage
area in the physical chip layout, although this is not a requirement of the language.
Each power domain has a scope and an extent. The scope is the level of logic hierarchy
designated as the root of the domain. The extent is the set of logic elements that belong to
the power domain and share the same power supply needs. The scope is the hierarchical
level at which the domain is defined and is an ancestor of the elements belonging to the
power domain, whereas the extent is the actual set of elements belonging to the power
domain.
Each scope in the design has supply nets and supply ports at the defined hierarchical
level of the scope. A supply net is a conductor that carries a supply voltage or ground
throughout a given power domain. A supply net that spans more than one power domain is
said to be “reused” in multiple domains. A supply port is a power supply connection point
between two adjacent levels of the design hierarchy, between the parent and child blocks
of the hierarchy. A supply net that crosses from one level of the design hierarchy to the
next passes through a supply port.
A supply set is an abstract collection of supply nets, consisting of two supply functions,
power and ground. A supply set is domain-independent, which means that the power and
ground in the supply set are available to be used by any power domain defined within the
scope where the supply set was created. However, each power domain can be restricted
 to limit its usage of supply sets within that power domain.
You can use supply sets to define power intent at the RTL level, so you can synthesize a
design even before you know the names of the actual supply nets. A supply set is an
abstraction of the supply nets and supply ports needed to power a design. Before such a
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38

design can physically implemented (placed and routed), its supply sets must be refined, or
associated with actual supply nets.
A supply set handle is an abstract supply set created for a power domain. By default, a
power domain has supply set handles for the domain’s primary supply set, a default
isolation supply set, and a default retention supply set. These supply set handles let you
synthesize a design even before you create any supply sets, supply nets, and supply ports
for the power domain. Before such a design can be physically implemented, its supply set
handles must be refined, or associated with actual supply sets; and those supply sets
must be refined so that they are associated with actual supply nets.
A power switch (or simply switch) is a device that turns on and turns off power for a supply
net. A switch has an input supply net, an output supply net that can be switched on or off,
and at least one input signal to control switching. The switch can optionally have multiple
input control signals and one or more output acknowledge signals. A power state table
lists the allowed combinations of voltage values and states of the power switches for all
power domains in the design.
A level shifter must be present where a logic signal leaves one power domain and enters
another at a substantially different supply voltage. The level shifter converts a signal from
the voltage swing of the first domain to that of the second domain.
An isolation cell must be present where a logic signal leaves a switchable power domain
and enters a different power domain. The level shifter generates a known logic value
during shutdown of the domain. If the voltage levels of the two domains are substantially
different, the interface cell must be able to perform both level shifting (when the domain
is powered up) and isolation (when the domain is powered down). A cell that can perform
both functions is called an enable level shifter.
In a power domain that has power switching, any registers that must retain data during
shutdown must be implemented as retention registers. A retention register has a separate,
always-on supply net, sometimes called the backup supply, which keeps the data stable in
the retention register while the primary supply of the domain is shut down.

UPF Flows
The Fusion Compiler tool supports both the traditional UPF flow and the golden UPF
flow. The golden UPF flow is an optional method of maintaining the UPF multivoltage
power intent of the design. It uses the original “golden” UPF file throughout the synthesis,
physical implementation, and verification steps, along with supplemental UPF files
 generated by the Fusion Compiler tool.
Fusion Compiler Concepts

Figure 3compares the traditional UPF flow with

the golden UPF flow. Figure 3 UPF-Prime

Fusion Compiler™ User Guide V-2023.12-SP3 (Traditional) and Golden UPF Flows
39
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The golden UPF flow maintains and uses the same, original “golden” UPF file throughout
the flow. The Fusion Compiler tool writes power intent changes into a separate
“supplemental” UPF file. Downstream tools and verification tools use a combination of the
golden UPF file and the supplemental UPF file, instead of a single UPF’ or UPF’’ file.
The golden UPF flow offers the following advantages:
• The golden UPF file remains unchanged throughout the flow, which keeps the form,
structure, comment lines, and wildcard naming used in the UPF file as originally
written.
• You can use tool-specific conditional statements to perform different tasks in different
tools. Such statements are lost in the traditional UPF-prime flow.
• Changes to the power intent are easily tracked in the supplemental UPF file.
• You can optionally use the Verilog netlist to store all PG connectivity information,
making connect_supply_net commands unnecessary in the UPF files. This
can significantly simplify and reduce the overall size of the UPF files.
To enable the golden UPF flow, use the following application option setting before you load
the UPF:
 fc_shell> set_app_options -as_user_default \
-list {mv.upf.enable_golden_upf true}

To load supplemental UPF files, use the -supplemental option with the
load_upf command.

For more information about using the golden UPF flow, see SolvNet article 1412864,
“Golden UPF Flow Application Note.”
Fusion Compiler Concepts

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40
Multiple-Patterning Concepts
Chapter 1: Working With the Fusion Compiler Tool Feedback

At the 20-nm process node and below, printing the required geometries is extremely
difficult with the existing photolithography tools. To address this issue, a new technique,
multiple patterning, is used to partition the layout mask into two or more separate masks,
each of which has an increased manufacturing pitch to enable higher resolution and better
printability. Figure 4shows an example of double-patterning, where the layout mask is
partitioned into two separate masks, MASK A and MASK B.

Figure 4 Double-Patterning Example

To use multiple patterning, you must be able to decompose the layout into two or more
masks, each of which meets the multiple-patterning spacing requirements. A multiple
patterning violation occurs if your layout contains a region with an odd number of
neighboring shapes where the distance between each pair of shapes is smaller than the
multiple-patterning minimum spacing. This type of violation, which is called an odd cycle,
is shown in Figure 5.
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Fusion Compiler Concepts

Figure 5 Odd-Cycle Violation

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If the spacing between any pair in the loop is greater than the multiple-patterning minimum
spacing, no violation occurs and the layout can be decomposed. For example, in Figure 6,
if the spacing, x, between segments B and C is greater than the multiple-patterning
minimum spacing, there is no odd cycle and the layout can be decomposed.

Figure 6 No Odd-Cycle Violation

The Fusion Compiler tool ensures that the generated layout is conducive to double
patterning by considering the multiple-patterning spacing requirements during placement
and routing and preventing odd cycles.
In general, double patterning is performed only on the bottom (lowest) metal layers, which
are referred to as multiple-patterning layers. The metal shapes on the multiple-patterning
 layers must meet the multiple-patterning spacing requirements, whether they are routing
shapes or metal within the standard cells and macros. The metal shapes on other layers
do not need to meet the stricter multiple-patterning spacing requirements.
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Multiple-patterning considerations affect all parts of the place and route flow. Depending
on your standard cell library, you follow either an uncolored or precolored multiple
patterning flow.
• You use the uncolored flow if the cells in your standard cell library have sufficient
spacing to the cell boundaries to ensure that multiple-patterning violations do not occur
during placement. This type of library is referred to as a correct-by-construction library;
most multiple-patterning libraries are correct-by-construction libraries.
In the uncolored flow, the tool determines the appropriate mask settings for the pins
and net shapes.
• You use the precolored flow if the cells in your standard cell library have assigned
masks on the metal shapes inside the cells. These assigned masks are often referred
to as colors and this type of library is referred to as a precolored library.
In the precolored flow, the tool must consider these mask assignments to ensure that
multiple-patterning violations do not occur during placement. The tool also uses the
mask assignments to determine the appropriate mask settings for the pins and net
shapes.
The mask assignments are represented as mask constraints in the Fusion Compiler
tool. You must ensure that the mask constraints are properly set before starting place
and route. For information about the mask constraints, see Mask Constraints.

Mask Constraints
Mask constraints indicate the mask requirements for the metal shapes of the physical pins
and nets in a block that uses multiple-patterning technology. These mask requirements
drive placement and routing to ensure that the resulting layout is multiple-patterning
compliant.
Note:
Mask constraints are used only for the precolored flow; they are not necessary
in the uncolored flow.
You can set mask constraints on timing-critical nets (net shapes, routing rules, and routing
blockages) and vias. For nets, the mask constraint is defined in the mask_constraint
attribute. For vias, the mask constraints are defined in the lower_mask, upper_mask, and
 cut_mask attributes. Table 1shows the supported values for these attributes.

Table 1 Mask Constraint Values

Attribute value Description

same_mask This constraint means that the mask color is not yet been determined. Shapes with
this attribute must be at least the multiple-patterning minimum spacing
distance from any other colored metal shape.

Table 1 Mask Constraint Values (Continued)

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43 Attribute value Description
Chapter 1: Working With the Fusion Compiler Tool Feedback
Working With the 3DIC Compiler User Interfaces

mask_one This constraint means that the shape has the mask1 color. Shapes with this attribute
must be at least the multiple-patterning minimum spacing distance
from other mask1-colored metal shapes.

mask_two This constraint means that the shape has the mask2 color. Shapes with this attribute
must be at least the multiple-patterning minimum spacing distance
from other mask2-colored metal shapes.

mask_three This constraint means that the shape has the mask3 color. Shapes with this
attribute must be at least the multiple-patterning minimum spacing distance
from other mask3-colored metal shapes.

any_mask This constraint means that the shape is not colored. Shapes with this attribute must be
at least the standard minimum spacing distance from other metal
shapes; the multiple-patterning minimum spacing rules do not apply to these
shapes.

Working With the 3DIC Compiler User Interfaces

The Fusion Compiler tool operates in the X Window environment on Linux. IThe tool
provides a flexible working environment with both a shell command-line interface and a
GUI. The CLI is always available during a Fusion Compiler session. You can start or exit a
session in either the shell or the GUI, and you can open or close the GUI during a session.
The tool uses Tcl, which is used in many applications in the EDA industry. Using Tcl, you
can extend the fc_shell command language by writing reusable procedures and scripts
(see the Using Tcl With Synopsys Tools manual).
The following topics describe how to start and exit the tool using the command-line
interface.
 • Starting the CLI
• Exiting the Fusion Compiler Tool
For information about using the GUI, see the Fusion Compiler Graphical User Interface
User Guide.
The following topics describe how to use the user interfaces of the Fusion Compiler
tool: • Starting the GUI

• Closing the GUI

Working With the 3DIC Compiler User Interfaces

Starting the CLI

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Chapter 1: Working With the Fusion Compiler Tool

The CLI interface is a text-only environment in which you enter commands at the
command-line prompt. It is typically used for scripts, batch mode, and push-button
operations.
Before you start the command-line interface, ensure that the path to the bin directory is
included in your $PATH variable.
To start fc_shell,
► Enter the fc_shell command in a Linux shell.
% fc_shell

You can include other options on the command line when you start the shell. For example,
you can use
• -file script_file_name to execute a script
• -x command to execute a command
• -output_log_file file_name to create a log file of your session •
-help to display a list of the available options (without starting the shell)
At startup, the tool :

1. Creates a command log file.

2. Reads and executes the setup files.
3. Executes any script files or commands specified by the -file and -x
options, respectively, on the command line.
 4. Displays the program header and fc_shell> prompt in the shell.

See Also
• Using the Command Log File
• Using Setup Files
• Using Tcl Scripts
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Entering fc_shell Commands

Exiting the Fusion Compiler Tool

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You can end the session and exit the Fusion Compiler tool at any time. To exit the tool, use
the exit or quit command.
Note:
When you exit the tool from the command line, the tool exits without saving the
open blocks.

Entering fc_shell Commands

You interact with the Fusion Compiler tool by using fc_shell commands, which are based
on the Tool Command Language (Tcl) and include certain command extensions needed
to implement specific Fusion Compiler functionality. The Fusion Compiler command
language provides capabilities similar to Linux command shells, including variables,
conditional execution of commands, and control flow commands. You can
• Enter individual commands interactively at the fc_shell> prompt in fc_shell • Enter
individual commands interactively on the console command line in the GUI

• Run one or more Tcl scripts, which are text files that contain fc_shell commands (see
Using Tcl Scripts)
When entering a command, an option, or a file name, you can minimize your typing by
pressing the Tab key when you have typed enough characters to specify a unique name;
the Fusion Compiler tool completes the remaining characters. If the characters you typed
could be used for more than one name, the Fusion Compiler tool lists the qualifying
names, from which you can select by using the arrow keys and the Enter key.
 If you need to reuse a command from the output for a command-line interface, you can
copy and paste the portion by selecting it, moving the pointer to the fc_shell command
line, and clicking with the middle mouse button.
When you run a command, the Fusion Compiler tool echoes the command output
(including processing messages and any warnings or error messages) in fc_shell and, if
the GUI is open, in the console log view. By default, the tool does not use page mode, so
the output might scroll. To enable page mode, set the sh_enable_page_mode variable
to true.
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Chapter 1: Working With the Fusion Compiler Tool

Entering fc_shell Commands

Interrupting or Terminating
Command Processing
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If you enter the wrong options for a command or enter the wrong command, you can
interrupt command processing and remain in fc_shell. To interrupt or terminate a
command, press Ctrl+C.
Some commands and processes cannot be interrupted. To stop these commands or
processes, you must terminate fc_shell at the system level. When you terminate a process
or the shell, no data is saved.
When you use Ctrl+C, keep the following points in mind:
• If a script file is being processed and you interrupt one of its commands, the script
processing is interrupted and no further script commands are processed.
• If you press Ctrl+C three times before a command responds to your interrupt, fc_shell
is interrupted and exits with this message:
Information: Process terminated by interrupt.

Getting Information About Commands

The following online information resources are available while you are using the Fusion
Compiler tool:
• Command help, which is information about an Fusion Compiler command
• Man pages

See Also
 • Viewing Man Pages

Displaying Command Help

Command help consists of either a brief description of aFusion Compiler command or a
list of the options and arguments supported by an Fusion Compiler command.
• To display a brief description of a Fusion Compiler command, enter the help command
followed by the command name. For example, to display a brief description of the
report_timing command, use the following command:

fc_shell> help report_timing

• To display the options supported by a Fusion Compiler command, enter the command
name with the -help option on the command line. For example, to see the options
supported by the report_timing command, use the following command:
fc_shell> report_timing -help
Using Application Options

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Using Application Options
Chapter 1: Working With the Fusion Compiler Tool Feedback

The Fusion Compiler tool uses application options to control the tool behavior. Application
options use the following naming convention:
category[.subcategory].option_name

where category is the name of the engine affected by the application option. Some
application option categories have subcategories to further refine the area affected by the
application option.
Application options have either a global scope or a block scope.
• Block-scoped application options apply only to the block on which they are set. They
are saved in the design library and are persistent across tool sessions.
• Global-scoped application options apply to all blocks, but only within the current
session. They are not saved in the design library; you must specify them in
each fc_shell session. You might want to consider adding the global settings to
your .synopsys_fc.setup file.
To get a list of available application options, use the get_app_options command.
By default, this command lists all application options. To restrict the reported
application options, provide a pattern string as an argument to the command.
For example, to list all available application options, use the following
command: fc_shell> get_app_options
 To list all available timer application options, use the following
command: fc_shell> get_app_options timer.*

To generate a report of application options, use the report_app_options command.

For detailed information about application options, see Application Options in the Fusion
Compiler Data Model User Guide.

See Also
• Using Setup Files

Using Variables
In general, the Fusion Compiler tool modifies default behavior by using application options
rather than application variables; however it does support user-defined Tcl variables, as
well as a minimal number of application variables, such as the search_path variable.
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To list the variables and their values, use the printvar command. For example, to list
all variables defined in the current session, use the following command:
fc_shell> printvar *

To print the value of the search_path variable, use the following

command: fc_shell> printvar search_path

See Also
• Defining the Search Path

Viewing Man Pages

To display the man page for a Fusion Compiler command or application option, enter the
man command followed by the command or application option name. For example, to
see the man page for the report_timing command, use the following command:
fc_shell> man report_timing

To display the man page for a Fusion Compiler application option, enter the man
command followed by the option name. You can also view the following types of summary
pages for application options:
• Category summaries
 To view a man page that summarizes all of the application options for a specific
category, enter the man command followed by category_options. For example,
to see the man page that summarizes all timer application options, use the
following command:
fc_shell> man timer_options

• Subcategory summaries
To view a man page the summarizes all of the application options for a specific
subcategory, enter the man command followed by category.subcategory_options.
For example, to see the man page that summarizes all common route application
options, use the following command:
fc_shell> man route.common_options
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Using Tcl Scripts

• Command summaries
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To view a man page the summarizes all of the application options for a specific
command, enter the man command followed by command_options. For example, to
see the man page that summarizes all application options that affect the
report_timing command, use the following command:

fc_shell> man report_timing_options

If you enter the man command on the fc_shell command line, the man page is displayed
in the Fusion Compiler shell and in the console log view if the GUI is open. If you enter
this command on the console command line in the GUI, the man page is displayed in the
GUI man page viewer.

Using Tcl Scripts

You can use Tcl scripts to accomplish routine, repetitive, or complex tasks. You create a
command script file by placing a sequence of Fusion Compiler commands in a text file.
Any Fusion Compiler command can be executed within a script file.
In Tcl, a pound sign (#) at the beginning of a line denotes a comment. For
example, # This is a comment

For more information about writing scripts and script files, see the Using Tcl With
Synopsys Tools manual.
 Use one of the following methods to run a Tcl script:
• Use the -file option with the fc_shell command when you start the Fusion
Compiler tool.
• Use the source command from the fc_shell command line.
• Choose File > Execute Script in the GUI.
If an error occurs when running a command, the Fusion Compiler tool raises the
TCL_ERROR condition, which immediately stops the script execution. To tolerate errors
and allow the script to continue executing, either
• Check for TCL_ERROR error conditions with the Tcl catch command on the
commands that might generate errors.
• Set the sh_continue_on_error variable to true in the script file.
• Starting the CLI
• Adding Changes to a Script With Checkpoints

Adding Changes to a Script With

Fusion Compiler™ User Guide V-2023.12-SP3 Checkpoints
50 Feedback
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Adding Changes to a Script With Checkpoints

See Also

When running experiments on a block, you might might modify your golden flow scripts in
two ways:
• By making flow changes, such as setting application options, modifying constraints, or
making other changes to improve the quality of results
• By generating reports (either additional reports or reports at new places in the flow) to
help debug an issue
In most flows, you apply changes through a small number of static, modifiable files. Here
is a typical example to run the place_opt flow, where you source a
pre_place_opt_settings.tcl file to add flow changes and a generate_reports.tcl file to run all
 your reporting at the end of the script:
open_block ./design:init_design
source ./scripts/pre_place_opt_settings.tcl
remove_buffer_trees -all
place_opt -from initial_place -to initial_drc
create_placement -incremental -timing_driven -congestion
place_opt -from initial_drc -to -initial_opto
place_opt -from final_place -to final_opto
source ./scripts/generate_reports.tcl

In some cases, complex changes require modifying your golden flow script directly, which
might be discouraged or difficult to do in many design environments. These changes can
be time consuming to implement, especially if you are implementing them at multiple
stages in the design flow, across multiple blocks, or for several different flow experiments.
The checkpoint system streamlines this process and allows you to run experiments
without modifying your golden flow scripts. When you use the checkpoint system, you
define checkpoints for important steps in your golden flow. These checkpoints enwrap the
commands associated with the given steps. By default, the checkpoints run only the code
they enwrap. That is, simply inserting checkpoints in your script does not change your
flow. However, you can associate these checkpoints with flow changes or reports that you
want to run before, after, or in place of the code the checkpoints enwrap. By defining these
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associations in a portable configuration file, you isolate your golden flow scripts from the
changes you want to apply for a particular run.
The following figure shows how you can use checkpoints to instantly apply a set of flow
changes or reports to multiple designs, without modifying each design's golden flow script.
In this case, the configuration file has been copied to each design's run directory.
 In addition, when multiple users are working on a project, each user can have an individual
checkpoint.config.tcl file with his or her preferred settings:

The checkpoint system also allows you to

• Insert flow changes and reports with more precision than you could using a typical non
checkpointed flow script
• Reference a single source of truth where you can find all changes that have been
applied to your default golden flow
• Report a history of the checkpoints that were run, including the flow changes or reports
that were run at those checkpoints
unique and descriptive report names

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system is as follows: 1. Insert checkpoints in
Chapter 1: Working With the Fusion Compiler Tool
Adding Changes to a Script With Checkpoints your script.

2. Configure your checkpointsby

• Report runtime and memory information for Feedback

each checkpoint that was run • Generate

 ◦ Defining the flow changes or reports you want to associate with the checkpoints
◦ Associating the flow changes or reports you defined with your checkpoints 3. Run
your script.

Defining Checkpoints
To define a checkpoint, insert the eval_checkpoint command in your script. Specify
a unique name for the checkpoint and wrap the checkpoint around a block of code.
Note the following:
• If you define a checkpoint with the same name as an existing checkpoint, the tool
automatically adds a unique suffix to the name of the newly-defined checkpoint when it
encounters the checkpoint in a run. For example, if you duplicate a checkpoint named
placement, the tool renames the duplicate to placement2 when it encounters the
checkpoint in a run.
• Do not nest checkpoints within other checkpoints. Although the tool does not prevent
you from defining nested checkpoints, the tool ignores nested checkpoints during a
run, executing only the outermost checkpoints (note that the Tcl code inside nested
checkpoints still runs, but runs as though the checkpoints do not exist).
Suppose you have a simple place_opt script:
open_block ./design:init_design
source ./scripts/pre_place_opt_settings.tcl
remove_buffer_trees -all
place_opt -from initial_place -to initial_drc
create_placement -incremental -timing_driven -congestion
place_opt -from initial_drc -to -initial_opto
place_opt -from final_place -to final_opto

The following example wraps a checkpoint around each major step in your golden flow.
The checkpoints are named remove_buffers, place_opt_to_initial_drc, incr_placement,
place_opt_to_initial_opto, and place_opt_to_final_opto.
open_block ./design.nlib:init_design
source ./scripts/pre_place_opt_settings.tcl
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 eval_checkpoint place_opt_to_initial_op
eval_checkpoint remove_buffers { to {
remove_buffer_trees -all place_opt -from initial_drc -to ini
} tial_opto
}
eval_checkpoint place_opt_to_initial_dr
c { eval_checkpoint place_opt_to_final_opto
place_opt -from initial_place -to i {
nitial_drc } place_opt -from final_place -to fin
al_opto
eval_checkpoint incr_placement { }
create_placement -incremental -timi Feedback
ng_driven -congestion }

By default, the checkpoints run the Tcl code they enwrap. That is, simply inserting
checkpoints with the eval_checkpoint command does not change your flow. However,
you can associate these checkpoints with flow changes or reports that you want to run
before, after, or in place of the code the checkpoints enwrap, as described in Configuring
Checkpoints.

See Also
• Configuring Checkpoints
• Querying Checkpoints and Checkpoint Behaviors

Configuring Checkpoints
For a checkpoint to affect your flow, you must associate it with a flow change or report that
you want to run before, after, or in place of the code the checkpoint enwraps.
The process of defining flow changes and reports and associating them with individual
checkpoints is described in the following topics:
 • Defining Checkpoint Behaviors
• Associating Checkpoints and Checkpoint Behaviors

Defining Checkpoint Behaviors

You can define two types of checkpoint behaviors: reports and actions. Define a
checkpoint report to generate one or more reports supported by the tool or custom reports
you create yourself. Define a checkpoint action to execute any kind of flow change before,
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after, or in place of the code block enwrapped by a checkpoint. For example, you might set
an application option to a specific value before a particular checkpoint.
Define these behaviors in your checkpoint.config.tcl file, which is automatically sourced by
the checkpoint system.
Defining Checkpoint Reports
To define a checkpoint report, use the create_checkpoint_report command in
your checkpoint.config.tcl file. Specify a unique name for the report and define the Tcl
commands to generate the report.
The following example defines a checkpoint report named timing, which writes the output
of the report_qor and report_timing commands to disk:
create_checkpoint_report timing {
set name [get_current_checkpoint -name]
set pos [get_current_checkpoint -position]

report_qor -nosplit > ./checkpoint/$name.$pos.qor.rpt

report_qor -summary -nosplit >> ./checkpoint/$name.$pos.qor.rpt

report_timing -nosplit -max_paths 10 \

> ./checkpoint/$name.$pos.path.rpt
}

Notice the use of the get_current_checkpoint command with the -name and
-position options to give the generated reports a meaningful name. When these
reports are generated, their names reflect the checkpoint that triggered them
(get_current_checkpoint -name), as well as whether they were generated before
or after the checkpoint (get_current_checkpoint -position). For example, if this
checkpoint report is executed after a checkpoint named checkpoint_A, the generated
reports are saved to the checkpoint directory, and the name of the QoR report is
checkpoint_A.after.qor.rpt.
The next example defines a checkpoint report named app_options, which writes all your
non-default application options to disk:
 create_checkpoint_report app_options {
set name [get_current_checkpoint -name]
set pos [get_current_checkpoint -position]

report_app_options -non_default \
> ./checkpoint/$name.$pos.app_options.rpt
}

Defining Checkpoint Actions

To define a checkpoint action, use the create_checkpoint_action command in
your checkpoint.config.tcl file. Specify a unique name for the action and define the Tcl
commands that constitute the action.
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The following example defines a checkpoint action named gropto, which enables global
route based buffering:
create_checkpoint_action gropto {
set_app_options -name place_opt.initial_drc.global_route_based \
-value true
}

The next example defines a checkpoint action named placer_high_effort_cong, which runs
high-effort congestion reduction:
create_checkpoint_action placer_high_effort_cong {
set placer_command [get_current_checkpoint -script]
set cong_option "-congestion_effort high"
eval $placer_command $cong_option
}

Notice the use of the get_current_checkpoint -script command and option, which
retrieves the command originally enwrapped by the checkpoint and sets its congestion
effort to high (-congestion_effort high). The -script option is typically used to
define actions that replace the contents of a command. In this example, the action
modifies the -congestion_effort option of the command that is enwrapped by the
checkpoint associated with this action.

Associating Checkpoints and Checkpoint Behaviors

After defining checkpoints with the eval_checkpoint command and checkpoint
behaviors with the create_checkpoint_* command, you must associate the two so that
the tool executes the behaviors when it encounters the checkpoints in a run, as described
in the following topics:
• Associating Checkpoints With Checkpoint Reports
• Associating Checkpoints With Checkpoint Actions
 See Also
• Defining Checkpoints
• Defining Checkpoint Behaviors
Associating Checkpoints With Checkpoint Reports
To associate a checkpoint report with one or more checkpoints, use the
associate_checkpoint_report command in your checkpoint.config.tcl
file.
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• Specify the checkpoint report name with the

-enable option.
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• To enable the report to run before one or more checkpoints, specify the checkpoint
names with the -before option.
• To enable the report to run after one or more checkpoints, specify the checkpoint
names with the -after option.
When associating a report with multiple checkpoints, you can list the checkpoint names or
specify the asterisk wildcard character.
Assume you have defined three checkpoints in your script named remove_buffers,
place_opt_to_initial_opto, and place_opt_to_final_opto using the eval_checkpoint
command, and two checkpoint reports named timing and app_options using the
create_checkpoint_report command.

To enable your timing report to run after the place_opt_to_initial_opto and

place_opt_to_final_opto checkpoints, use the following command:
associate_checkpoint_report -enable timing \
-after { place_opt_to_initial_opto place_opt_to_final_opto }

To enable your app_options report to run before all the checkpoints in your script, use the
following command:
associate_checkpoint_report -enable app_options -before *

You can also add the command like this, which enables the report to run before the
remove_buffers checkpoint and any checkpoints beginning with the phrase
place_opt:
associate_checkpoint_report -enable app_options -before remove_buffers
 place_opt*

The following is a portion of your checkpointed script showing what happens when the
script runs. Note that the highlighted code is not actually in your script, but shows the
checkpoint behaviors that are executed when the tool encounters the checkpoints in the
run.
• The code that is commented out identifies the original script body
• The blue code identifies the checkpointed Tcl commands in your golden flow
• The green code identifies the app_options report, configured to run before each
checkpoint
• The purple code identifies the timing report, configured to run after the
place_opt_to_final_opto checkpoint
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Associating Checkpoints With Checkpoint Actions

To associate a checkpoint action with one or more checkpoints, use the
associate_checkpoint_action command in your checkpoint.config.tcl

file. • Specify the checkpoint action name with the-enable option.

• To enable the action to run before one or more checkpoints, specify the checkpoint
names with the -before option.
• To enable the action to run after one or more checkpoints, specify the checkpoint
names with the -after option.
• To enable the action to run instead of the code block enwrapped by the checkpoint,
 specify the checkpoint names with the -replace option.
When associating an action with multiple checkpoints, you can list the checkpoint names
or specify the asterisk wildcard character.
Assume you have defined two checkpoints in your script named place_opt_to_initial_drc
and incr_placement with the eval_checkpoint command, and two checkpoint actions
named gropto and placer_high_effort_cong with the create_checkpoint_action
command.
To enable your gropto action to run before the place_opt_to_initial_drc checkpoint, use the
following command:
associate_checkpoint_action -enable gropto \
-before place_opt_to_initial_drc
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To enable your placer_high_effort_cong action to run instead of the code block enwrapped
by the incr_placement checkpoint, use the following command:
associate_checkpoint_action -enable placer_high_effort_cong \
-replace incr_placement

The following is a portion of your checkpointed script showing what happens when the
script runs. Note that the highlighted code is not actually in your script, but shows the
checkpoint behaviors that are executed when the tool encounters the checkpoints in a run.
• The code that is commented out identifies the original script body
• The blue code identifies the checkpointed Tcl commands in your golden flow
• The green code identifies the gropto action, configured to run before the
place_opt_to_initial_drc checkpoint
• The purple code identifies the placer_high_effort_cong action, configured to run in
place of the code block enwrapped by the incr_placement checkpoint
 Adding Changes to a Script With Checkpoints

Associating a Checkpoint With Multiple

Behaviors
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When you associate a checkpoint with multiple behaviors, the tool executes those
behaviors in the following order:
• Any reports configured to run before the checkpoint
• Any actions configured to run before the checkpoint
• The checkpointed code block, or any actions configured to replace it
• Any actions configured to run after the checkpoint

• Any reports configured to run after the checkpoint

If multiple reports or multiple actions are configured to run at the same position (-before,
-after, or -replace) in the same checkpoint, the tool executes them in the order in which
they were associated with the checkpoint with the associate_checkpoint_* commands.
For example, suppose you define a timing report before an area report. If you associate
the area report to run after a checkpoint before you associate the timing report to run after
the same checkpoint, the tool runs the area report first when it encounters the checkpoint.
 See Also
• Defining Checkpoints
• Defining Checkpoint Behaviors
• Querying Checkpoints and Checkpoint Behaviors

Querying Checkpoints and Checkpoint Behaviors

To return a list of all the checkpoints or checkpoint behaviors in the current session,
or to return detailed information for any checkpoint or checkpoint behavior, use the
get_checkpoint_data command.

• To return a list of all the checkpoints that have been executed, specify the
-list_names option:

fc_shell> get_checkpoint_data -list_names

remove_buffers place_opt_to_initial_drc
incr_placement place_opt_to_initial_opto
place_opt_to_final_opto

• To return detailed information for a checkpoint, specify the checkpoint with the -name
option. The tool returns the output as a Tcl dictionary:
fc_shell> get_checkpoint_data -name place_opt_to_initial_drc
memory 173.85 start_time 2.34 end_time 2.34 before_runtime 2.34
before_report_runtime 0.00 after_report_runtime 0.00 self_runtime

0.00 before_reports {} after_reports {

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before_actions {gropto} after_actions
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• To return a list of all the checkpoint behaviors defined in your configuration, specify the
-list_reports or -list_actions option:

fc_shell> get_checkpoint_data -list_reports

timing app_options

fc_shell> get_checkpoint_data -list_actions

gropto placer_high_effort_congestion

• To return the contents and associations of a checkpoint report or action, specify the
report or action with the -report or -action option:
fc_shell> get_checkpoint_data -report app_options
contents {
set name [get_current_checkpoint -name]
 set pos [get_current_checkpoint -position]

report_app_options -non_default \
> ./checkpoint/$name.$pos.app_options.rpt
} before_patterns {*} after_patterns {}

See Also
• Viewing Your Checkpoint History

Viewing Your Checkpoint History

To view your checkpoint history, navigate to the checkpoint directory. This directory
contains a checkpoint_history.rpt file that captures the history of the checkpoints the
tool encounters during each run, along with the runtime and memory usage for each
checkpoint. The checkpoint directory also contains any checkpoint reports you have
written to it.
In some cases, you might want to clear the full or partial contents of your checkpoint
history. A typical example is when a checkpointed run fails and you want to clear some or
all of the data associated with that run, depending on whether you plan to rerun a portion
of the flow or the entire flow.
• To clear your full checkpoint history, use the reset_checkpoints
command. fc_shell> reset_checkpoints

The reset_checkpoints command clears the full contents of the checkpoint

directory, including any reports you have written to it. However, before clearing the
checkpoint directory, the reset_checkpoints command saves a timestamped copy
of the directory in your run directory.
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• To clear a portion of the data in your checkpoint_history.rpt file, use the -from option to
specify the name of a checkpoint.
This option removes all checkpoints including and following the specified checkpoint
from your checkpoint_history.rpt file; it does not remove any checkpoint reports you
have written to the checkpoint directory.
For example, suppose your checkpoint_history.rpt file contains the following data after
your run a full checkpointed flow:
Checkpoints Memory StartTime ...
remove_buffers 32290.86 2020-03-23_14:34:17 ...
place_opt_to_initial_drc 36389.15 2020-03-23_17:21:56 ...
incr_placement 37002.09 2020-03-23_19:13:02 ...
place_opt_to_initial_opto 45655.59 2020-03-23_23:44:36 ...
place_opt_to_final_opto 46322.34 2020-03-23_30:12:55 ...
 Suppose you want to rerun your flow beginning with incremental placement. To clear
the last three checkpoints from your checkpoint_history.rpt file before rerunning that
portion of your flow, use the following command:
fc_shell> reset_checkpoints -from incr_placement

After clearing the checkpoints, your checkpoint_history.rpt file lists only the first two
checkpoints in your flow:
Checkpoints Memory StartTime ...
remove_buffers 32290.86 2020-03-23_14:34:17 ...
place_opt_to_initial_drc 36389.15 2020-03-23_17:21:56 ...

Similarly, the get_checkpoint_data -list_names command returns only

the remove_buffers and place_opt_to_initial_drc checkpoints:
fc_shell> get_checkpoint_data -list_names
remove_buffers place_opt_to_initial_drc

Using Setup Files

When you start the Fusion Compiler tool, it automatically executes the commands in
the .synopsys_fc.setup file.
The tool looks for this file both in your home directory and in the project directory (the
current working directory in which you start the Fusion Compiler tool). The file is read in
the following order:
1. The .synopsys_fc.setup file in your home directory
2. The .synopsys_fc.setup file in the project directory
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The setup files can contain commands that perform basic tasks, such as initializing
application options and setting GUI options. You can add commands and Tcl procedures to
the setup files in your home and project directories. For example,
• To set application options that define your Fusion Compiler working environment,
create setup files in your home directory.
• To set project- or block-specific application options that affect the processing of a block,
create a setup file in the design directory.

See Also
• Working With the 3DIC Compiler User Interfaces
• Using Application Options
 • Using Variables
• Using Tcl Scripts

Using the Command Log File

The command log file records the commands processed by the Fusion Compiler tool,
including setup file commands and application option settings. By default, the Fusion
Compiler tool writes the command log to a file named fc_command.log in the directory
from which you invoked fc_shell.
You can change the name of the command log file by setting the sh_command_log_file
variable in your .synopsys_fc.setup file. You should make any changes to this variable
before you start the Fusion Compiler tool. If your user-defined or project-specific setup
file does not contain this variable, the Fusion Compiler tool automatically creates the
fc_command.log file.
Each Fusion Compiler session overwrites the command log file. To save a command log
file, move it or rename it. You can use the command log file to
• Produce a script for a particular implementation strategy
• Record the physical implementation process
• Document any problems you are having

Enabling Multicore Processing

Several functions in the Fusion Compiler tool support multicore processing, whether
through multithreading, distributed processing, or parallel command execution. Multicore
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processing improves turnaround time by performing tasks in parallel much more quickly
than if they were run sequentially on a single core.
Note:
A single machine has one or more CPUs and each CPU has one or more
cores. The total number of cores available for processing on a machine is the
number of CPUs multiplied by the number of cores in each CPU.
When using multicore processing, you need one Fusion Compiler license for every 16
parallel tasks. For example, to run 17 parallel tasks, you need 2 Fusion Compiler
licenses.
In most cases, you configure multicore processing by using the set_host_options
 command. The following topics describe how to use the set_host_options command
to configure multicore processing:
• Configuring Multithreading
• Configuring Distributed Processing
• Reporting Multicore Configurations
• Removing Multicore Configurations
The following topic describes how to use distributed processing to run the same task on
several blocks in a hierarchical design:
• Running Tasks in Parallel
The following topic describes how to use parallel command execution for checking and
reporting commands:
• Running Commands in Parallel on Your Local Host

Configuring Multithreading
Multithreading performs tasks in parallel by using multiple cores on the same machine,
using a single process memory image. When using multithreading, each parallel task is
called a thread. For the best performance during multithreading, you should limit the
number of threads to the number of available cores, which is the number of CPUs in the
machine times the number of cores per CPU.
The following commands support multithreading configured by the set_host_options
command:
• place_opt
• clock_opt
place.legalize.enable_advanced_legalize
r application option to true.

• insert_via_ladders
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route_detail, and route_eco Note:
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Enabling Multicore Processing When you run routing with a single thread, the
result is deterministic; if
Feedback
• check_legality, when advanced legalization
is enabled by setting the
 you start with the same block, you always get the same result. However, if
you use multiple threads, the routing results are not deterministic; the final
routing is slightly different between runs due to the varying division of tasks
between threads. Global routing supports a deterministic mode for multicore
routing. To enable this mode, set the route.global.deterministic
application option to on.
• route_opt
• signoff_check_drc
• signoff_fix_drc
• signoff_create_metal_fill
• signoff_fix_isolated_via
• write_def
By default, all commands use a single thread. To enable multithreading for those
commands that support it, set the -max_cores option of the set_host_options
command to a value greater than one and less than or equal to the number of cores
available on your machine, which is the number of CPUs in the machine times the number
of cores per CPU. The number of cores specified by the -max_cores option applies to all
commands that support multithreading.
When you enable multithreading, multithreaded commands create and use the specified
number of threads, even if the number is more than the number of available cores. You
must set an appropriate number of threads, so that the command does not try to use
more resources than it has. Overthreading can reduce performance because the extra
threads compete for resources. For best performance, do not run more than one thread
per available core.
For example, if your machine has two CPUs and each CPU has three cores, specify six as
the maximum number of threads:
fc_shell> set_host_options -max_cores 6
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 Processing
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Configuring Distributed

Distributed processing performs tasks in parallel by using multiple machines; each process
uses its own process memory image. When using distributed processing, each parallel
task is called a process. For the best performance during distributed processing, you
should limit the number of processes to the number of available cores, which is the sum of
the number CPUs times the number of cores per CPU for each host machine.
The following commands support distributed processing configured by the
set_host_options command:

• analyze_rail
• create_placement -floorplan
• signoff_check_drc
• signoff_fix_drc
• signoff_create_metal_fill
• signoff_fix_isolated_via
When you configure distributed processing, you can specify one or more of the following
settings:
• The job submission command (the -submit_command option)
If you do not specify this option, the tool uses the rsh command to submit the
parallel processes.
• The list of host machines (the host_names argument)
• The maximum number of processes (the -num_processes option)
By default, the tool assigns a name to each configuration you define with the
set_host_options command. To specify the configuration name, use the -name
option. You use the configuration name to select the configuration to use for specific
commands and to remove a configuration.
For example, to specify a distributed processing configuration that uses the qsub
command to submit the parallel processes, use the following command:
fc_shell> set_host_options -name dp_config \
-submit_command [list qsub -P bnormal -cwd]

Reporting Multicore Configurations

To report the values set by the set_host_options command, use
 the report_host_options command.
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Removing Multicore Configurations

To remove the multicore configurations defined by the set_host_options command,
use the remove_host_options command. To remove all multicore configurations, use
the -all option. To remove a specific multicore configuration, specify the configuration
name with the -name option.
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Running Tasks in Parallel

To efficiently run the same task on several blocks in your design, you can use the
run_block_script command to enable distributed processing and perform the
tasks in parallel. The run_block_script command accepts a Tcl script and applies
the commands in the script to the blocks you specify.
For example, to compile the subblocks of a design in parallel in a hierarchical
flow, 1. Write the script to run on the blocks in the design.

The following example performs the steps necessary to compile each subblock in the
design. You can add additional commands to the script as needed to perform other
operations.
open_lib $block_libfilename
open_block $block_refname.design
commit_upf
set_editability -from_level 1 -value false
compile_fusion -from initial_map -to initial_map
create_abstract -read_only
create_frame
save_block $block_refname -as $block_refname/initial_map
compile_fusion -from logic_opto -to logic_opto
create_abstract -read_only
create_frame
save_block $block_refname -as $block_refname/logical_opt
compile_fusion -from initial_place -to initial_place
create_abstract -read_only
create_frame
save_block $block_refname -as $block_refname/initial_place
save_block
save_lib
close_block -force -purge
close_lib

2. Run the run_block_script command to process each block in parallel by using

the script created in step 1.
The following example specifies the settings for distributed processing with the
set_host_options command and runs the block_synthesis.tcl synthesis script on
the subblocks in parallel by using the Load Sharing Facility (LSF). The command
writes data and log files to the my_work_dir directory.
fc_shell> set block_list [get_attribute \
[get_cells -hierarchical -filter "is_soft_macro==true" \
ref_full_name]
fc_shell> set block_list [lsort -unique $block_list]
fc_shell> set_host_options -name myhost -submit_command "sh"
fc_shell> run_block_script \
-host_options myhost \
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-work_dir my_work_dir
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Enabling Multicore Processing

To control the order in which blocks are processed, use the -run_order option with the
top_down or bottom-up argument. When you specify the -run_order top-down
option, the tool delays processing for a child block until all parent blocks for the child
block are processed. When you specify the -run_order bottom-up option, the tool
begins by processing the child blocks, then processes the parent blocks. By default,
blocks are processed in a bottom-up order.

Running Commands in Parallel on Your Local Host

You can improve runtime by running checking and reporting commands in parallel on
your local host. You can run the commands either in the background (with the redirect
-bg command) or in the foreground (with the parallel_execute command). These
techniques do not require the use of additional licenses beyond the licenses required for
the parent run. They also do not require you to use or configure distributed processing.
When you use these techniques, consider the following guidelines:
• To reduce runtime and memory usage, run the update_timing command before
running the commands in parallel; otherwise, each command that requires updated
timing runs the update_timing command independently.
• To pass variables from a child process to the parent process, you must write the
contents of the variables to a file during the child process, and then read that file in the
parent process.

See Also
• Running Commands in the Background
• Running Commands in Parallel

Running Commands in the Background

To improve runtime, you can run checking and reporting commands in the background
while you run other commands in the foreground. This is useful in interactive sessions
when you want to continue your work while the tool generates a report.
To run commands in the background, use the redirect command with the -bg option.
When you use this command, fc_shell returns immediately to execute the next command.
If you issue an exit command in the parent process, the tool waits for all
 redirect -bg commands to complete before exiting.
To list the commands supported by the redirect -bg command, use the
list_commands -bg command. You can run either a single command or source a Tcl
script that contains
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69 Feedback

only supported commands. If the command or script includes a redirect -bg

command, the -bg option is ignored.
You can run at most two jobs in the background. If you specify more than two background
jobs, they are queued.
To specify the maximum number of cores to use for the background jobs, use the
-max_cores option with the redirect command. The number of cores available
for the parent process (as specified by the -max_cores option of the
set_host_options command) is reduced by the number of cores allocated for
background jobs.
The following example redirects a Tcl script to run in the background:
fc_shell> set_host_options -max_cores 8
fc_shell> redirect -bg -max_cores 3 -file bg_log.out \
{source bg_script.tcl}
Information: redirect -bg with max_cores 3 started. The maximum number of
cores available in parent is reduced to 5. (BGE-004)

Reporting Background Jobs

To report the background jobs submitted with the redirect -bg command, use the
report_background_jobs command. This command reports both the completed jobs
and the jobs currently running in the background, as shown in the following example:
fc_shell> report_background_jobs
JOB 'redirect -bg -file {background.log} source bg_script.tcl
-max_cores 4 ' completed
JOB(pid:13010) 'redirect -bg -file {background_1.log}
source bg_script_1.tcl -max_cores 3 ' is running

To omit the completed jobs, use the -reset option with the
report_background_jobs command.

Running Commands in Parallel

To improve runtime, you can run checking and reporting commands in parallel and return
to the parent process after the longest running command in the parallel execution list
completes. This is useful in batch scripts.
To run commands in parallel, use the parallel_execute command, as shown in
the following example:
 fc_shell> update_timing
fc_shell> parallel_execute {
report_cmd1 log_file1
report_cmd2 log_file2
report_cmd3 log_file3
...
}

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To list the supported commands, use the -list_allowed_commands option with

the parallel_execute command.
To specify the maximum number of cores to use when running the parallel_execute
command, use the -max_cores option. If you do not use this option, the tool uses the
value of the -max_cores option from the set_host_options command. If you do not
specify the maximum number of cores with either command, the tool runs the commands
sequentially instead of in parallel.
To run commands in parallel as a background job, use the redirect -bg command to
run the parallel_execute command, as shown in the following example:
fc_shell> redirect -bg -max_cores 3 -file bg_log.out {
parallel_execute {
report_cmd1 log_file1
report_cmd2 log_file2
}
}
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2
Preparing the Design
The Fusion Compiler tool uses a design library to store your design and its associated
library information. This topic describes how to create a design library and how to prepare
and save your design.
These steps are explained in the following topics:
• Defining the Search Path
• Setting Up Libraries
 • Using Pin Access Checker Utility
• Analyzing Libraries
• Reading the Design
• Mitigating Design Mismatches
• Importing the Floorplan Information
• Setting Up Multivoltage Designs
• Specifying Timing Constraints and Settings
• Specifying Logical Design Rule Constraints
• Specifying Clock Gating Constraints
• Specifying Physical Constraints for Placement and Legalization
• Specifying Placement Settings
• Specifying Legalization Settings
• Controlling the Optimization of Cells, Nets, Pins, and Ports
• Specifying Settings for Preroute Optimization
• Setting Up for Power-Related Features
• Specifying the Routing Resources
Check Manager • Applying Mega-Switch
Command Settings

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72 Defining the Search Path
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Chapter 2: Preparing the Design
Defining the Search Path

• Handling Design Data Using the Early Data

The Fusion Compiler tool uses a search path to look for files that are specified with a
relative path or with no path.
To specify the search path, use the set_app_var command to set the
 search_path application variable to the list of directories, in order, in which to look
for files. When the tool looks for a file, it starts searching in the leftmost directory
specified in the search_path variable and uses the first matching file it finds.
You can also use the Tcl lappend command to add your directories to the default
search path, which is the directory from which you invoked the tool. For example,
fc_shell> lappend search_path ./mylibdir

Setting Up Libraries
A block is a container for physical and functional design data. A design library is a
collection of related blocks, together with technology data that applies to the block
collection. A chip design consists of one or more blocks, often stored in different design
libraries. A design library uses instances of blocks defined in lower-level libraries, called
reference libraries. A design library can serve as a reference library for another design
library.
To learn about setting up libraries, see the following topics:
• Working With Design Libraries
• Setting Up Reference Libraries
• Library Configuration
• Restricting Library Cell Usage
• Restricting the Target Libraries Used
• Specifying Library Subset Restrictions
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Working With Design Libraries

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You can create, open, query, save, or close a design library, using an absolute path, a
relative path, or no path, by using the following commands:
• create_lib
This command creates the library in memory and sets it as the current library. When
you run this command to create a new design library, you must specify the library
name. Slash (/) and colon (:) characters are not allowed in library names. The following
command creates the my_libA library using a relative path:
 fc_shell> create_lib ../my_lib_dir/my_libA
{my_libA}

• open_lib
This command opens the specified library, makes that library the current library, and
opens all its associated reference libraries. Opening a library means loading it into
memory and making its blocks accessible. The following example opens the my_libA
library saved on disk:
fc_shell> open_lib my_libA
Information: Loading library file '/usr/lib/StdCells.ndm' (FILE-007)
Information: Loading library file '/usr/lib/RAMs.ndm' (FILE-007)
Information: Loading library file
'/usr/lib/PhysicalOnly.ndm' (FILE-007)
{my_libA}

• current_lib
By default, the library most recently opened is the current library. You can explicitly
set any open library to be the current library by using the current_lib command.
For example,
fc_shell> current_lib my_libA
{my_libA}

• save_lib
When you create or change a library, the changes are stored in memory only. To save
a library to disk, use this command. For example,
fc_shell> save_lib lib_A
Saving library 'lib_A'
1

• close_lib
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When you no longer need access to data in a library, you can close it by using the
close_lib command. Be sure to save the changes in the library before you close
it. For example,
fc_shell> close_lib
Closing library 'lib_A'
1

In addition, you can use the current_lib, get_libs, and report_lib commands
to query design libraries.
For more information, see the Design Libraries topic in the Fusion Compiler Data Model
 User Guide.

Setting Up Reference Libraries

You can specify a reference library list for a design library when you create the design
library by using the -ref_libs option of the create_lib command. You can also
change the reference library list at any time by using the set_ref_libs command.
Use the following commands to specify, rebind, and report reference
libraries: • create_lib -ref_libs

You can specify a relationship between a new design library and its lower-level
reference libraries by using the create_lib command. For example,
fc_shell> create_lib lib_B \
-ref_libs {../LIBS/lib_c ../STND/stdhvt.ndm} ...
{lib_B}

• set_ref_libs -ref_libs
For an existing design library, open the library and then use the set_ref_libs
command to specify the reference libraries. For example,
fc_shell> current_lib
{lib_B}
fc_shell> set_ref_libs \
-ref_libs {../LIBS/lib_C ../STND/stdhvt.ndm}
../LIBS/lib_C ../STND/stdhvt.ndm

• report_ref_libs
To report the reference libraries of a design library, use the report_ref_libs
command.

For example,
fc_shell> create_lib lib_A -ref_libs \
{../libs/SCLL.ndm ../libs/SCHH.ndm
../BLOCKS/MACROS} {lib_A}
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fc_shell> report_ref_libs...
75
Name Path Location
Chapter 2: Preparing the Design Feedback
Setting Up Libraries

---------------------------------------------------------------
*+ SCLL ../libs/SCLL.ndm /remote/project/libs/SCLL.ndm
 *+ SCHH ../libs/SCHH.ndm /remote/project/libs/SCHH.ndm
* MACROS ../BLOCKS/MACROS /remote/project/BLOCKS/MACROS
"*" = Library currently open
"+" = Library has technology information

• set_ref_libs -rebind
When you make a change that invalidates the reference library list, such as moving a
reference library to a new location, you need to rebind the reference libraries. To do
so, use the -rebind option, which rebinds each reference library path specified by
the search_path variable to libraries that are currently loaded in memory. For
example,
fc_shell> current_lib
{lib_A}
fc_shell> set_app_var search_path {. ../REFLIBS ../CLIBS}
. ../LIBS ../BLOCKs
fc_shell> set_ref_libs -rebind
../REFLIBS/lib_C ../REFLIBS/lib_D ../CLIBS/stdhvt.ndm}

Rebinding a library does not affect the bindings of blocks already existing in the design
library. To rebind these blocks using an updated reference library list, use the -rebind
option with the link_block command.

Library Configuration
Library configuration allows you to specify which vendor libraries to use as reference
libraries for the current design. You specify the technology file, physical libraries, and logic
libraries by using the search_path and link_library variables, and then you use the
create_lib or set_ref_libs command to assemble the cell libraries.
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During library configuration,

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• The Fusion Compiler tool automatically calls the Library Manager tool without user
intervention to generate cell libraries, as shown in the following figure:

ASCII
.db files
 .frame files
technology
file

Cell

libraries Synthesis

• The tool saves the generated cell libraries to disk and adds them to the reference
library list of the design library.
• These cell libraries are the same as when the cell libraries are created during library
preparation in the Library Manager tool.
For more information, see the Configuring Cell Libraries topic in the Fusion Compiler Data
Model User Guide.

Restricting Library Cell Usage

By default, the Fusion Compiler tool can use all of the library cells available in the cell
libraries when performing optimization or clock tree synthesis on the block. To restrict the
cell usage, use the set_lib_cell_purpose command after the block is in memory. The
command has a block scope and is persistent across tool sessions. The specified settings
are restored when the block is reopened.
To specify how the tool can or cannot use library cells, use the -include and
-exclude options with the set_lib_cell_purpose command. Both of these options
accept one or more of the following values: all, cts, hold, optimization, none.
• The -include option sets the included_purposes attribute on the specified
library cells.
• The -exclude option sets the excluded_purposes attribute on the specified
library cells.
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If a library cell has a dont_use attribute, it is excluded from all uses, which is
 the same as if you specified set_lib_cell_purpose -include none for
that cell.
When the tool performs optimization, which includes setup, hold, and logical DRC fixing,
it can use library cells that have an included purpose of optimization, hold, or both.
When the tool performs clock tree synthesis, it can use library cells that have an included
purpose of cts.
For example, to disallow the use of a set of library cells for all uses, use the following
command:
fc_shell> set_lib_cell_purpose -include none lib_cells

To allow a set of library cells to be used only for clock tree synthesis, use the following
commands:
fc_shell> set_lib_cell_purpose -include none lib_cells
fc_shell> set_lib_cell_purpose -include cts lib_cells

To allow a set of library cells to be used for all uses except clock tree synthesis, use the
following command:
fc_shell> set_lib_cell_purpose -exclude cts lib_cells

To use the asterisk wildcard character (*) to query a collection of cells, you must use the
get_lib_cells command. However, the set_lib_cell_purpose command
excludes synthetic modules by default. Therefore, you should use the
set_synlib_dont_use command to exclude synthetic modules. For example,

fc_shell> set_lib_cell_purpose \
-include none [get_lib_cells */*01_*_AB]
Warning: The 'set_lib_cell_purpose' command cannot be used on synthetic
library cell 'standard:*OPMOD.DW01_ADD_AB.timing'. (NDMUI-511) 0

Restricting the Target Libraries Used

By default, the tool can select any library cell from the target library during optimization. In
some cases, you might want to restrict the library cells used for clock tree synthesis and
optimization. For example, you might want to exclude specific double-height cells from the
target library for some design blocks during optimization.
To restrict the library cells used for clock tree synthesis and optimization, 1. Specify
the library subset by using the set_target_library_subset command. By
default, the library subset restriction applies to

To set it for a specific subblock, use the

Fusion Compiler™ User Guide V-2023.12-SP3 -objects option.
78
◦ Both clock and data paths.
Chapter 2: Preparing the Design
Setting Up Libraries To set it for only the clock or data paths, use the
-clock or -data option. You can further
◦ The top block and all its subblocks
restrict the target library subset setting as Feedback

follows:

◦ Specify a list of cells from the libraries that should not be used by using the
-dont_use option.

◦ Specify that these libraries cannot be used for any other objects, other than the
specified objects, by using the -only_here option.
2. Enable the use of the target library subset by setting the
opt.common.enable_target_library_subset_opt application option to

1. When you set target library subsets, remember the following points:

• The subset restriction applies to hierarchical cells but not to leaf cells.
• The command enforces the subset restriction on the specified blocks and their
subdesigns in the hierarchy, except those subdesigns where a different subset
restriction is set.
• A subset specified at a lower level supersedes any subset specified at a higher level.

Figure 7 Logic Hierarchy of Design

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Libraries

For example, assume your design has a logic hierarchy as shown in Figure 7and you
want to implement the following library restrictions during optimization and clock tree
synthesis:
• Use only the cells from the library named LVT_lib for the Sub1 block and its subblocks,
SubA and SubB.
• Do not use the cells from this library anywhere else in the design.
To do so, use the following settings:
fc_shell> set_target_library_subset -objects {top/Sub1} \
-only_here [get_lib_cells LVT_lib/*] [get_libs LVT_lib]
fc_shell> set_app_options \
-name opt.common.enable_target_library_subset_opt -value 1

In addition to these settings, assume you specify the following setting:

fc_shell> set_lib_cell_purpose -include cts \

{HVT_lib/buf1 HVT_lib/buf2 LVT_lib/buf1 LVT_lib/buf2} Then, when

adding buffers on the clock network during clock tree synthesis, the tool uses

• The buf1 and buf2 cells from the LVT_lib library for the block named Sub1 and its
subblocks
• The buf1 and buf2 cells from the HVT_lib library for the rest of the design
Reporting Target Library Subsets

To find out which target library subsets have been defined for a top block or hierarchical
cell, use the report_target_library_subset command.
Reports that are generated by reporting commands, such as report_cells and
report_timing, show the td attribute attached to the cells that are specified by
the -dont_use or -only_here option.
Removing Target Library Subsets
To remove a target library subset restriction from a top block or hierarchical cell, use the
 remove_target_library_subset command.

Specifying Library Subset Restrictions

You can restrict the mapping and optimization of sequential cells and instantiated
combinational cells to a subset of reference libraries and library cells. To specify one or
more library subset restrictions, use the define_libcell_subset command followed
by the set_libcell_subset command.

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