Vel Tech Rangarajan Dr.

Sagunthala R&D Institute of Science and Technology

(Deemed to be University Estd. u/s 3 of UGC Act, 1956)
School of Computing
VTR UGE 2021- (CBCS)
B.Tech. – Computer Science and Engineering
Academic Year: 2024 - 25

Course Category : Program Core

Course Code / Title : 10211CS109/Microprocessor and Microcontroller
Semester : Winter Semester 2024-2025
Unit – I
Two Mark questions
1. Classify the types of computers.
Based on Size and Capability
Supercomputers, Mainframe Computers, Minicomputers (Mid-range Computers),
Microcomputers (Personal Computers)

2. List the different general-purpose registers utilized in a processor’s operations.

Accumulator (AX) Register, Base (BX) Register, Count (CX) Register, Data (DX) Register,
Stack Pointer (SP), Base Pointer (BP), Source Index (SI), Destination Index (DI).

3. State the various levels of 8086 programming languages.

Machine Language (Low-level Language), Assembly Language (Low-level Language), High-
Level Languages.

4. What is an assembler?
1.Translation from Assembly Language to Machine Code 2. Symbolic Name Resolution 3. Macro
Expansion 4. Error checking 5. Object code generation 6. Handling directives.

5. How Interrupt service routine handles interrupt in a microprocessor system.

Steps: Interrupt occurs, Interrupt acknowledgement, Interrupt Vector table(IVT) Lookup, Saving
the current state, Jump to the Interrupt Service Routine(ISR), ISR execution, Restoring the
program context(return from interrupt), Interrupt-related flags.

6. Differentiate minimum and maximum mode signals.

Minimum Mode is typically used for single processor systems, where the 8086 microprocessor
generates all control signals, and the system is simpler.
Maximum Mode is used for multiprocessor or complex systems, where an external bus controller
(8288) generates and manages the control signals, facilitating the coordination between
processors and peripherals.

7. What do you mean by Pipelining?

Pipelining in the 8086 microprocessor refers to the technique used to increase the throughput of
the processor by overlapping the execution of multiple instructions. Stages involved are
instruction fetch, decode, execute and writeback.
8. List the different buses of 8086 microprocessor.
 The 8086 microprocessor has three main types of buses that handle the movement of data,
addresses, and control signals between the microprocessor and other components (such as
memory and I/O devices). These buses are: Data Bus, Address Bus and Control Bus.

9. Find the physical address when the respective content of CS and IP register are 34BA and
4214.

10. Articulate the distinctions between a microprocessor and a microcontroller.

Microprocessors are designed for general-purpose computing with higher performance and
flexibility, making them suitable for systems that require high computational power.
Microcontrollers, on the other hand, are optimized for embedded control applications, where low
power consumption, simplicity, and cost-effectiveness are prioritized. They integrate the CPU,
memory, and peripherals on a single chip, making them ideal for specific control tasks.

11. List few real time applications of microprocessor.

Real-Time Applications of Microprocessors: Personal Computers, Industrial Automation,
Automotive Systems, Consumer Electronics, Medical equipment, Telecommunications,
Aerospace and Avionics, Smart Home Automation, Gaming Consoles, Flight Simulators,
Security Systems and Military Systems.

12. What are physical and logical address in 8086?

The physical address is the actual memory location in physical memory (RAM) and is calculated
by adding the segment address (shifted by 4 bits) to the offset.
The logical address is a combination of a segment and an offset used by the CPU to generate
memory locations within a segment.

13. Explain the data and address size in 8086 microprocessor.

The 8086 microprocessor operates with 16-bit data, processing data in 16-bit chunks, though it
also supports 8-bit data.
The address size of the 8086 is 20 bits, allowing it to access up to 1MB of memory. The logical
address used by the processor is computed from the combination of a 16-bit segment and a 16-bit
offset, which is then translated into a physical address.

14. Define troubleshooting in 8086 microprocessor.

Troubleshooting in the 8086 microprocessor involves diagnosing and resolving issues related to
both hardware and software components. It requires a systematic approach, including identifying
symptoms, checking key components like memory and I/O, using diagnostic tools, and debugging
code. By carefully isolating the problem, one can restore the 8086 microprocessor-based system
to full functionality.

15. Interpolate assembler directive management in memory allocation.

In the 8086 microprocessor, assembler directives are used to organize, allocate, and manage
memory in a structured way. These directives assist in:
 Defining memory segments (CODE, DATA, STACK).
 Reserving memory space for variables and constants using directives like DB, DW, DD,
RESB, RESW, and RESD.
 Initializing constants using EQU.
  Specifying segment relationships with the ASSUME directive to ensure proper memory
addressing.

Three Marks Questions

1. Explain how advancements in microprocessor technology have shaped modern
computing.
Advancements in microprocessor technology have played a pivotal role in shaping modern
computing by enabling faster, more powerful, and more efficient systems. The development of
microprocessors has driven key innovations in areas such as processing power, energy
efficiency, miniaturization, and system integration.
(2 Marks)
1. Increased Processing Power
2. Miniaturization of Devices
3. Energy Efficiency
4. Parallel Processing and Multicore Designs
5. Integration of Specialized Functions
6. Edge Computing and IoT
7. Security Enhancements
8. Democratization of Technology (1 Mark)
2. Outline the structure of flag register and what does it signify.
Status Flags (Indicate results of operations)
Sign Flag (SF), Zero Flag (ZF), Auxiliary Carry Flag (AF), Parity Flag (PF), Overflow Flag
(OF),
Control Flags (Affect processor operations)
Interrupt Enable Flag (IF), Direction Flag (DF) (2 Marks)
Significance: Indicating Operation Results, Controlling Program Flow, Debugging and
Diagnostics, Error Detection, Optimizing Execution (1 Marks)
3. Discuss the role of assembly language play in the functioning of the microprocessor.
Assembly language plays a crucial role in the functioning of the microprocessor by providing a
low-level programming interface between human-readable instructions and the machine code
that the microprocessor can execute directly. It acts as a bridge, allowing developers to write
code that is efficient, fast, and optimized for the underlying hardware.
(2 Marks)
Also it manages, Direct Hardware Communication, Instruction Set Utilization, Memory
Management, Optimization of Critical Code, Debugging and Diagnostics, Enabling System-
Level Programming, Hardware Abstraction for Developers.

(1 Mark)
4. Distinguish between linker and loader.
 Purpose:
 The linker is responsible for combining code and preparing the executable file.
 The loader ensures the executable file is loaded into memory and ready to execute.
Timing:
 The linker works during the build process (before execution).
 The loader works during the runtime process (just before execution). (1 ½ Marks)
Output:
 The linker produces an executable file.
 The loader ensures the program runs by placing it in memory. (1 ½ Marks)
Library Handling:
 The linker integrates static libraries into the executable or prepares dynamic libraries for
runtime linking.
 The loader dynamically links and loads libraries if needed during execution.
5. Explain the various interruption pins in the 8086 microprocessor and how they are
triggered.
The 8086 microprocessor has five primary interrupt-related pins:
NMI (Non-Maskable Interrupt), INTR (Interrupt Request), INTA (Interrupt Acknowledge),
RESET
HOLD. (2 Marks)
The interrupt system of the 8086 microprocessor allows it to handle external events efficiently
and react promptly to various system conditions. INTR and INT are used for general interrupts,
NMI is for critical, non-maskable interrupts, and RESET ensures that the processor can be
reinitialized. HOLD/HLDA facilitates DMA, enabling faster data transfer without processor
involvement. Together, these interrupt pins provide the microprocessor with flexibility in
managing hardware interactions, critical system errors, and real-time operations.
(1 Mark)
6. Discuss the maximum mode operation using read and write control signals in the 8086
microprocessors.
In the 8086 microprocessor, maximum mode is a specific mode of operation that allows the 8086
to work with external components like memory and I/O devices using additional support chips.
This mode is primarily used for multiprocessor systems or systems with external memory that
require complex control signals. In maximum mode, the 8086 microprocessor needs external
support for generating various control signals, which it cannot generate on its own in this mode.
(2 Marks)
Status Signals (S2, S1, S0), Control Signals Generated by the 8288 Bus Controller, Address
Latch Enable (ALE), Data Transfer Synchronization.
(1 Mark)

7. Dramatize read and write operations using memory and I/O devices.
 8086 microprocessor handles the basic tasks of reading and writing data both to memory and I/O
devices. The process involves precise coordination using the address bus, data bus, and control
signals like ALE, RD, WR, M/IO, and DEN. (1 Mark)
 Memory operations involve fetching or storing data in RAM, with address and data buses
actively involved.
 I/O operations are similar, but the microprocessor interacts with external devices like
sensors, displays, or keyboards using specific I/O ports. (1 Mark)
The Memory Read Operation, the Memory Write Operation, the I/O Read Operation, the I/O
Write Operation. (1 Mark)
8. Interpret the function and importance of the status pins in the 8086 microprocessors.
Function of the Status Pins (S2, S1, and S0): (1 ½ Marks)
The S2, S1, and S0 pins form a 3-bit status code that provides the current state of the processor.
The status code is used primarily to indicate the type of bus cycle or operation being executed
by the 8086, which helps external devices (memory, I/O controllers) determine whether the
operation is related to memory, I/O, or another process.
(1 ½ Marks)
Importance of the Status Pins:
1. Communication with External Devices, 2. Coordination of Data Transfers, 3. Interrupt
Handling, 4. Debugging and Testing, 5.System Efficiency and Control.
9. Illustate the process of troubleshooting in 8086 microprocessors.
Troubleshooting the 8086 microprocessor involves a systematic approach to diagnosing and
resolving issues in its operation.
Define the Problem, Preliminary Checks, Test Hardware Components, Debug Software, Use
Diagnostic Tools, Analyze Timing, Test Communication, Isolate and Rectify the Fault.
(2 Marks)
Importance of Troubleshooting
1. Reliability: Ensures that the 8086 system functions as expected under various conditions.
2. Efficiency: Identifies and resolves bottlenecks or malfunctions that hinder performance.
3. Longevity: Prevents long-term hardware damage and extends the system’s lifespan.
4. Debugging Skills: Enhances understanding of the microprocessor's operation, aiding in
the development of robust systems.
(1 Mark)
10. Explain briefly about END, ENDP and ENDS.
The assembler directives END, ENDP, and ENDS are used to mark the end of certain sections
of code or procedures.
END (End of Program)
(1 Mark)
 Purpose: The END directive marks the end of the entire assembly language program.
ENDP (End of Procedure)
 (1 Mark)
 Purpose: The ENDP directive marks the end of a procedure in the assembly code.
ENDS (End of Segment)
(1 Mark)
 Purpose: The ENDS directive is used to mark the end of a segment in the assembly code.
Five marks Questions
1. Explain the role of microprocessors in electronic world. Discuss how the changes in
microprocessor technology influenced the development of computing over time.
A microprocessor is an integrated circuit (IC) that contains the central processing unit (CPU),
which is responsible for executing instructions and managing the flow of data within a system.
1. The Early Days (1970s - 1980s) (2
Marks)
Key Milestones:
 First Microprocessors (1971): The Intel 4004, released in 1971, was the first
commercially available microprocessor. It was a 4-bit processor capable of executing
simple instructions.
 Introduction of 8-bit Microprocessors (1972 - 1980): The Intel 8080 and the Zilog Z80
(1976) were popular 8-bit processors that spurred the development of personal computers
(PCs), allowing for the first commercial microcomputers.
 Intel 8086 and 8088 (1978-1979): The 8086 was a 16-bit processor and one of the first
to adopt the x86 architecture, which remains the foundation for modern PC processors.
This chip introduced the concept of segmentation, which allowed computers to access
more memory than the simple 64KB limit of previous microprocessors.
2. The Rise of 16-bit and 32-bit (1980s - 1990s) (1
Mark)
Key Milestones:

 Intel 80386 (1985): The 80386 was Intel's first 32-bit processor, which allowed for a
larger memory address space (4GB) and improved multitasking.
 Increased Clock Speeds and Processing Power: The 80386 introduced significant
performance improvements over its predecessors, with the introduction of protected
mode and support for larger, more sophisticated operating systems such as Windows and
UNIX.
 Motorola 68000: Competing with Intel, the Motorola 68000 (1984) used a 32-bit
architecture internally but had a 16-bit external data bus. This processor powered several
early Macintosh computers.

3. The Era of Pentium and Beyond (1990s - 2000s) (1 Mark)

Key Milestones:
 Pentium and Beyond (1993): The Intel Pentium series of microprocessors marked a major
leap forward in terms of clock speed, internal architecture (superscalar architecture), and
 multimedia capabilities. The Pentium introduced features like MMX (Multimedia
Extensions), improving performance for audio, video, and graphics.
 64-bit Microprocessors (2000s): With the release of AMD Athlon 64 (2003) and later
Intel's Core 2 Duo series, the 64-bit architecture allowed for even more memory
addressing (theoretically up to 18 exabytes of RAM) and improved performance.
 Multi-Core Processors: The advent of multi-core processors in the early 2000s (e.g., Intel
Core i7, AMD Ryzen) led to the ability to perform multiple processes simultaneously,
greatly enhancing performance and efficiency in handling multi-threaded applications.
4. Modern Microprocessors (2010s - Present) (1 Mark)
Key Milestones:
 64-bit and Beyond: Modern processors, such as Intel Core i9 and AMD Ryzen
processors, have adopted 64-bit architecture, multiple cores, and simultaneous multi-
threading (SMT). These processors can execute multiple threads per core, further
boosting performance.
 ARM Architecture: ARM-based processors, such as those used in smartphones and
tablets (e.g., Apple A-series, Qualcomm Snapdragon), became dominant in mobile
computing due to their low power consumption and high efficiency.
 Specialized Processors: The emergence of GPUs (Graphics Processing Units) and AI
chips has also pushed the boundaries of computation. GPUs are designed for parallel
processing and are widely used in fields like machine learning, scientific simulations, and
gaming.
2. Illustrate the key components and organization of 8086-microprocessor architecture.
The 8086 microprocessor, developed by Intel in 1978, is a 16-bit processor with a 32-bit
address bus. It was designed to process instructions in a more advanced manner than its
predecessors, and it forms the basis for the later x86 architecture used in modern computers.
Understanding the architecture of the 8086 is essential to comprehend how it processes
instructions and interacts with other components of a computer system.

(2 Marks)
Key Components and Organization of the 8086 Microprocessor Architecture
1. ALU (Arithmetic Logic Unit):
  The ALU is responsible for performing all arithmetic and logical operations, including
addition, subtraction, logical AND, OR, NOT, and comparison operations. It receives
data from the registers and performs the operation, sending the result back to the
appropriate register or memory location.
2. Registers:
The 8086 microprocessor contains a range of registers that serve different purposes, including
holding data, addresses, and control information. These are grouped into various categories:
 General Purpose Registers:
o AX (Accumulator Register): Used for arithmetic, logic, and I/O operations.
o BX (Base Register): Primarily used for addressing data.
o CX (Count Register): Used for loop operations (e.g., with LOOP instruction).
o DX (Data Register): Used in I/O operations, and as an extension of AX for
multiplication and division.
 Segment Registers:
o CS (Code Segment): Points to the code segment (memory area where the
program is loaded).
o DS (Data Segment): Points to the data segment (where data is stored).
o SS (Stack Segment): Points to the stack segment (used for function calls and
returns).
o ES (Extra Segment): Used in string and memory operations.
 Pointer and Index Registers:
o SP (Stack Pointer): Points to the top of the stack in the stack segment.
o BP (Base Pointer): Used in referencing data on the stack.
o SI (Source Index): Used for string operations.
o DI (Destination Index): Used for string operations.
 Flag Register:
o The Flag Register (also known as Status Register) contains individual flags that
are set or cleared based on the result of the most recent operation. The key flags
include:
 Carry Flag (CF): Indicates an overflow or underflow in arithmetic
operations.
 Zero Flag (ZF): Indicates if the result of the operation is zero.
 Sign Flag (SF): Indicates if the result is negative.
 Overflow Flag (OF): Indicates if there was an overflow in a signed
operation.
 Direction Flag (DF): Controls string operations.
 Parity Flag (PF): Indicates if the number of set bits in the result is even
or odd.
  Auxiliary Carry Flag (AF): Used in BCD arithmetic operations.
3. Bus Interface Unit (BIU):
The BIU handles communication between the microprocessor and memory or I/O devices. It is
responsible for managing the address bus, data bus, and control signals.
 Instruction Queue: The 8086 has a 6-byte instruction queue that fetches instructions in
advance from memory. This allows for pipelining, where the next instruction can be
fetched while the current instruction is being decoded and executed, improving
processing speed.
 Address Bus: The 8086 has a 20-bit address bus that can address up to 1MB of
memory.
 Data Bus: The 16-bit data bus allows data to be transferred in 16-bit chunks.
 Control Signals: The BIU generates control signals for reading from and writing to
memory or I/O ports, as well as controlling other parts of the system, such as interrupt
handling.
4. Execution Unit (EU):
The EU is responsible for decoding and executing instructions. It operates closely with the
ALU to perform operations.
 Instruction Decoder: Decodes the binary instruction fetched by the BIU.
 Control Unit: Coordinates the execution of instructions, managing how and when
different components of the microprocessor are activated. It handles instruction fetches,
decodes, and control signals for execution.
 ALU: Executes the arithmetic and logical operations.
5. Memory Organization:
The 8086 utilizes a segmented memory model, which divides the memory into smaller
segments, allowing more efficient use of available memory.
 Code Segment (CS): Contains the executable instructions of the program.
 Data Segment (DS): Stores variables, constants, and other data used by the program.
 Stack Segment (SS): Stores data related to the stack, such as function return addresses,
local variables, and intermediate data.
 Extra Segment (ES): An additional segment used for memory manipulation and string
operations.
The segment registers (CS, DS, SS, ES) provide a 16-bit offset into these segments, and the 20-
bit address bus allows accessing 1MB of memory by combining the 16-bit segment base
address with the 16-bit offset.
(3 Marks)
3. Discuss the different levels of programming languages utilized in microprocessor systems.
8086 microprocessor programming is typically done at different levels, ranging from low-level
machine language to high-level languages. These different levels of programming languages
offer varying degrees of abstraction from the hardware, providing a balance between efficiency
and ease of use. Below is a discussion of the different levels of programming languages
utilized in microprocessor systems, specifically focusing on the 8086 microprocessor:
1. Machine Language (Low-Level) (1 ½
Mark)
Description:
Machine language is the most basic level of programming, where instructions are
written in binary or hexadecimal code. These instructions are directly executed by the
microprocessor without any translation or interpretation. Each instruction corresponds
to a specific operation on the hardware, such as adding two numbers, storing data in a
register, or jumping to a different part of memory.
Characteristics:
 Binary/Hexadecimal Format: Instructions are written as binary or hexadecimal codes
(e.g., 10110000, 0xB0).
 Processor-Specific: Machine language is tailored to the architecture of the specific
microprocessor. In the case of the 8086, machine instructions correspond directly to its
opcode set (operations like MOV, ADD, etc.).
 No Abstraction: There is no abstraction, meaning the programmer must be familiar with
the hardware and instruction set.
2. Assembly Language (Low-Level) (2 Mark)
Description:
Assembly language is a step above machine language, where mnemonics (human-
readable instructions) are used to represent machine instructions. Each mnemonic
corresponds to a machine language opcode. Assembly language is specific to the
microprocessor architecture, and for the 8086, it follows the 8086 instruction set.
In assembly language, programmers can use symbols and labels for memory addresses,
registers, and constants, making the code easier to read and write compared to raw
binary.
Characteristics:
 Mnemonics: Instructions are written using mnemonics like MOV, ADD, SUB, CMP,
etc., which represent specific machine operations.
 Assembler: An assembler program is used to translate assembly language into machine
code (binary).
 Direct Access: Assembly provides direct control over system hardware (registers,
memory, etc.).
 Architecture-Specific: Assembly language is processor-specific. The 8086's assembly
language uses the x86 instruction set.
3. High-Level Languages (HLLs) (1 ½
Marks)
Description:
High-level languages provide a greater level of abstraction from the hardware. These languages
are more similar to human language and are designed to be easier to read and write. High-level
languages abstract away the details of hardware management and allow the programmer to
focus on logic and problem-solving. In the context of the 8086 microprocessor, several high-
level languages could be used, including C, Pascal, and FORTRAN.
 High-level languages require a compiler or interpreter to translate the program into machine
code. The resulting machine code is then executed by the 8086 microprocessor.
Characteristics:
 Abstraction: These languages abstract hardware details, allowing programmers to write
code without worrying about the underlying hardware.
 Portability: Programs written in high-level languages can often be compiled to run on
different hardware architectures with minimal changes.
 Ease of Use: These languages are easier to read, write, and maintain compared to
assembly or machine language.
4. Generalize the key tools used in microprocessor programming, and how do they help in
debugging and simulation.
Below are the key tools used in 8086 microprocessor programming, along with their role in
debugging and simulation: (Each tool
carries 1 mark=5 marks)
1. Assembler: An assembler is a tool that translates assembly language code into machine code
(binary code) that can be executed by the 8086 microprocessor. The assembler reads the source
code written in mnemonics (human-readable instructions) and converts them into
corresponding machine instructions.
 Error Checking: During the assembly process, the assembler detects syntax errors,
undefined labels, or incorrect instructions, making it easier for the programmer to fix
issues before execution.
 Code Optimization: Some assemblers offer optimization features that help in improving
the efficiency of the generated machine code.
 Symbol Table Generation: The assembler generates a symbol table that helps track the
usage of labels and variables in the code, which can be used for debugging.
2. Debugger: A debugger is a program used to identify and fix errors (bugs) in the source code.
It allows you to step through the code, examine the contents of registers, memory, and flags,
and track the flow of execution. Debuggers are crucial in 8086 assembly language
programming as they help pinpoint logic errors and unexpected behaviour.
 Step-by-Step Execution: Debuggers allow the user to step through the program one
instruction at a time, helping to identify the exact point where the program deviates
from the expected behaviour.
 Breakpoints: Programmers can set breakpoints to pause the program at specific
instructions or memory addresses, allowing for in-depth examination of the program’s
state at that point.
 Register and Memory Inspection: Debuggers enable users to view the contents of
various 8086 registers (like AX, BX, CX, DX) and memory locations during execution.
This allows the programmer to verify if the program is manipulating data correctly.
 Flag Monitoring: They also help in monitoring the status flags (like Carry Flag, Zero
Flag, Overflow Flag) to verify the outcomes of arithmetic operations.
3. Simulator: A simulator is a tool that emulates the 8086 microprocessor's behavior on a host
machine, allowing developers to simulate how their program will execute on actual hardware
without needing the physical microprocessor.
 Emulation of Hardware: The simulator mimics the 8086’s CPU, memory, and other
hardware features, enabling programmers to test programs in a virtual environment.
 Instruction-level Simulation: It simulates the execution of each instruction and the
manipulation of registers and flags, helping the programmer understand the precise
behavior of the program.
 Memory and I/O Simulation: Simulators allow the programmer to simulate the reading
and writing of data from/to memory and I/O ports, even when actual hardware is not
available.
 Error Detection: Simulators can identify potential issues, such as invalid memory
accesses or improper instruction sequences, and provide feedback for fixing these
issues.
4. Integrated Development Environment (IDE): An IDE is a software application that provides
comprehensive facilities for software development. It typically includes a code editor,
compiler/assembler, debugger, and other tools in one unified interface. Some IDEs are
specifically designed for assembly language programming and microprocessor simulation.
 Code Editing: IDEs provide syntax highlighting, code completion, and error warnings,
which help developers write error-free code.
 Built-in Debugger: Most modern IDEs come with an integrated debugger that allows
step-by-step execution and real-time inspection of registers, flags, and memory.
 Simulation and Testing: Some IDEs offer built-in simulators that emulate the behavior
of the 8086 processor, allowing the programmer to test the code without the need for
actual hardware.
 Error Detection: The IDE typically highlights syntax and logical errors, and some
advanced IDEs offer real-time debugging assistance by pointing to problematic sections
of code.
5. Emulator: An emulator is similar to a simulator but typically refers to a tool that mimics the
entire hardware environment (including the microprocessor, memory, I/O devices, etc.) of a
system. Emulators are used to replicate the behaviour of the 8086-microprocessor system for
development and testing.
 Hardware Emulation: Emulators replicate the 8086 microprocessor’s actual hardware,
allowing programmers to run their programs as if they were running on real hardware.
 Execution Trace: Emulators often provide a detailed trace of the program's execution,
which helps in diagnosing and debugging issues such as incorrect program flow or
memory management errors.
 Peripheral Emulation: Some emulators simulate the connected I/O devices, helping test
programs that rely on external hardware interaction.
6. Disassembler: A disassembler is a tool that converts machine code (binary) back into
assembly language, allowing the programmer to analyse a compiled program. It is useful when
you have a compiled binary program (such as from a non-8086 source) and want to inspect the
assembly code it corresponds to.
  Reverse Engineering: Disassemblers help in reverse engineering binary code to
understand how the machine code operates.
 Code Analysis: They help in inspecting the low-level machine instructions for
debugging purposes, allowing programmers to trace how a specific operation is
executed at the machine level.
 Memory Inspection: A disassembler can assist in inspecting memory by providing the
assembly equivalent of a machine code dump.
5. Demonstrate how 8086 microprocessor manages multiple interrupt requests during its
operation.
In the 8086 microprocessor, interrupt handling plays a crucial role in managing multiple
interrupt requests that occur during its operation. The 8086 uses a combination of hardware and
software mechanisms to prioritize and manage interrupt requests, ensuring that the most critical
tasks are handled first.
Key Concepts of Interrupt Handling in 8086: (2
Marks)
1. Interrupt Types:
o Hardware Interrupts: These are external signals that request the attention of the
microprocessor. These signals come from external devices such as keyboards,
timers, or external I/O devices.
o Software Interrupts: These are interrupts generated by instructions within the
program (e.g., INT instruction). These interrupts are typically used for system
calls or exception handling.
2. Interrupt Priority: The 8086 microprocessor does not have a built-in priority mechanism
for interrupt requests. However, external hardware (typically in the form of an interrupt
controller) handles the priority of the interrupt requests. The 8086 uses a priority-based
scheme where certain interrupt signals are given precedence over others.
3. Interrupt Vector Table (IVT):
o The interrupt vector table stores the addresses of interrupt service routines (ISR)
for each interrupt. The 8086 supports up to 256 interrupt types (0–255).
o The first 32 interrupts (0–31) are reserved for hardware interrupts, exceptions,
and processor-specific functions. These interrupts are mapped to specific
locations in the interrupt vector table.
o Interrupt vector 0 points to address 0000h, interrupt vector 1 points to 0004h,
and so on. Each vector consists of a 4-byte pointer that specifies the segment
and offset of the ISR.
How the 8086 Prioritizes and Manages Multiple Interrupts: (1
Mark)
1. Interrupt Request (IRQ):
2. Priority
3. Interrupt Acknowledge:
4. Interrupt Handling Process:
 Handling Multiple Interrupt Requests: (2 Marks)
If multiple interrupts are triggered at the same time, the priority system plays a critical role in
determining which interrupt is handled first.
1. Masking of Interrupts:
o The 8086 can mask interrupts using the INTR pin. If the INTR pin is not active
(logic low), the 8086 will ignore any interrupt requests.
o The Interrupt Flag (IF) in the FLAGS register determines whether the 8086 will
accept maskable interrupts. When IF = 0, interrupts are disabled, and when IF =
1, interrupts are enabled.
2. Nested Interrupts:
o The 8086 allows for nested interrupts, meaning that if a higher-priority interrupt
occurs while an ISR is running, the microprocessor will suspend the current
ISR, save its state, and jump to the ISR of the higher-priority interrupt.
o Once the higher-priority interrupt is serviced, the processor will return to the
original ISR.
For example, if an interrupt of higher priority (IRQ0) occurs while the microprocessor is
servicing an interrupt of lower priority (IRQ2), the microprocessor suspends the service of
IRQ2 and starts servicing IRQ0. After IRQ0 is handled, the 8086 will return to handle IRQ2.
3. Vectoring and Acknowledgment:
o Each interrupt request has a vector that determines the address of the ISR. For
example, the interrupt vector for IRQ0 (timer interrupt) is 0000h and for IRQ1
(keyboard interrupt) is 0004h.
o The 8086 uses the interrupt vector to jump to the correct location in the Interrupt
Vector Table (IVT). This mechanism allows the system to handle multiple
interrupt requests by directing them to the appropriate ISRs.
6. Summarize the control signals in the 8086 microprocessor’s minimum mode operation to
facilitate communication with external components.
In minimum mode operation of the 8086 microprocessor, the microprocessor operates
independently without the need for additional control chips (such as the 8288 Bus Controller).
The control signals are used to facilitate communication between the 8086 microprocessor and
external components like memory, input/output devices, and other peripherals.
Key Control Signals in 8086 Minimum Mode (Each pin carries ½ mark=5
marks)
In minimum mode, the control signals are directly generated by the 8086. These signals govern
the flow of data, address, and control between the processor and external components. Here is a
summary of the important control signals:
1. M/IO (Memory/Input-Output)
 Purpose: This signal distinguishes between memory and I/O operations.
 Logic Level:
o Low (0): Memory operation (the address is directed to memory).
o High (1): I/O operation (the address is directed to an I/O device).
  Usage: Helps determine whether the current address bus cycle is for memory or I/O
communication.
2. IO/MEM (Memory or I/O Operation)
 Purpose: Similar to M/IO, this signal indicates the type of operation (whether accessing
memory or I/O).
 Logic Level:
o Low (0): Memory operation.
o High (1): I/O operation.
3. S1 and S0 (Status Signals)
 Purpose: These are used to indicate the status of the 8086 during the bus cycle.
 Logic Levels: The combination of S1 and S0 determines the type of bus cycle (whether
it's a memory read, memory write, I/O read, I/O write, etc.).
o For example:
 S1 = 0, S0 = 0: Microprocessor is in Instruction Fetch mode.
 S1 = 0, S0 = 1: Memory Read.
 S1 = 1, S0 = 0: Memory Write.
 S1 = 1, S0 = 1: I/O Read/Write.
4. RD (Read)
 Purpose: This signal indicates that the processor is performing a read operation.
 Logic Level:
o Low (0): Read operation.
o High (1): Not a read operation.
 Usage: When RD is low, the 8086 reads data from memory or I/O. The ALE (Address
Latch Enable) signal is typically used to latch the address for memory reads.
5. WR (Write)
 Purpose: This signal indicates that the processor is performing a write operation.
 Logic Level:
o Low (0): Write operation.
o High (1): Not a write operation.
 Usage: When WR is low, the 8086 writes data to memory or an I/O device.
6. ALE (Address Latch Enable)
 Purpose: This signal is used to latch the address on the address bus into a latch or
buffer.
 Logic Level:
o High (1): When the signal is high, the address bus contains valid address data.
o Low (0): The signal is low during the data phase when the data bus is being
used.
 7. INTA (Interrupt Acknowledge)
 Purpose: This signal is generated by the 8086 in response to an interrupt request.
 Logic Level:
o Low (0): Indicates that the processor is acknowledging the interrupt request and
ready to fetch the interrupt vector.
 Usage: It is sent when the 8086 acknowledges an interrupt, signaling that it will process
the interrupt.
8. HOLD (Bus Hold)
 Purpose: This signal indicates that an external device is requesting control of the system
bus.
 Logic Level:
o Low (0): No external device is holding the bus.
o High (1): An external device is requesting control of the bus.
 Usage: Used when other devices (like DMA controllers) need access to the system bus
to transfer data.
9. HLDA (Hold Acknowledge)
 Purpose: This signal is sent by the 8086 in response to a HOLD request from an
external device.
 Logic Level:
o High (1): Indicates that the 8086 has released control of the bus to the external
device.
 Usage: When the 8086 releases the bus, it sends HLDA to acknowledge the bus
handover.
10. LOCK (Bus Lock)
 Purpose: This signal is used to prevent other devices from accessing the system bus
while the 8086 is executing critical sections of code (e.g., for atomic operations).
 Logic Level:
o Low (0): No lock; external devices can access the bus.
o High (1): Bus locked, external devices cannot access the bus.
11. RESET (System Reset)
 Purpose: This signal is used to reset the processor and initialize its internal registers and
flags.
 Logic Level:
o Low (0): Processor reset is active.
o High (1): Normal operation.
 Usage: When active, the 8086 starts executing from memory location 0xFFFF0 (the
reset vector).
7. Illustrate 8086-based microcomputer with the help of block diagram.
The 8086-based microcomputer consists of various components working together to execute
instructions and interact with external devices. Below is a diagrammatic representation of a
typical 8086-based microcomputer, illustrating its essential components.

(2 Marks)
Description of the Components:
1. 8086 Microprocessor:
o The central processing unit (CPU) of the system. It executes instructions,
handles arithmetic and logic operations, manages memory and I/O interactions,
and controls the overall operation of the system.
o The 8086 is a 16-bit microprocessor, which means it has a 16-bit wide data bus
and can handle 16-bit data in one operation.
2. Memory (RAM):
o The RAM (Random Access Memory) stores data and programs that are being
executed. It is connected to the address and data buses of the 8086
microprocessor.
o The 8086 uses a segmented memory model, where it accesses 1MB of memory
using segment registers.
3. I/O Devices:
o These include peripheral devices like a keyboard, monitor, printer, disk drives,
etc.
o The 8086 communicates with these devices via I/O ports.
4. Interrupt Controller (8259 PIC):
 o The 8259 Programmable Interrupt Controller is responsible for managing
interrupts in the system.
o The 8086 does not have a built-in interrupt controller, so the 8259 PIC helps
handle multiple interrupt requests, prioritizing them and directing the 8086 to
the appropriate Interrupt Service Routine (ISR).
5. Control Bus:
o This bus carries control signals from the 8086 to manage the operation of
memory, I/O devices, and peripherals. These signals include read, write, and
interrupt signals.
6. Address Bus:
o The address bus is responsible for carrying the address from the 8086 to
memory and I/O devices to fetch or store data.
o The 8086 has a 20-bit address bus, allowing access to 1MB of memory.
7. Data Bus:
o The data bus is used for transferring data between the 8086 microprocessor,
memory, and I/O devices.
o The 8086 has a 16-bit data bus, meaning it can transfer 16 bits of data at a time.
Functionality of Each Component:
 The 8086 microprocessor fetches instructions from RAM or I/O devices through the
address and data buses.
 It executes the instructions and uses the control bus to manage the communication with
memory and I/O devices.
 The 8259 PIC manages interrupts and ensures that the microprocessor handles them in
priority order, sending an Interrupt Acknowledge signal to the processor when an
interrupt is serviced.
This basic architecture allows the 8086 microprocessor to interact with external memory,
peripherals, and handle interrupts, enabling it to perform complex operations and execute user
programs in real-time.
(3 Marks )
8. Explain about the 8086 microprocessor's pin diagram. (Pin diagram – 1 mark, pin
details – 4 marks)
Explanation of Key Pins in the 8086 Microprocessor Pin Diagram:
1. AD0-AD15 (Address/Data Bus):
o These are multiplexed pins for address and data transfer. The 8086 uses these pins
to carry both address and data during different phases of its bus cycle. Initially,
these pins carry address information, and later, they carry data during read/write
operations.
2. A0-A19 (Address Bus):
o These pins provide the 20-bit address for accessing up to 1MB of memory. The
8086 microprocessor can address 1MB of memory, and these address lines send
the corresponding memory address to the RAM or I/O devices.
3. M/IO (Memory/Input-Output):
o This pin tells whether the microprocessor is performing a memory operation or
an I/O operation.
o Low (0): Memory operation
o High (1): I/O operation
4. RD (Read) and WR (Write):
o These pins control read and write operations. When RD is low, it indicates a read
operation, and when WR is low, it indicates a write operation.
5. RESET:
o The RESET pin initializes the microprocessor, clearing all registers and restarting
the program from the reset vector (typically 0xFFFF0).
6. HOLD and HLDA (Hold and Hold Acknowledge):
o HOLD: A request from an external device to take control of the system bus (e.g.,
for DMA operations).
o HLDA: The microprocessor responds to a HOLD request by acknowledging the
bus release.
7. CLK (Clock):
o The clock pin provides the timing signal for the microprocessor, synchronizing
all operations inside the 8086.
8. INTA (Interrupt Acknowledge):
o This pin signals that the 8086 is acknowledging an interrupt request. It is used to
retrieve the interrupt vector.
9. LOCK:
o The LOCK pin prevents other devices from accessing the system bus while the
microprocessor is executing critical instructions that require exclusive access to
the bus.
 10. BUSY:
o The BUSY pin indicates if the microprocessor is in use and can accept or initiate
operations. It is used to indicate bus contention.
11. READY:
o The READY pin informs the microprocessor if the external device is ready for
data transfer or if it needs to wait for the device to become ready.
12. NMI (Non-Maskable Interrupt):
o The NMI pin is used to handle high-priority interrupts that cannot be masked by
the interrupt flags.

9. Classify the common problems encountered in the 8086 microprocessor and the steps taken
to troubleshoot them. (Each step 1 mark= 5 marks)
The 8086 microprocessor is a powerful processor, but like any complex electronic device, it can
experience various issues. Below are some common problems encountered in 8086 systems and
the troubleshooting steps to resolve them.
1. System Not Starting / No Power On
Problem: The microprocessor is not powering up, or the system does not begin the boot process.
Possible Causes: Power supply failure, Incorrect power connection to the microprocessor
(VCC/GND), Damaged microprocessor or faulty components like the crystal oscillator.
Troubleshooting Steps: Check Power Supply, Inspect Connections, Check Oscillator Circuit,
Test Microprocessor, Verify Power Rails.
2. Incorrect or No Output on Display
Problem: The system is running, but there is no output on the monitor or incorrect data displayed.
Possible Causes: Issues with the data bus or address bus, Faulty memory (RAM), Problems with
the I/O ports or display circuitry, Misconfigured I/O devices.
Troubleshooting Steps: Check Address/Data Bus, Check Memory, Test Display Interface, Check
I/O Port Connections
3. Intermittent System Crashes or Freezes
Problem: The microprocessor system runs fine for a while, but then it crashes or freezes
intermittently.
Possible Causes: Faulty interrupt handling, Memory issues (e.g., RAM corruption or improper
memory addressing), Bus contention or timing issues, Issues with control signals like RD or WR.
Troubleshooting Steps: Check Interrupts, Examine Timing Signals, Memory Diagnostics, Check
Bus Signals, Check Control Signals.
4. System Running But Incorrect Data Processing (Logical Errors)
Problem: The system runs, but the computations or logic operations produce incorrect results.
Possible Causes: Incorrect programming or corrupted software, Faulty registers or improper
memory access, Issues with the ALU (Arithmetic Logic Unit) or instruction decoding.
 Troubleshooting Steps: Check Program Code, Examine Register States, Verify ALU Operations,
Verify Memory Access
5. Interrupts Not Being Serviced Properly
Problem: The system has interrupt handling, but interrupts are not serviced correctly or are
ignored.
Possible Causes: Issues with the interrupt controller (e.g., 8259 PIC), Incorrect interrupt vector
table or handler, Interrupt priority problems.
Troubleshooting Steps: Check Interrupt Controller, Verify Interrupt Vector Table, Check
Interrupt Flags, Test Interrupt Priority.
6. Bus Contention or Conflicts
Problem: The microprocessor is trying to access the bus while another device is also attempting
to use it, leading to bus contention.
Possible Causes: DMA (Direct Memory Access) devices trying to use the bus, Conflicts between
the microprocessor and peripheral devices (e.g., video card, I/O devices).
Troubleshooting Steps:
Monitor Bus Signals, Check DMA Control Lines, Isolate Peripherals, Check Bus
Arbitration.
10. Discuss how the assembler directives influence the way an assembly language program is
processed by the assembler.
Assembler directives are commands in assembly language programs that instruct the assembler
on how to process the source code. They are not translated into machine code but influence the
assembly process, such as the allocation of memory, setting data types, and controlling program
execution. In the context of the 8086 microprocessors, these directives provide essential
guidance on how the assembler handles and structures the assembly code. Here's a breakdown
of how they influence the assembly process:
1. Memory Allocation and Initialization (1 Mark)
Assembler directives play a key role in allocating memory and initializing values. They help
define sections of the program (such as data and code sections) and specify how data is stored.
Example: .data, .bss, .code
 .data: This directive is used to declare initialized data (e.g., variables with predefined
values). It tells the assembler that the data following this directive is initialized and ready
for use.
 .bss: Used for uninitialized data. This section reserves space in memory but does not
initialize it. The assembler will allocate memory space for variables declared with this
directive but will not assign them a value.
 .code: Marks the beginning of the code segment, where the actual instructions reside.
2. Control over Program Execution (1 Mark)
Some directives influence the flow of execution, enabling the programmer to specify where the
program starts or when the execution halts.
Example: .org, .end
  .org: This directive is used to set the starting address of the program or a particular
section. It allows control over where specific parts of the program will reside in memory.
 .end: Marks the end of the source code. This tells the assembler that there is no more
source code to process.
3. Data Type Definitions and Allocation (1 Mark)
Assembler directives enable the programmer to define the size and type of data elements. This
influences how the data is processed and stored in memory.
Example: .byte, .word, .dword
 .byte: This directive defines a byte (8 bits) of data, allowing the programmer to specify
values for individual bytes.
 .word: This directive is used to define word-sized data (16 bits). It is particularly useful
for allocating variables that are intended to hold values larger than a byte.
 .dword: This is used to define double word data (32 bits) and is more common in modern
systems. In the 8086, it is not as commonly used because the 8086 is a 16-bit
microprocessor.
4. Macro Definitions ( ½ Mark)
Assembler directives like macros help in defining reusable code blocks that can be inserted into
the program at various points. They influence the assembly process by substituting code snippets
wherever macros are invoked.
Example: MACRO, ENDM
 MACRO: This directive is used to define a macro that can be used multiple times within
the program. It enables reusability and reduces the need to write repetitive code.
 ENDM: Marks the end of the macro definition.
5. Conditional Assembly ( ½ Mark)
Assembler directives also allow for conditional assembly, enabling the program to include
or exclude portions of code based on certain conditions. This is helpful for creating code that
can adapt to different environments or configurations.
Example: IF, ENDIF
 IF / ENDIF: This directive enables conditional assembly, allowing the assembler to
include or exclude blocks of code based on the evaluation of a condition.
6. Equate Directives ( ½ Mark)
Equate directives allow programmers to assign names to specific constants or memory
locations. This improves code readability and maintenance by using meaningful names
instead of magic numbers or raw addresses.
Example: EQU
 EQU: Used to define constants or equate values to symbolic names.
7. Aligning Data ( ½ Mark)
In some cases, data must be aligned on boundaries (such as word or double-word boundaries)
for optimal performance or correct functioning. Assembler directives allow for this alignment.
Example: .align
 .align: Ensures that data is aligned to a specified boundary, typically 2-byte (word) or 4-byte
(double-word) alignment.
 UNIT - 2 ANSWER KEY

Two Marks Questions

1. List the different types of addressing modes in 8086.
Answer: The 8086 microprocessor supports the following addressing modes:
 Immediate Addressing: Operand is directly specified in the instruction.
 Register Addressing: Operand is in a register.
 Direct Addressing: Operand is located at a specific memory address.
 Indirect Addressing: Operand is at a memory location specified by a register.
 Indexed Addressing: Operand’s address is computed using a base address and an
index.
 Based Indexed Addressing: Operand’s address is computed using a base register and
an index register.

2. What are the arithmetic instructions supported in 8086?

Answer: Arithmetic instructions perform mathematical operations on data. Common
arithmetic instructions include:
 ADD destination, source: Adds the source operand to the destination operand.
 SUB destination, source: Subtracts the source operand from the destination operand.
 MUL operand: Multiplies the accumulator (AX) by the operand.
 DIV operand: Divides the accumulator (AX) by the operand.
 INC operand: Increments the operand by 1.
 DEC operand: Decrements the operand by 1.

3. Illustrate the functions of CMP instruction in 8086.

Answer: The CMP instruction compares two operands by subtracting the source operand
from the destination operand. It does not store the result, but it updates the flags based on the
result of the subtraction, allowing conditional branches.
Example: CMP AX, BX (Compares AX with BX).
4. Classify the different types of branch instructions in 8086.
Answer: Branch instructions in 8086 allow for conditional or unconditional jumps. Types
include:
 Unconditional: JMP (Unconditional jump).
 Conditional: JE/JZ, JNE/JNZ, JG, JL, JC, JNC, etc., which depend on the status of
flags.

5. Define the LOOP instruction in 8086.

Answer: The LOOP instruction is used for looping a specific number of times. It decrements
the CX register by 1 and jumps to the specified label if CX is not zero.
Example: LOOP LOOP_START (Decrements CX and jumps to LOOP_START if CX ≠ 0).

6. Discuss the use of JMP instruction in 8086.

Answer: The JMP instruction is used for an unconditional jump to a specified label or
address. It causes the program control to transfer to the target address.
Example: JMP START (Unconditionally jumps to the label START).

7. Outline the logical instructions in 8086.

Answer: Logical instructions perform bitwise operations. Common logical instructions
include:
 AND destination, source
 OR destination, source
 XOR destination, source
 NOT operand (performs complement operation).

8. State the term, “Procedure” in assembly language.

Answer: A procedure is a block of code that performs a specific task. It is similar to a
function in high-level languages. A procedure is invoked via the CALL instruction and
returns control to the caller via the RET instruction.

9. Explain briefly about the function of NOP instruction in 8086.

Answer: The NOP (No Operation) instruction does nothing. It is used for inserting a delay or
aligning code without affecting registers or flags.
Example: NOP (No operation is performed).
10. List the purpose of IN and OUT instructions in 8086.
Answer:
 IN port, AL: Reads data from the specified port and stores it in the AL register.
 OUT AL, port: Sends data from the AL register to the specified port.
These are used for I/O operations.

Three Marks Questions.

1.Explain the function of MOV instruction in 8086 with suitable example.
Explanation:1 Mark
Syntax and Example: 2 Marks

The MOV instruction in 8086 is one of the most commonly used instructions in assembly
language. It is primarily used to transfer data from one location to another. The MOV
instruction can copy data between various operands, such as registers, memory, and
immediate values.

Syntax:

MOV destination, source

 Destination: This is where the data will be moved to (it can be a register or a memory
location).
 Source: This is the data that will be moved to the destination. It can be a register, a
memory location, or an immediate value (constant).

Examples:
 "MOV AX, BX": Copies the contents of register BX to register AX.
 "MOV [BX], 10H": Stores the immediate value 10H into the memory location
addressed by the contents of register BX.

2. Illustrate the purpose of PUSH and POP instructions in 8086 with relevant syntax
and example.
Explanation:1 Mark
Syntax and Example: 2 Marks
Answer: The PUSH and POP instructions are used in assembly language programming to
manage data on the stack. The stack is a special region of memory used to store temporary
data, such as local variables, return addresses, and saved register values, especially when
calling procedures or handling interrupts.
1. PUSH Instruction:

The PUSH instruction is used to push data onto the stack. It involves two main actions:

 Decrement the stack pointer (SP): The Stack Pointer (SP) register points to the top
of the stack. When a PUSH operation is performed, the SP is first decremented
(because the stack grows downward in memory).
 Store the value: The value from the specified operand is then stored at the memory
location pointed to by the updated SP.

Syntax:

PUSH operand

 Operand: The data that will be pushed onto the stack. This can be a register or a
memory location.

How PUSH Works:

 The SP register is first decremented by 2 (since 8086 is a 16-bit processor and uses
16-bit data).
 Then, the operand (either a register or a memory value) is copied to the new memory
location pointed to by SP.

Example:
PUSH AX ; Push the value of AX onto the stack

In this example:

 The value in register AX is pushed onto the stack.

 The SP is decremented by 2, and the value in AX is stored at the memory location
pointed to by the new value of SP.

2. POP Instruction:

The POP instruction is used to pop data from the stack. It performs two actions:

 Load the value from the stack: The value from the memory location pointed to by
the SP register is copied to the operand (usually a register).
 Increment the stack pointer (SP): After the value is transferred, the SP is
incremented by 2, effectively removing the data from the stack.

Syntax:

POP operand

 Operand: The location (usually a register) where the data will be transferred from the
stack.
How POP Works:

 The SP register points to the top of the stack. The value at that memory location is
copied into the specified operand.
 After the value is popped off the stack, the SP is incremented by 2.

Example:

POP BX ; Pop the top value from the stack into BX

In this example:

 The value from the memory location pointed to by SP is moved into register BX.
 Afterward, the SP is incremented by 2, effectively removing the value from the stack.

3. Classify the difference between a macro and a procedure.

For any 3 differences: 3 marks
Answer:
 Macro: A macro is a sequence of code that is expanded at compile-time wherever the
macro is invoked.
 Procedure: A procedure is a block of code that is executed when called, and it is
typically called at runtime. Procedures support parameters and provide modularity.

4. Discuss the functions of IDIV instruction in 8086.

Def & Syntax: 1 mark
8 Bit example: 1 mark
16 Bit example: 1 mark
Answer: The IDIV instruction is used for signed division. It divides the accumulator by a
specified operand and stores the quotient in AL or AX, and the remainder in AH.

The IDIV instruction in the 8086 microprocessor is used for signed integer division. It
divides a signed 16-bit number by another signed 8-bit or 16-bit number, depending on the
operands. The result of the division is placed in the AX register (for 8-bit divisor) or in
DX:AX (for 16-bit divisor), and the flags are updated based on the result.

Syntax:
IDIV divisor

 Divisor: The number by which the dividend (either in AX or DX:AX) is divided.

Example: IDIV BL (Divides AX by BL and stores the quotient in AL and remainder in AH).
Examples:
1. 8-bit Signed Division:
MOV AX, 1234h ; Dividend (AX = 1234h)
MOV BL, 10 ; Divisor (BL = 10)
IDIV BL ; Signed division: AX divided by BL

 AX contains the dividend (1234h).

 BL contains the divisor (10).
 After IDIV BL, the quotient will be stored in AL (8-bit) and the remainder in AH (8-
bit).

2. 16-bit Signed Division:

MOV DX, 1234h ; High word of the dividend (DX = 1234h)
MOV AX, 5678h ; Low word of the dividend (AX = 5678h)
MOV BX, 100 ; Divisor (BX = 100)
IDIV BX ; Signed division: DX:AX divided by BX

 DX:AX contains the 32-bit dividend.

 BX contains the divisor.
 After IDIV BX, the quotient will be stored in AX (16-bit) and the remainder in DX
(16-bit).

5. Explain about the CALL instruction in 8086.

Def & Ex: 1 mark
Operation: 2 marks
Answer: The CALL instruction is used to invoke a procedure or function. It pushes the
address of the next instruction onto the stack before jumping to the procedure’s address.
Example: CALL PROC (Calls the procedure PROC).

The CALL instruction in 8086 is used to call a procedure or function. When executed, it
does two things:

1. Pushes the address of the next instruction (the instruction following the CALL)
onto the stack.
2. Transfers control to the procedure or function specified by the operand (address).

The CALL instruction is essential for subroutine invocation and procedure calls, enabling
the execution of reusable blocks of code.

Syntax:
CALL destination

 destination: This is the address of the procedure or function to which control is

transferred. It can be a direct address (e.g., a label) or an indirect address (e.g., stored
in a register or memory location).

How CALL Works:

1. Push the Return Address:

o The next instruction's address (the instruction following the CALL) is
pushed onto the stack. This is called the return address because it tells the
processor where to return after the procedure has finished executing.
o The stack pointer (SP) is decremented by 2 (since 8086 is a 16-bit processor)
before the return address is stored.
2. Transfer Control:
o After the return address is pushed onto the stack, the Program Counter (IP)
is loaded with the address of the procedure or function, causing the processor
to jump to that address and start executing the procedure.
3. Procedure Execution:
o The procedure executes, and when it is done, the RET (return) instruction is
typically used to pop the return address from the stack and jump back to the
instruction following the CALL.

6. Compare the REP and REPE instructions used in 8086.

Def: 1 Mark
Comparison table: 2 marks
Answer:
 REP is used to repeat a string operation a number of times. It is combined with string
instructions like MOVSB or CMPSB.
 REPE (repeat while equal) performs a string operation while the Zero flag (ZF) is set.
Example: REP MOVSB (Repeatedly moves a byte from DS:SI to ES:DI).

7. Outline the functions of RET instruction in 8086.

Defn & Ex: 1mark
Diagram & Explanation: 2 marks
Answer:

The RET instruction stands for return. This instruction is used at the end of the procedures
or the subprograms. This instruction transfers the execution to the caller program. Whenever
the RET instruction is called, the following process takes place inside the microprocessor:

 The address of the next instruction in the mainline program which was previously
stored inside the stack is now again fetched and is placed inside the instruction pointer
(IP).
 The instruction queue will now again be filled with the subsequent instructions of the
mainline program.

The Syntax for the RET instruction is as follows:

RET

Example: RET (Returns from the procedure).

The following diagram illustrates how the control of the instruction execution is transferred
within the code from one program to another whenever a procedure is called and whenever it
returns the execution. In most of the cases, the procedure CALL is made from the mainline
program and hence the control is returned to the mainline program itself.
8. Compare JMP and CALL instructions used in 8086.
Defn: 1 mark
Comparison table (Any 4): 2 marks
Answer:
 JMP: An unconditional jump to a specified label or memory address.
 CALL: Calls a procedure, saves the return address on the stack, and jumps to the
procedure.
Exam
9.Demonstrate how a WHILE loop can be implemented in assembly language with an
example.
Def: 1 mark
Example: 2 marks

Answer: A WHILE loop in assembly can be implemented using a comparison (CMP)

instruction to check the condition and a jump (JGE) to exit the loop when the condition is
false.

Example:

MOV AX, 0 ; Initialize AX to 0

WHILE_LOOP:
CMP AX, 10 ; Compare AX with 10
JGE END_LOOP ; Jump to END_LOOP if AX >= 10
INC AX ; Increment AX
JMP WHILE_LOOP ; Repeat the loop
END_LOOP:

In this example, the loop continues to run while the value in AX is less than 10.

10. Illustrate the ADD and SUB instructions with relevant examples.
Defn & Example for each: 1.5 marks
ADD Instruction in 8086

The ADD instruction is used to add the contents of two operands and store the result in the
destination operand. The operands can be registers, memory locations, or immediate values.

Syntax:
ADD destination, source

 destination: This is the operand that will receive the result of the addition.
 source: This is the operand that will be added to the destination operand.

Example of ADD Instruction:

MOV AL, 5 ; Load AL with 5

MOV BL, 3 ; Load BL with 3
ADD AL, BL ; Add BL to AL and store the result in AL

In this example:

 The value of AL is initially 5.

 The value of BL is 3.
  The ADD AL, BL instruction adds 3 (value of BL) to 5 (value of AL), and stores the
result 8 in AL.
 The Carry Flag and Overflow Flag will remain unaffected because the result doesn't
cause a carry or overflow.

After execution, AL = 8.

SUB Instruction in 8086

The SUB instruction is used to subtract the contents of one operand from another and store
the result in the destination operand.

Syntax:
SUB destination, source

 destination: This is the operand that will receive the result of the subtraction.
 source: This is the operand that will be subtracted from the destination operand.

Example of SUB Instruction:

MOV AL, 10 ; Load AL with 10
MOV BL, 4 ; Load BL with 4
SUB AL, BL ; Subtract BL from AL and store the result in AL

In this example:

 The value of AL is initially 10.

 The value of BL is 4.
 The SUB AL, BL instruction subtracts 4 (value of BL) from 10 (value of AL), and
stores the result 6 in AL.
 The Carry Flag will be cleared (no borrow), and the Zero Flag will also be cleared
since the result is not zero.

After execution, AL = 6.

Five Marks Questions.

1.Explain the various addressing modes in 8086 with relevant examples.
Addressing mode Defn: 1 mark
Explanation of any 5 Addressing modes with examples: 4 marks
Addressing Modes of 8086
 Addressing mode indicates a way of locating data or operands.
 Depending upon the data types used in the instruction and the memory addressing
modes, any instruction may belong to one or more addressing modes, or some
instruction may not belong to any of the addressing modes.
 Thus addressing modes describe the types of operands and the way they are accessed
 for executing an instruction.
 According to the flow of instruction execution, the instructions may be categorized as

Sequential control flow instructions

Control transfer instructions
 Sequential control flow instructions are the instructions which after execution,
transfer control to the next instruction appearing immediately after it in the program.
 For example, the arithmetic, logical, data transfer and processor control instructions
are sequential control flow instructions.
 The control transfer instructions, on the other hand , transfer control to some
predefined address or the address somehow specified in the instruction, after their
execution.
 For example INT, CALL, RET and JUMP instructions fall under this category
 The addressing modes for sequential and control transfer instructions are explained as
follows.
1 Immediate:
•In this type of addressing, immediate data is a part of instruction, and appears in the
form of successive byte or bytes
Eg: MOV AX, 0005H

2 Direct:
•In the direct addressing mode, a 16-bit memory address (offset) is directly specified
in
the instruction as a part of it.
Eg: MOV AX,[5000H], –Effective address= 10H*DS +5000H

3 Register:
•In the register addressing mode, the data is stored in a register and it is referred using
the particular register
•All the registers, except IP, may be used in this mode.
•Eg: MOV AX, BX
4 Register Indirect:
•Sometimes, the address of the memory location which contains data or operand is
determined in an indirect way, using the offset registers.
•This mode of addressing is known as register indirect mode
•In this addressing mode, the offset address of data is in either BX or SI or DI register.
•The default segment is either DS or ES. The data is supposed to be available at the
address pointed to by the content of any of the above registers in the default data
segment.
Eg: MOV AX,[BX] –Effective address is 10H*DS+[BX]

5 Indexed:
•In this addressing mode, offset of the operand is stored in one of the Index registers.
DS is the default segment for index registers SI and DI
•In the case of string instructions DS and ES are default segments for SI and DI
respectively.
•This mode is a special case of the above discussed register indirect addressing mode
Eg: MOV AX,[SI] –effective address is 10H*DS+[SI]

6 Register Relative:
•In this addressing mode, the data is available at an effective address formed by
adding an 8-bit or 16-bit displacement with the content of any one of the registers BX,
BP, SI and DI in the default (either DS or ES) segment.
Eg: MOV AX,50H[BX] –Effective address is 10H*DS+50H+[BX]

7 Based Indexed:
•The effective address of the data is formed, in this addressing mode, by adding the
content of a base register (any one of BX or BP) to the content of an index register
(anyone of SI or DI)

•The default segment register may be DS or ES

Eg: MOV AX,[BX][SI] effective address is 10H*DS +[BX]+[SI]
8 Relative Based Indexed:
•The effective address is formed by adding an 8-bit or 16-bit displacement with the
sum of contents of anyone of the base registers (BX or BP) and any one of the index
registers (SI or DI), in a default segment.

Eg: MOV AX,50H[BX][SI] –Effective address is 10H* DS+[BX]+[SI]+50H

•For the control transfer instructions, the addressing modes depend upon whether the
destination location is within the same segment or in a different one.
•It also depends upon the method of passing the destination address to the processor.
•Basically there are two addressing modes for the control transfer instructions, viz,
intersegment and intra segment addressing modes.
•If the location to which the control is to be transferred lies in a different segment
other than the current one, the mode is called intersegment mode.
•If the destination location lies in the same segment, the mode is called intra segment
Mode

Fig 2.1 Addressing modes for control transfer instructions

2. Demonstrate the various Data transfer instructions in 8086 with examples.

Explanation of any 5 data transfer instructions: 5 marks
Answer:
Data Transfer Instructions in 8086

In the 8086 microprocessor, data transfer instructions are used to transfer data between
registers, memory locations, and I/O ports. These instructions do not involve any arithmetic
or logical operations; instead, they move data from one place to another.

The primary data transfer instructions in 8086 include MOV, PUSH, POP, XCHG, IN, and
OUT.
1. MOV (Move) Instruction

The MOV instruction is used to transfer data between registers, memory, and I/O ports. It
moves data from the source operand to the destination operand. The source and destination
operands can be:

 Immediate values
 Registers
 Memory locations

Syntax:
MOV destination, source
Examples:
MOV AX, BX ; Move the content of BX into AX
MOV AL, 0xFF ; Move immediate value 0xFF into AL
MOV [5000h], AX ; Move the content of AX into memory location 5000h

 The MOV instruction does not modify the flags.

2. PUSH Instruction

The PUSH instruction is used to push a value onto the stack. It decrements the stack
pointer (SP) and then stores the value at the memory location pointed to by SP.

Syntax:

PUSH source

 The source can be a register or memory operand.

 The stack grows downward, so SP is decremented before storing the data.

Example:
PUSH AX ; Push the value of AX onto the stack

 This stores the value of the AX register at the memory address pointed to by SP and
decrements SP by 2 (since it's a 16-bit register).

3. POP Instruction

The POP instruction is used to pop a value from the stack into a register or memory location.
It first loads the value from the memory location pointed to by SP and then increments SP.

Syntax:
POP destination

 The destination can be a register or memory location.

 SP is incremented after the value is loaded into the destination.
Example:
POP AX ; Pop the value from the stack into AX

 This instruction loads the value at the memory address pointed to by SP into the AX
register and increments SP by 2.

4. XCHG Instruction

The XCHG (Exchange) instruction is used to exchange the values of two operands. The
operands can be registers or memory locations.

Syntax:
XCHG operand1, operand2

 The XCHG instruction swaps the contents of operand1 and operand2.

Example:
XCHG AX, BX ; Exchange the values of AX and BX

 This swaps the contents of the AX and BX registers.

5. IN Instruction

The IN instruction is used for input operations from an I/O port into a register. The value is
read from the I/O port specified by the port address.

Syntax:

IN destination, port

 destination: A register where the input data will be stored.

 port: The I/O port number from which the data will be read. The port can be specified
as an immediate value or a register.

Example:
IN AL, 0x60 ; Input a byte from I/O port 0x60 into AL

 This reads a byte of data from I/O port 0x60 and stores it in the AL register.

6. OUT Instruction

The OUT instruction is used for output operations to an I/O port from a register. The value
of the register is written to the specified port.
Syntax:
OUT port, source

 port: The I/O port number to which the data will be sent.
 source: The register containing the data to be output.

Example:
OUT 0x60, AL ; Output the value of AL to I/O port 0x60

 This writes the contents of the AL register to I/O port 0x60.

3. Explain the Arithmetic and Logical instructions in 8086 with examples.

Arithmetic instructions 2.5 marks
Logical instructions: 2.5marks
Answer: Arithmetic and logical instructions are used to perform mathematical and
bitwise operations. Some of these instructions include:
 Arithmetic Instructions:
o ADD destination, source: Adds the source operand to the destination.
Example: ADD AX, BX (Adds the value of BX to AX).
o SUB destination, source: Subtracts the source operand from the destination.
Example: SUB AX, BX (Subtracts BX from AX).
o MUL operand: Multiplies AX by the operand and stores the result in AX.
Example: MUL BX (Multiplies AX by BX).
o DIV operand: Divides AX by the operand and stores the result in AX and the
remainder in DX. Example: DIV BX (Divides AX by BX).
 Logical Instructions:
o AND destination, source: Performs a bitwise AND between the operands.
Example: AND AX, BX (Performs bitwise AND between AX and BX).
o OR destination, source: Performs a bitwise OR between the operands.
Example: OR AX, BX (Performs bitwise OR between AX and BX).
o XOR destination, source: Performs a bitwise XOR between the operands.
Example: XOR AX, BX (Performs bitwise XOR between AX and BX).
o NOT operand: Performs bitwise negation (complement) on the operand.
Example: NOT AX (Performs bitwise NOT on AX).
These instructions allow the processor to perform complex data manipulations.
 4. Construct the Loop instructions in 8086 with an example.
Defn & Types: 2 marks
Explanation of each: 1 mark (3 marks)

Answer: In the 8086 microprocessor, loop instructions are used to repeatedly execute a block
of code a specific number of times. Looping is essential for implementing repetitive tasks in
assembly language programs. The primary loop instructions in 8086 are:

1. LOOP
2. LOOPNZ / LOOPNE
3. LOOPZ / LOOPE

These loop instructions work by manipulating the CX register (or ECX in 32-bit versions),
which holds the count of iterations. Each time a loop instruction is executed, the CX register
is decremented by 1, and the loop continues until CX becomes zero. The behavior of the loop
can be modified by conditional checks (like Z for zero or NZ for non-zero).

1. LOOP Instruction

The LOOP instruction decrements the CX register by 1 and loops (jumps to the specified
label) if CX is not zero.

Syntax:
LOOP label

 CX is automatically decremented by 1.
 If CX is not zero, the program jumps to the specified label and repeats the loop.
 If CX is zero, the loop is exited, and the program continues with the next instruction.

Example:
MOV CX, 5 ; Load CX with 5 (loop will run 5 times)
START_LOOP:
MOV AX, 0 ; Some code to execute in the loop
ADD AX, 1 ; Increment AX
LOOP START_LOOP ; Decrement CX and loop back if CX != 0

In this example:

 MOV CX, 5 sets the loop counter to 5.

 The loop will repeat until CX becomes 0. In each iteration, AX is incremented by 1.
 The LOOP instruction will check CX, decrement it, and continue looping as long as
CX is not zero.
2. LOOPNZ / LOOPNE Instruction

The LOOPNZ (Loop if Not Zero) or LOOPNE (Loop if Not Equal) instruction decrements
the CX register by 1 and loops if CX is not zero and if the Zero Flag (ZF) is clear (i.e., the
condition is not zero).

Syntax:
LOOPNZ label

or

LOOPNE label

 CX is decremented by 1.
 The loop continues if CX is not zero and if ZF is clear (indicating the condition was
not zero).

Example:
MOV CX, 5 ; Load CX with 5
MOV AX, 0 ; Initialize AX to 0
START_LOOPNZ:
CMP AX, 3 ; Compare AX with 3
LOOPNZ START_LOOPNZ ; Loop if CX is not zero and AX != 3
INC AX ; Increment AX

In this example:

 The loop will run as long as CX is not zero and AX != 3 (since CMP AX, 3 affects
the ZF).
 The LOOPNZ instruction will only jump if ZF is not set (i.e., if the comparison was
not zero).
 The loop will stop if CX reaches zero or AX becomes equal to 3.

3. LOOPZ / LOOPE Instruction

The LOOPZ (Loop if Zero) or LOOPE (Loop if Equal) instruction decrements the CX
register by 1 and loops if CX is not zero and if the Zero Flag (ZF) is set (i.e., the condition is
zero).

Syntax:
LOOPZ label

or

LOOPE label

 CX is decremented by 1.
 The loop continues if CX is not zero and if ZF is set (indicating the condition is zero).
Example:
MOV CX, 5 ; Load CX with 5
MOV AX, 0 ; Initialize AX to 0
START_LOOPZ:
CMP AX, 0 ; Compare AX with 0
LOOPZ START_LOOPZ ; Loop if CX is not zero and AX == 0
INC AX ; Increment AX

In this example:

 The loop will run while CX is not zero and AX == 0.

 The LOOPZ instruction checks if ZF is set (indicating AX is equal to 0). If so, it
continues looping.

5. Illustrate the term, “Procedure” in 8086 and explain how to define and call a
procedure.

Defn: 2 marks
Explanation: 3 marks
Answer: A procedure is a block of code that performs a specific task. Procedures in 8086
allow modularity and code reusability.
 Defining a Procedure: To define a procedure, the PROCEDURE directive is used,
and the RET instruction returns control to the calling program.
Example:
assembly code
PROC1 PROCEDURE
; Procedure instructions
RET
PROC1 ENDP
 Calling a Procedure: The CALL instruction is used to invoke a procedure, which
pushes the return address onto the stack and transfers control to the procedure.
Example:
Assembly code
CALL PROC1 ; Calls the PROC1 procedure
After execution, the RET instruction in the procedure will return control to the next
instruction after CALL.
6.Relate macros in assembly language. Discuss how are they defined and used in 8086.
Defn: 2 marks
Explanation with Ex: 3 marks
Answer: A macro is a sequence of assembly instructions that is defined once and can be used
multiple times in a program. Macros are expanded during the assembly process, and their
code is inserted at the point where the macro is called.
 Defining a Macro: A macro is defined using the MACRO directive and ends with the
ENDM directive.
Example:
MYMACRO MACRO
; Macro instructions
MOV AX, BX
ENDM
 Using a Macro: A macro is called by using its name in the program. When invoked,
the macro's code is inserted inline.
Example:
Assembly code
MYMACRO ; Expands to MOV AX, BX
Macros allow code reuse but increase the size of the program since the code is expanded.

7. Explain the different branch instructions in 8086.

Conditional branch instructions: 2.5 marks
Unconditional branch instructions: 2.5 marks
Answer: Branch instructions control the flow of execution based on certain conditions or
unconditionally. Common branch instructions include:
 Unconditional Branch:
o JMP label: Unconditionally jumps to the specified label.
 Conditional Branches:
o JE (Jump if equal), JZ (Jump if zero)
o JNE (Jump if not equal), JNZ (Jump if not zero)
o JG (Jump if greater), JNLE (Jump if not less or equal)
 o JL (Jump if less), JNGE (Jump if not greater or equal)
o JC (Jump if carry), JNC (Jump if no carry)
o JO (Jump if overflow), JNO (Jump if no overflow)
These instructions depend on the flags (ZF, CF, OF) and allow branching based on the results
of previous operations.
1. Unconditional Program Execution Transfer Instructions – These instruction always
execute.
Opcode Operand Explanation Example

calls a subroutine and saves the return address on CALL

CALL address
the stack 2050

RET none returns from the subroutine to the main program RET

transfers the control of execution to the specified JUMP

JUMP address
address 2050

loops through a sequence of instructions until LOOP

LOOP address
CX=0 2050

Here the address can be specified directly or indirectly.

2.Conditional Program Execution Transfer Instructions : These instructions only

execute when the specified condition is true.

Opcode Operand Explanation Example

JC address jump if CF = 1 JC 2050

JNC address jump if CF = 0 JNC 2050

JZ address jump if ZF = 1 JZ 2050

JNZ address jump if ZF = 0 JNZ 2050

JO address jump if OF = 1 JO 2050

JNO address jump if OF = 0 JNO 2050

JP address jump if PF = 1 JP 2050

Opcode Operand Explanation Example

JNP address jump if PF = 0 JNP 2050

JPE address jump if PF = 1 JPE 2050

JPO address jump if PF = 0 JPO 2050

JS address jump if SF = 1 JS 2050

JNS address jump if SF = 0 JNS 2050

JA address jump if CF=0 and ZF=0 JA 2050

JNBE address jump if CF=0 and ZF=0 JNBE 2050

JAE address jump if CF=0 JAE 2050

JNB address jump if CF=0 JNB 2050

JBE address jump if CF = 1 or ZF = 1 JBE 2050

JNA address jump if CF = 1 or ZF = 1 JNA 2050

JE address jump if ZF = 1 JE 2050

JG address jump if ZF = 0 and SF = OF JG 2050

JNLE address jump if ZF = 0 and SF = OF JNLE 2050

JGE address jump if SF = OF JGE 2050

JNL address jump if SF = OF JNL 2050

JL address jump if SF != OF JL 2050

JNGE address jump if SF != OF JNGE 2050

JLE address jump if ZF = 1 or SF != OF JLE 2050

 Opcode Operand Explanation Example

JNG address jump if ZF = 1 or SF != OF JNG 2050

JCXZ address jump if CX = 0 JCXZ 2050

LOOPE address loop while ZF = 1 and CX = 0 LOOPE 2050

LOOPZ address loop while ZF = 1 and CX = 0 LOOPZ 2050

LOOPNE address loop while ZF = 0 and CX = 0 LOOPNE 2050

LOOPNZ address loop while ZF = 0 and CX = 0 LOOPNZ 2050

8. Discuss the IN and OUT instructions in 8086.

In Instr : 2.5 marks
Out Instr: 2.5 marks

Answer: The IN and OUT instructions in the 8086 microprocessor are used for input and
output operations with I/O ports. These instructions allow the 8086 microprocessor to
communicate with external devices (like keyboards, monitors, or printers) or to transfer data
between the CPU and peripherals.

The IN instruction reads data from an I/O port into a register, while the OUT instruction
writes data from a register to an I/O port.

1. IN Instruction

The IN instruction is used to read data from an I/O port and store it into a register. The I/O
port is specified either as an immediate value (direct port address) or as a value in a register.

Syntax:
IN destination, port

 destination: A register where the data from the I/O port will be stored (e.g., AL, AX,
DX).
 port: The I/O port number from which data will be read. The port can be specified as
an immediate value (a constant) or a register.
Operation:

 The IN instruction reads a byte (if using 8-bit registers like AL) or a word (if using
16-bit registers like AX) of data from the I/O port and stores it in the specified
destination register.

Examples:

 Example 1: Reading a byte from a specific I/O port

IN AL, 0x60 ; Read a byte from I/O port 0x60 into the AL register

 This reads a byte from I/O port 0x60 and stores it in the AL register.

2. OUT Instruction

The OUT instruction is used to send data from a register to an I/O port. The I/O port is
specified either as an immediate value (direct port address) or as a value in a register.

Syntax:
OUT port, source

 port: The I/O port number where data will be written. The port can be specified as an
immediate value (a constant) or a register.
 source: A register whose data will be written to the I/O port (e.g., AL, AX, DX).

Operation:

 The OUT instruction sends a byte (if using 8-bit registers like AL) or a word (if using
16-bit registers like AX) of data from the specified register to the specified I/O port.

Examples:

 Example 1: Sending a byte to a specific I/O port

OUT 0x60, AL ; Write the byte in the AL register to I/O port 0x60

 This sends the byte stored in the AL register to I/O port 0x60.

Flags Affected by IN and OUT:

 The IN and OUT instructions do not directly affect the FLAGS register. They are purely data
transfer instructions and are primarily used to move data between the CPU and I/O ports.
9. Demonstrate the CMP instruction in 8086 and explain the same with suitable syntax
and examples.
Defn & example: 2 marks
Syntax of each: 3 marks
Answer: The CMP instruction is used to compare two operands by subtracting the source
operand from the destination operand. It does not store the result but updates the flags based
on the result of the subtraction. This allows conditional branches based on the result.

The CMP (Compare) instruction in 8086 is used to compare two operands. It subtracts the
source operand from the destination operand, but it does not store the result. Instead, the
flags in the FLAGS register are updated based on the result of the subtraction.

This instruction is typically used to set the flags for conditional jump instructions like JE,
JNE, JL, JLE, etc., which are used to make decisions based on the result of the comparison.

Syntax of the CMP Instruction:

CMP destination, source

 destination: The operand from which the source will be subtracted.

 source: The operand that will be subtracted from the destination.

The CMP instruction does not store the result of the subtraction; instead, it affects the status
flags (Zero Flag (ZF), Sign Flag (SF), Carry Flag (CF), Overflow Flag (OF), and Parity Flag
(PF)) based on the result of the subtraction.

Example: CMP AX, BX (Compares AX with BX).

If AX > BX, the carry flag is cleared. If AX = BX, the zero flag is set, and so on.

10. Implement the string instructions in 8086. Explain with examples.

Def: 1 marks
Example with expl: 4 marks
Answer: String instructions are used to manipulate strings (arrays of bytes or words). These
instructions allow efficient handling of string operations like moving, comparing, and
loading.
 MOVSB: Moves a byte from source to destination. Example: MOVSB (Moves byte
from DS:SI to ES:DI).
 MOVSW: Moves a word from source to destination. Example: MOVSW (Moves
word from DS:SI to ES:DI).
 LODSB: Loads a byte from the source (DS:SI) into AL. Example: LODSB (Loads a
byte from DS:SI into AL).
 STOSB: Stores a byte from AL into the destination (ES:DI). Example: STOSB (Stores
AL at ES:DI).
These string operations are useful for efficiently processing large amounts of data.
Example of REP with MOVSB Instruction

MOV AX, 7000H Assign source segment address to AX

MOV DS, AX Load source segment address into DS
MOV AX, 8000H Assign destination segment address to AX
MOV CX, 0E0H Move the length of the string to the counter register CX
MOV SI, 3000H Assign source index address to SI
MOV DI, 4000H Assign destination index address to DI
CLD Ensure auto-increment mode is set by clearing the direction flag
REP MOVSB Repeat the move byte from source to destination instruction CX times

Example of REPE With CMPSB Instruction

MOV AX, SEG_STRING1 Move the segment address of STRING1 to AX

MOV DS, AX Load it to DS
MOV AX, SEG_STRING2 Move the segment address of STRING2 to AX
MOV ES, AX Load it to ES
MOV SI, OFFSET_STRING1 Move the offset of STRING1 to SI
MOV DI, OFFSET_STRING2 Move the offset of STRING2 to DI
MOV CX, 020H Move the length of the strings to CX
CLD Clear the direction flag, set auto-increment mode
REPE CMPSB Compare the 020H bytes of STRING1 and STRING2,While
they are Equal,
If mismatch is found modify the flags and proceed with
further Execution

NOTE: If Both Strings are Equal,CX becomes ZERO,the ZF is set otherwise ZF is reset

Example of REPNE With SCASW Instruction

MOV AX, SEGMENT_STR Move the segment address of the String to AX
MOV ES, AX Load it to ES
MOV DI, OFFSET_STR Move the offset of String to DI
MOV CX, 020H Move the length of the String to CX
MOV AL, WORD_TO_FIND The word to be scanned for is loaded into AL
CLD Clear the direction flag
REPNE SCASW Scan the 020H words of the String until a match to the
word is found

Example of LODSB Instruction

MOV CX, 10 Set CX to the number of bytes to be read

MOV SI, OFFSET_STR Set SI to point to the start of the string
MOV DI, OFFSET_BUF Set DI to point to the destination buffer
CLD Clear the direction flag for auto-increment

READ_LOOP:
LODSB Load a byte from the memory location pointed to by SI into AL,
and increment SI
STOSB Store the byte in AL at the memory location pointed to by DI,
and increment DI
LOOP READ_LOOP Decrement CX and loop back if CX is not zero
HLT Halt the processor (assembly language instruction for stopping
execution)
 UNIT 3 ARM PROCESSOR ARCHITECTURE
Answer Key
Two Marks Questions

1. Define the Cortex-M architecture.

Cortex-M architecture: A low-power, high-performance microprocessor architecture
designed for embedded systems. It is based on the ARM architecture and provides a
range of features for efficient execution of real-time applications.

2. Paraphrase the purpose of a pipelined architecture in Cortex-M processors.

Pipelined architecture: It enhances processor performance by allowing simultaneous
execution of multiple instructions, where each instruction is in a different stage of
execution (fetch, decode, execute).

3. List two advantages of the Cortex-M block diagram design.

Cortex-M block diagram: A high-level representation of the main components in the
Cortex-M processor, such as the core, memory, peripherals, and communication
buses.

4. Exemplify the term memory address map.

Memory address map: A mapping of memory locations used by the processor,
assigning address ranges to different types of memory (RAM, ROM, I/O devices).

5. Illustrate the role of the bus matrix in the Cortex-M processor.

Bus system: A communication channel that connects the processor core, memory,
and peripherals to transfer data. It is essential for system performance.

6. Summarize the functions of the DWT (Data Watchpoint and Trace) in Cortex-
M.
 DWT (Data Watchpoint and Trace): Monitors data accesses and generates events
based on specific conditions, useful for debugging and performance profiling.

7. Define t is the function of the TPIU (Trace Port Interface Unit)

TPIU (Trace Port Interface Unit): Allows for external trace equipment to access trace
data from the processor, facilitating real-time debugging and profiling.

8. List two features of exception handling in Cortex-M processors.

Exception handling: Involves handling events such as interrupts and errors, which
cause the processor to suspend its current task and execute specific routines.

9. What does the debug system in Cortex-M processors include?

Debug system: Includes components like the AHB access port, FPB, DWT, ITM,
ETM, and TPIU that aid in debugging, tracing, and monitoring the execution of
code.

10. Discuss the importance of interrupt handling in embedded systems.

Interrupt handling: The process by which the processor responds to an interrupt by
suspending its current task and executing an interrupt service routine (ISR).
Three Marks Questions
1.Discuses the typical number of pipeline stages in a Cortex-M processor.
For each stage 1 mark.
The Cortex-M processor typically uses a 3-stage or 5-stage pipeline (depending on the
model), including stages such as :
instruction fetch,
decode,
execute,
memory access, and
write-back.

2. Illustrate the bit-banding in Cortex-M architecture.

Bit-banding allows individual bits of a memory or peripheral region to be accessed as if they
were independent 32-bit words, 1 mark.
enabling faster bit-level manipulation. 1 mark.
It is available in the bit-band region of SRAM and peripheral memory. 1 mark.

3. Explain the system stack architecture of Cortex-M.

The system stack in Cortex-M processors is used to store context information during
interrupt and exception handling.
It is managed using a stack pointer (SP) 1 mark.
operates in Main Stack Pointer (MSP) 1 mark.
Process Stack Pointer (PSP) modes. 1 mark.

4. Demonstrate the purpose of the bus system in a Cortex-M processor.

The bus system in a Cortex-M processor facilitates communication between the

processor core, 1 mark.
memory, and peripherals, 1 mark.
using different buses such as the AHB and APB to optimize performance and power
consumption. 1 mark.

5.Discuss the debug features available in Cortex-M processors.

Write any three give 3 marks.

Answer: Cortex-M processors support several debugging features, including:

AHB Access Port (AHB-AP): Provides access to the processor's internal registers and
memory.
FPB (Flash Patch and Breakpoint Unit): Allows setting breakpoints in code.
DWT (Data Watchpoint and Trace Unit): Tracks changes to specific data values.
ITM (Instrumentation Trace Macrocell): Sends trace data for software analysis.
ETM (Embedded Trace Macrocell): Provides detailed program execution trace.
TPIU (Trace Port Interface Unit): Transmits trace data to an external debugger.
6. Distinguish between interrupt and exception.
Reason 2mark with example give 1 mark
An interrupt is an asynchronous event typically caused by external hardware,
while an exception is a synchronous event generated by the processor itself
(e.g., divide by zero, illegal instructions).

7. Discuss the behavior of the Cortex-M processor during an interrupt.

When an interrupt occurs, the Cortex-M processor automatically saves the
current context (register values) to the stack, 1 mark
disables further interrupts (optional), and 1 mark
transfers control to the corresponding interrupt handler. 1 mark

8.Outline the concept of vector table in Cortex-M processors.

The vector table stores addresses for interrupt and exception handlers. 1 mark
It is located at a fixed address (e.g., 0x00000000 for the reset vector) and 1 mark
contains the starting addresses for the handling routines. 1 mark

9. Demonstrate the role of the System Control Block (SCB) in Cortex-M processors.
Answer: The SCB manages the system control functions, 1 mark
including interrupt handling, system exceptions, 1 mark
system reset, and configuration of the vector table. 1 mark
It also provides status registers like the CPUID and AIRCR.

10. Explain what happens during exception or interrupt handling in Cortex-M

processors.
When an exception or interrupt occurs, the processor:
Suspends the current execution. 1 mark
Pushes the current state (registers) onto the stack. 1 mark
Jumps to the appropriate exception/interrupt handler based on the vector table. 1 mark
After handling, the processor pops the saved state from the stack and resumes execution.
 Five Marks Questions
1. Explain the Cortex-M block diagram and discuss its significance in embedded
applications.

Block Diagram-2 marks

Function -3 marks

The Cortex-M block diagram typically includes key components such as the core
processor, interrupt controller, system control unit, and debug interfaces. The major
sections are:
 ARM Cortex-M Core: This is the main processing unit that executes
instructions.
 NVIC (Nested Vectored Interrupt Controller): Handles interrupts and
prioritizes them.
 System Control Unit (SCU): Manages power and clock functions for the
processor.
  Memory Protection Unit (MPU): Provides access control for different regions
of memory.
 Debug Interfaces: Include features like the Embedded Trace Macrocell (ETM)
for real-time tracing and Instrument Trace Macrocell (ITM) for sending debug
information.
Significance in Embedded Applications: The Cortex-M block diagram is significant
because it provides a well-structured approach to real-time processing, power
efficiency, and low-latency interrupt handling—key requirements in embedded
systems. It is commonly used in applications like automotive control systems,
wearable devices, and IoT devices due to its low power consumption and high
processing speed.

2. Demonstrate the working of the pipelined architecture in Cortex-M and how it

enhances processing efficiency.

Block Diagram-2 marks

Function -3 marks

Cortex-M processors employ a 3-stage pipeline architecture (fetch, decode, execute),

which increases the processor's efficiency by allowing multiple instructions to be
processed simultaneously in different stages of execution:
 Fetch: The instruction is fetched from memory.
  Decode: The instruction is decoded into control signals.
 Execute: The decoded instruction is executed.
How it enhances processing efficiency:
 Parallel Execution: By using a pipeline, multiple instructions are processed at
the same time in different stages, minimizing idle processor time.
 Reduced Latency: The processor can begin executing the next instruction while
the current one is still in a different pipeline stage, speeding up overall
performance.
 Instruction Throughput: The overall throughput increases as the processor can
fetch, decode, and execute more instructions per cycle.

3. Discuss the role of the memory address map and the impact of memory
endianness in system performance.

Memory Address Map: It defines how memory addresses are allocated to different
components such as RAM, ROM, peripheral registers, and special function registers.
This map enables efficient access to various memory segments, contributing to
overall system performance. 2 marks
Impact of Memory Endianness:
Big Endian and Little Endian refer to how byte sequences are stored in memory. In
Big Endian, the most significant byte is stored first, whereas in Little Endian, the
least significant byte is stored first. 1 mark
System Performance: The correct handling of endianness is crucial for performance,
especially when communicating with external devices. Misaligned endianness can
cause overhead due to extra conversion cycles or may lead to incorrect data
interpretation. 1 mark
Hardware Design: Some systems are optimized for a specific endianness, and having
mismatched configurations between devices or memory can lead to inefficiencies in
data transfers. 1 mark

4. Illustrate the concept of bit banding and explain how it improves memory
access efficiency.

Bit Banding allows individual bits in a word-aligned memory region to be accessed

directly rather than dealing with the whole word. In the Cortex-M architecture, a bit-
 band region maps a 32-bit word into a bit-level address space, enabling atomic bit-
level operations. 2 marks
How it improves memory access efficiency:
 Faster Bit Manipulation: Instead of loading and manipulating a whole 32-bit
word, only the specific bit is accessed and altered, making bit-level operations
more efficient. 1 mark
 Atomic Operations: Bit banding ensures that bitwise operations are atomic,
meaning they can be performed without interruption, which is critical for
embedded applications like flag settings or status registers. 1 mark
 Reduced Processing Overhead: By enabling direct bit-level addressing, bit
banding reduces the need for complex bitwise masking or shifting operations,
improving execution speed. 1 mark

5. Explain the debug system components (AHB, FPB, DWT, ITM, ETM, TPIU)
and their significance in debugging embedded applications.

For Each component explanation - 1 mark

The debug system in Cortex-M processors involves several key components:
 AHB (Advanced High-performance Bus): This is a bus that connects the debug
components to the rest of the processor and peripherals, providing high-speed
data transfer for debugging operations.
 FPB (Flash Patch and Breakpoint Unit): This unit allows setting breakpoints in
the code, patching code during runtime, and managing execution flow for
debugging.
 DWT (Data Watchpoint and Trace Unit): Monitors specific memory addresses
and can trigger events (e.g., breakpoints) when certain data conditions are met,
useful for tracking variable values during execution.
 ITM (Instrumentation Trace Macrocell): Provides trace information about the
application by sending debug information to a host debugger.
 ETM (Embedded Trace Macrocell): Provides real-time program flow tracing,
recording the execution path of instructions, which is helpful for performance
analysis and bug tracking.
 TPIU (Trace Port Interface Unit): Acts as a bridge between the debug system
and external trace capture tools, enabling the transfer of trace data from the
processor to an external device.
 Significance in Debugging:
 These components provide a comprehensive debugging solution, enabling
real-time trace, breakpoints, watchpoints, and data monitoring. This
significantly improves debugging efficiency by allowing developers to capture
fine-grained execution details, track performance issues, and troubleshoot
embedded applications without halting the system.

6. Illustrate the System Stack Architecture of Cortex-M and Discuss How it

Manages Interrupts.
Block Diagram-2 marks
Function -3 marks
System Stack Architecture
The Cortex-M processors use a stack-based architecture to manage subroutine calls
and interrupts efficiently. They typically have two stacks:
1. Main Stack Pointer (MSP): Used by default and during exception handling.
2. Process Stack Pointer (PSP): Used by threads in an OS environment.
Diagram:

Interrupt Management
1. Automatic Context Saving: When an interrupt occurs, the processor
automatically saves critical registers (R0-R3, R12, LR, PC, and xPSR) onto the
stack.
2. Vector Table: Interrupts are managed through a vector table that maps interrupt
requests to their handlers.
 3. Nested Vectored Interrupt Controller (NVIC): The NVIC allows prioritization
and nesting of interrupts.
Key Steps:
 Save context on the stack.
 Jump to the interrupt service routine (ISR).
 Restore context from the stack upon ISR completion.

7. Compare and Contrast the Functions of the Bus System and the Bus Matrix in
Cortex-M Processors.

Bus System 2 marks

 Purpose: Transfers data between the processor core and peripherals/memory.
 Architecture: Often single or dual-bus systems in simple designs like Cortex-
M0.
 Efficiency: Can be a bottleneck due to shared paths for all transactions.
Bus Matrix 2 marks
 Purpose: Enables parallel data transactions between multiple masters (e.g.,
CPU, DMA) and slaves (e.g., memory, peripherals).
 Architecture: A crossbar switch connecting multiple input and output buses.
 Efficiency: Improves performance by allowing simultaneous transactions.
Comparison Table 1 mark

Feature Bus System Bus Matrix

Design Simple shared path Crossbar switch

Performance Limited by contention Parallel transactions

Scalability Less scalable Highly scalable

8. Discuss the Process of Exception and Interrupt Handling in Cortex-M,

Highlighting the Importance of Conditional Execution.
 Exception and Interrupt Handling - 3 Marks
1. Triggering: Exceptions or interrupts are triggered by events such as peripheral
requests, errors, or software instructions.
2. Vector Table: The processor looks up the vector table to locate the ISR.
3. Context Saving: Critical registers are automatically pushed onto the stack.
4. ISR Execution: The processor executes the ISR to handle the event.
5. Return: Context is restored, and normal execution resumes.
Conditional Execution 2 Mark
 Cortex-M uses the IT (If-Then) instruction to execute instructions
conditionally.
 Reduces branch instructions, improving performance.
 Critical in ISRs to selectively execute tasks based on conditions.

9. Evaluate the Significance of the Trace Components (ETM and ITM) in

Debugging and Performance Analysis.

Embedded Trace Macrocell (ETM) 1 Mark

 Provides instruction-level trace to monitor program execution in real-time.
 Essential for analyzing code flow without halting the processor.
Instrumentation Trace Macrocell (ITM) 1 Mark
 Supports event and variable tracing.
 Sends debug messages and data over a trace port.
Significance: 1 Mark
 Identifies bottlenecks in performance.
 Debugs hard-to-reproduce issues, especially in real-time systems.
 Reduces debugging time by providing detailed insights.
Diagram: 2 Marks
10. Examine a Scenario Where Conditional Execution in Cortex-M Processors
Optimizes Code Performance.
Scenario: Real-Time Control System - 2 Marks
 Task: In a motor control application, an ISR must read sensor data and adjust motor speed.
 Optimization: Using conditional execution (e.g., IT instructions), the ISR can skip
unnecessary computations based on sensor thresholds.
Code Snippet: 2 Marks
CMP R0, #THRESHOLD ; Compare sensor data with threshold
IT LT ; Execute next instruction if Less Than
MOVLT R1, #LOW_SPEED ; Set motor to low speed if condition is met
Benefits: 1 Mark
 Avoids branching, reducing instruction cycles.
 Improves ISR response time, ensuring real-time performance.
 UNIT 4 ARM PROCESSOR PROGRAMMING
Two Marks Questions. Course
Marks Level
Outcome

1. 2 CO4 K2
The two states of operation of ARM processor are, ARM state and
thumb state.
ARM state Thumb state
32 bit operations only Can perform 16-bit half
word
Operations
High performance Higher instruction code
density

2. The advantages of Assembly language program are 2 CO4 K1

 An assembly language program provides complete as well as
precise control of the available hardware resources.
 When writing a program in a high level language, the user is
mostly unaware of the underlying hardware capabilities,
which can lead to highly inefficient implementation.
 Programming in assembly language also gives the user
complete understanding of the system architecture.
3. The different fields of an instruction are opcode,operand, mnemonic 2 CO4 K2
and label.

The left-most field called label is an optional field with unique

symbolic representation in an assembly instruction.
The next field is called the opcode field, which
contains the instruction or the opcode. The opcode field is a unique
symbolic representation of the instruction’s machine code, which is
used by the processor for execution and is a mandatory field.
Next to the opcode field is the operand field that might contain a
different number of operands.
4. The MOV instruction is used to transfer data within the 2 CO4 K2
processor, i.e., between different registers or an immediate value to
a register. On the other hand, LDR and STR instructions allow data
to be transferred between processor and memory. The load register,
LDR, instruction is used to transfer data from memory to the
processor register, while store register, STR, instruction is used to
transfer data from processor register to memory.
5. Instruction encoding is the process of assigning a unique binary 2 CO4 K1
codeword to each assembly instruction. One of the main jobs of an
assembler is to translate each assembly instruction to an equivalent
codeword. Some of the assembly instructions are encoded to 16-bit
codewords, while some other instructions are encoded using 32bit
codewords.
6. The bitwise operations implemented by shift, rotate, and logical 2 CO4 K2
instructions are grouped together. The bitfield instructions operate
on a group of adjacent bits and differ from the instructions involving

1
 bitwise operations, which can operate on individual bits and do not
have any adjacency requirement.
7. The special rotate right extended (RRX) instruction has a slightly 2 CO4 K2
different behavior from the usual rotate operations. One key
difference is that no count is specified and this instruction always
rotates by one bit. Second, 1 bit rotation in RRX involves the C flag
as part of the rotation. The LSB of the register moves to C flag and
the original value of C flag enters the MSB of the register.
8. A 32-bit word object will result in an aligned word access if the first 2 CO4 K2
two bits of its starting address are zero or if it is divisible by 4.
Otherwise, the 32-bit data access is unaligned. Usually aligned
memory accesses are faster than the unaligned accesses. But on the
other hand, memory is better utilized with unaligned access. As a
result, there is a tradeoff between memory size required for certain
data and the speed at which this data can be accessed by the
processor.
9. The rules to be followed using stack are, 2 CO4 K2
 The push and pop operations should always be performed
inside the memory region specified for stack.
 The number of push operations should always have a
matching number of pop operations following a specified
order.
10. The special registers used in ARM processor are, 2 CO4 K1

Three Marks Questions.

*Q.Nos. 1- 5 first half Portion of unit syllabus and Q.No 6 - 10 Course
Marks Level
from the second half portion of syllabus Outcome

1. The two types of development environments used in KEIL tool are CO4 K2
software and hardware levels.

 Keil MDK is the complete software development

1
environment for a range of Arm Cortex-M based
microcontroller devices.

 KEIL tools provide two types of development environments. 1

One environment configuration allows the user to simulate
the ARM Cortex-M microcontroller at the software level.

2
  The second environment enables the user to download, run, 1
and debug the program on an actual hardware platform.

2. The instruction used to transfer data from memory location to CO4 K3

register, register to memory location and also register to register are,
 Data Transfer from Memory to Register: MOV AX, 1
[address] ; Load data from memory address into register AX
 Data Transfer from Register to Memory: MOV [address],
1
AX ; Store data from register AX into memory address
 Data Transfer from Register to Register: MOV BX, AX ;
Transfer data from register AX to register BX 1
3. A pseudo-operation, commonly called a pseudo-op, is an instruction 1 CO4 K3
to the assembler that does not generate any machine code.
The assembler resolves pseudo-ops during assembly, unlike 2
machine instructions, which are resolved only at runtime.
4. Implementation of division by 8 using ALP shift instructions for CO4 K3
ARM processor is
LSR R4, R3, #3 ; R4 = R3 << 3 1
ASR R5, R3, #3 ; R5 = R3 << 3 1
LSR – Logical shift right instruction
ASR – Arithmetic shift right instruction 1
5. To rotate left its contents by 3 bits without using left shift instruction CO4 K3
is performed by,

ROR R2, R2, #29 ; Equivalent to rotate left by 3 bits

2
; R2 = 64 after execution
It is important to realize that due to the barrel shifter the rotate right
operation for 29 bit positions takes one processor clock cycle and no 1
issue regarding execution performance inefficiency arise.
6. ALP for setting the 4th bit of register R0 using ARM processor is CO4 K3
given below.

MOV R1, #1 1
LSL R1, #4 ; R1 = 1 << 4 1
ORR R0, R0, R1 ; R0 = R0 | R1 1
7. The operation of the ALP instruction MLA R1, R2, R3, R5 of ARM CO4 K2
processor is

MLA R1, R2, R3, R5 ; Multiply with accumulate, 1

; R1=(R2 x R3)+R5 1
It is important to remember that only the least significant 32 bits of 1
the result are written to a destination register.
8. To Test whether 0x7FFF FFFF is greater than 0x8000 0000 deciding CO4 K3
whether these are signed or unsigned numbers.
The integer variables are represented in a signed and unsigned 1
manner. The positive and negative values are differentiated by using
the sign flag in signed numbers. The unsigned numbers do not use
3
 any flag for the sign, i.e., only positive numbers can be stored by the
unsigned numbers.
If signed, then 0x7FFF FFFF is greater than 0x8000 0000 but when
these numbers are interpreted as unsigned numbers, 0x8000 0000 is 2
greater than 0x7FFF FFFF.
9. The ways to perform a branch operation without using any of the CO4 K2
four branch instructions(B, BL, BX, BLX) are,
CMP R0, #0 ; Compare R0 with 0 1

LDR R1, =target_address ; Load target address into R1

1
ADDNE PC, PC, R1 ; If not equal, add R1 to PC (effectively jump)
It is also possible to implement branch operations with MOV, LDR,
and POP instructions by using PC (R15) as the destination register 1
with these instructions.
10. The need for applying restrictions to the IT block instruction CO4 K2
execution is
 A branch or any instruction that modifies the PC must either 1
be outside an IT block or must be the last instruction inside
the IT block.
 Do not branch to any instruction inside an IT block, except 1
when returning from an exception handler.
 All conditional instructions except conditional branches must 1
be inside an IT block.
 Each instruction inside the IT block must specify a condition
code suffix that is either the same or logical inverse of the
condition code used by the IT instruction.
 The first conditional instruction inside the IT block should
always use the condition code the same as the one used by
the IT instruction itself

Five Marks Questions.

*Q.Nos. 1- 5 first half Portion of unit syllabus and Q.No 6 - 10 from Course
Marks Level
the second half portion of syllabus Outcome

1 Sequence of steps that are followed after reset operation in ARM Cortex CO4 K2
M4:
Memory map is 2

4
we have a code region, where we are going to write our final binary.
That memory is starting from 0x00000000 to 0x1FFFFFFF. The code
region has the final output of our program (.hex or .bin or etc). SRAM
will be having stack, heap, global RW variables, and Static variables,
etc.

5
The final output of our program will be ordered in this way by using a
linker. So, the vector table is starting from 0x00000000 by default.
The vector table will contain all the locations of the exception and
interrupt ISR. As Cortex-M4 has below exceptions, interrupts and those
things are ordered in the below image.

6
 The 0x00000000 address contains the initial Stack Pointer Value. Then
0x00000004 has the address of the reset handler.

After Reset key is pressed, the following steps are to be followed.

1. PC (Program Counter) will be loaded with 0x00000000. So will
start from the address 0x00000000.
2. Since the address has an Initial Stack Pointer value, It will be
fetched to the MSP (Main Stack Pointer). So, that value will be
the starting of the stack.
3. Then PC will be loaded with the Reset handler’s address.
4. After that, the reset handler will perform the below operations.
1. Initialize the system.
2. Copy the Initialized global variable, and static
variable (.data) to SRAM.
3. Copy the Un-initialized data (.bss) to SRAM and
initialize it to 0.
4. It Calls main().
This is how main() is getting called while power-up or pressing the
reset button.
2
2. ARM cortex M4 addressing modes: CO4 K2
2
ARM register set.

7
 R0 to R12 are the general-purpose registers.
R13 is reserved for the programmer to use it as the stack
pointer.
R14 is the link register which stores a subroutine return
address.
R15 contains the program counter and is accessible by the
programmer.

Condition code flags in CPSR:

N - Negative or less than flag
Z - Zero flag
C - Carry or borrow or extended flag
V - Overflow flag
The least-significant 8-bit of the CPSR are the control bits
of the system.
The other bits are reserved.

ARM addressing Modes

There are different ways to specify the address of the operands for any 3
given operations such as load, add or branch. The different ways of
determining the address of the operands are called addressing modes.
The different addressing modes of ARM processor fit into a single word
(32 bits).

Name Alternative Name ARM Examples

8
 ------------------------------------------------------
Register to register Register direct MOV R0, R1
------------------------------------------------------
Absolute Direct LDR R0, MEM
------------------------------------------------------
Literal Immediate MOV R0, #15
ADD R1, R2, #12
------------------------------------------------------
Indexed, base Register indirect LDR R0, [R1]
------------------------------------------------------
Pre-indexed, Register indirect LDR R0, [R1, #4]
base with displacement with offset
------------------------------------------------------
Pre-indexed, Register indirect LDR R0, [R1, #4]!
autoindexing pre-incrementing
------------------------------------------------------
Post-indexing, Register indirect LDR R0, [R1], #4
autoindexed post-increment
------------------------------------------------------
Double Reg indirect Register indirectLDR R0, [R1, R2]
Register indexed
------------------------------------------------------
Double Reg indirect Register indirect LDR R0, [R1, R2,
LSL #2]
with scaling indexed with scaling
------------------------------------------------------
Program counter relative LDR R0, [PC,
#offset]
------------------------------------------------------

3. The code for finding minimum and maximum values in numeric array is 5 CO4 K3
given as,

Logic – 1 mark

Program-4 marks

print("""@ Min-Max.s
@ Find minimum and maximum values in array NUM1

.data
NUM1: .word 82, 45, 93, 17, 64, 31, 78, 25, 59 @ Array of
numbers
N: .word 9 @ Length of array
MIN: .word 0 @ Variable to store minimum
MAX: .word 0 @ Variable to store maximum

.text
.global _start
_start:

9
 LDR R0, =NUM1 @ Load address of array
LDR R1, [R0] @ Load first element
MOV R2, R1 @ Initialize MIN with first element
MOV R3, R1 @ Initialize MAX with first element
LDR R4, =N @ Load address of N
LDR R4, [R4] @ Load value of N
MOV R5, #1 @ Initialize counter i = 1

loop:
CMP R5, R4 @ Compare i with N
BGE endloop @ If i >= N, exit loop

LSL R6, R5, #2 @ R6 = i * 4 (offset for word-aligned array)

LDR R7, [R0, R6] @ Load NUM1[i]

@ Check for minimum

CMP R7, R2 @ Compare current element with MIN
BGE checkmax @ If current >= MIN, skip to max check
MOV R2, R7 @ Update MIN

checkmax:
CMP R7, R3 @ Compare current element with MAX
BLE continue @ If current <= MAX, continue
MOV R3, R7 @ Update MAX

continue:
ADD R5, R5, #1 @ Increment counter
B loop @ Repeat loop

endloop:
LDR R0, =MIN @ Load address of MIN
STR R2, [R0] @ Store minimum value
LDR R0, =MAX @ Load address of MAX
STR R3, [R0] @ Store maximum value

@ Exit program
MOV R7, #1 @ Exit syscall
SWI 0 @ Software interrupt

.end""")

4. Register accesses CO4 K2

16-bit Thumb instructions can access only a limited set of registers.

There are also some restrictions on the use of special-purpose registers
by ARM and 32-bit Thumb instructions.
2

Most 16-bit Thumb instructions can only access R0 to R7. Only a

small number of these instructions can access R8-R12, SP, LR, and
PC. Registers R0 to R7 are called Lo registers. Registers R8-R12, SP,
10
 LR, and PC are called Hi registers.

All 32-bit Thumb instructions can access R0 to R12, and LR.

However, apart from a few designated stack manipulation instructions,
most Thumb instructions cannot use SP. Except for a few specific
instructions where PC is useful, most Thumb instructions cannot use
PC.

In ARM state, all instructions can access R0 to R12, SP, and LR, and
most instructions can also access PC (R15). However, the use of the
SP in an ARM instruction, in any way that is not possible in the
corresponding Thumb instruction, is deprecated. Explicit use of the PC
in an ARM instruction is not usually useful, and except for specific
instances that are useful, such use is deprecated. Implicit use of the PC,
for example in branch instructions or load (literal) instructions, is
never deprecated.

The MRS instructions can move the contents of a status register to a

general-purpose register, where they can be manipulated by normal
data processing operations. You can use the MSR instruction to move
the contents of a general-purpose register to a status register.

3
Register accesses
16-bit Thumb instructions can access only a limited set of registers.
There are also some restrictions on the use of special-purpose registers
by ARM and 32-bit Thumb instructions.

Most 16-bit Thumb instructions can only access R0 to R7. Only a small
number of these instructions can access R8-R12, SP, LR, and PC.
Registers R0 to R7 are called Lo registers. Registers R8-R12, SP, LR,
and PC are called Hi registers.

All 32-bit Thumb instructions can access R0 to R12, and LR. However,
apart from a few designated stack manipulation instructions, most
Thumb instructions cannot use SP. Except for a few specific
instructions where PC is useful, most Thumb instructions cannot use
PC.

11
 In ARM state, all instructions can access R0 to R12, SP, and LR, and
most instructions can also access PC (R15). However, the use of the SP
in an ARM instruction, in any way that is not possible in the
corresponding Thumb instruction, is deprecated. Explicit use of the PC
in an ARM instruction is not usually useful, and except for specific
instances that are useful, such use is deprecated. Implicit use of the PC,
for example in branch instructions or load (literal) instructions, is never
deprecated.

The MRS instructions can move the contents of a status register to a

general-purpose register, where they can be manipulated by normal data
processing operations. You can use the MSR instruction to move the
contents of a general-purpose register to a status register.

5. A software interrupt instruction (SWI) causes a software interrupt CO4 K2

exception, which provides a mechanism for applications to call
operating system routines.
Syntax: SWI {<cond>} SWI_number

SWI Software lr_svc=address of instruction following the

interrupt SWI
spsr_svc=cpsr
pc=vectors+0x8
cpsr mode= SVC
cpsr I=I (mask IRQ interrupt)

When the processor executes an SWI instruction, it sets the program 2

counter pc to the offset 0xB in the vector table.
The instruction also forces the processor mode to SVC, which allows an
operating system routine to be called in a privileged mode.
Each SWI instruction has an associated SWI number, which is used to
represent a particular function call or feature.
The example below shows an SWI call with SWI number 0x123456,
used by ARM toolkits as a debugging SWI.
PRE
cpsr=nzcVqift_USER
3
pc=0x00008000

12
 lr=0x003fffff ;
lr=r14
r0=0x12
0x00008000 SWI 0x123456
POST
cpsr=nzcVqIft_SVC
spsr= nzcVqift_USER
pc=0x000000008
lr=0x00008004
r0=0x12
Since SWI instructions are used to call operating system routines, it is
required some form of parameter passing. This achieved by using
registers. In the above example, register r0 is used to pass parameter
0x12. The return values are also passed back via register.

6. (i) r0=0x80000004 and r1=0x80000004. CPSR is not 5, CO4 K3

updated. each
1
(ii) Before execution of the instruction, r1=0x80000004=1000 mark
0000 0000 0000 0000 0000 0000 0100 in binary. After 1
bit logical shift left(LSL), the value is 0000 0000 0000
0000 0000 0000 0000 1000 which is copied to r0. After the
execution of the instruction, r0=0x00000008 and
r1=0x80000004. CPSR is not updated.
(iii) Before execution of the instruction, r1=0x80000004=1000
0000 0000 0000 0000 0000 0000 0100 in binary. After 1
bit logical left shift (LSL), the value is 0000 0000 0000
0000 0000 0000 0000 1000 which is copied to r0.Most
significant bit (MSB) is copied to the carry flag and carry
flag is set. After the execution of the instruction,
r0=0x00000008 and r1=0x80000004. CPSR is updated.
(iv) NOT of r1 is 0111 1111 1111 1111 1111 1111 1111
1011=0x7ffffffb is copied to ro. After the execution,
r0=0x7ffffffb and r1=0x80000004. CPSR is not updated.
(v) Before execution of the instruction, r1=0x80000004=1000
0000 0000 0000 0000 0000 0000 0100 in binary. After 1
bit logical shift right (LSR), the value is 0100 0000 0000
0000 0000 0000 0000 0010 which is copied to r0. After the
execution of the instruction, r0=0x40000002 and
r1=0x80000004. CPSR is not updated.

13
7. Logic – 2 marks 5 CO4 K3

Program – 3 marks

AREA CountOneZero, CODE, READONLY

ENTRY

LDR R0, =0X40000000

LDR R1, [R0] MOV R2, #32

AGAIN RORS R1, #1

BCS ONES

ADD R3, R3, #1

B NEXT

ONES ADD R4, R4, #1

NEXT ADD R2, R2, #-1

CMP R2, #0

BNE AGAIN

ADD R0, R0, #4

STRB R3, [R0]

STRB R4, [R0,#1]

MOV R0, #0X18

LDR R1, =0X20026

SVC #0123456

END

8. Explanation 2 marks 5 CO4 K2

Working – 3marks
The stack is part of main memory and is used to store data objects in
last-in-firstout buffering format. In ARM Cortex-M processor, the stack
always operates on 32-bit data. The stack pointer contains an address
that points to a 32-bit data at the top of the stack. As we push data
objects onto the stack, the addresses are decremented. The most recent
item known as the “top of the stack” is actually the data object stored at
the lowest address. Hence, the stack grows in the downward direction

14
and we say that it employs a full-descending stack management.
The assembly instructions to access the stack memory region are PUSH
and POP. A PUSH instruction copies one or more data objects from a
register or a list of registers onto the stack, whose starting address is
determined by SP. The POP instruction works in the opposite manner.
The general syntax for these two instructions is given below.
To push a data object on the stack, the stack pointer is first decremented
by 4, and then the 32-bit information is stored at the address specified
by SP.
To pop a
data object from the stack, the 32-bit information pointed to by SP is
first retrieved, and then the stack pointer is incremented by 4. The SP
register points to the last item pushed, which is also the next item to be
popped. It is possible to use SP instead of R13, when writing an
assembly program. It is important to note that with PUSH and POP
instructions SP gets adjusted automatically.
In the case of PUSH, the register or set of registers is source operand
while the memory region reserved for the stack in the RAM is the
destination. On the other hand, for POP instruction a register or set of
registers is the destination and memory is the source. Please note that
the contents of the source operands are not changed, while those of the
destination operands get updated.

Example instructions are,

PUSH {R0} ; push the 32-bit value of R0 onto the stack
PUSH {R1} ; push the 32-bit value of R1 onto the stack
PUSH {R2} ; push the 32-bit value of R2 onto the stack
POP {R3} ; retrieve a 32-bit value from the stack and store in R3
POP {R4} ; retrieve a 32-bit value from the stack and store in R4
POP {R5} ; retrieve a 32-bit value from the stack and store in R5

As shown in figure below, The instruction PUSH {R0} first decrements

SP by 4, and then stores the contents of R0 to a memory location
pointed to by the updated value of SP. The right-most part of the figure
shows the stack after the push occurs three times.
The stack contains the numbers 10, 20, and 30 with 30 on the top of the
stack.
The instruction POP {R3} first loads the value from the stack memory
pointed to by SP into R3, and then increments SP by 4. After the pop
occurs three times, the stack returns to its original state and registers R3,
R4, and R5 contain 30, 20, and 10, respectively.

Figure: Illustration of stack working.

15
9. i. Logic – 1 mark 2 CO4 K3
Program-1 mark
LDR r4,=b ; get address for b
LDR r0,[r4] ; get value of b

LDR r4,=c ; get address for c

LDR r1,[r4] ; get value of c

ADD r2,r0,r1 ; compute partial result

LDR r4,=a ; get address for a

LDR r0,[r4] ; get value of a

MUL r2,r2,r0 ; compute final value for y

LDR r4,=y ; get address for y

STR r2,[r4] ; store y

ii. Logic – 1 mark 3 CO4 K3

Program-2 marks
LDR r4,=a ; get address for a
LDR r0,[r4] ; get value of a

MOV r0,r0,LSL 2 ; perform shift

LDR r4,=b ; get address for b

LDR r1,[r4] ; get value of b

AND r1,r1,#15 ; perform AND

ORR r1,r0,r1 ; perform OR

LDR r4,=z ; get address for z

STR r1,[r4] ; store value for z

10 Implementation of FIR filter in ARM assembly language 5 CO4 K3

Logic- 2 marks
Program-3 marks
16
loop initiation code
MOV r0,#0 ; use r0 for I
LDR r2,=N ; get address for N
LDR r1,[r2] ; get value of N
MOV r2,#0 ; use r2 for f
LDR r3,=c ; load r3 with base of c
LDR r5,=x ; load r5 with base of x

loop body
loop LDR r4,[r3,r0,LSL #2] ; get c[i]
LDR r6,[r5,r0,LSL #2] ; get x[i]
MUL r4,r4,r6 ; compute c[i]*x[i]
ADD r2,r2,r4 ; add into running sum f
ADD r0,r0,#1 ; add 1 to i
CMP r0,r1 ; exit?
BLT loop ; if i < N, continue ;
Finalize result
LDR r3,=f ; point to f
STR r2,[r3] ; f = result

17
 UNIT 5 ARM PROCESSOR INTERFACING
SCHEME OF EVALUATION
Two Marks Questions

1. Name the main processing unit in the TM4C123 microcontroller and its primary
role.
o The main processing unit is the ARM Cortex-M4F processor.
o Its primary role is to execute instructions, perform computations, and control
peripheral operations efficiently, including floating-point tasks.
2. Categorize the real-time applications of the TM4C123 microcontroller into
automotive, industrial, and IoT domains.
o Automotive: Vehicle diagnostics, anti-lock braking systems (ABS).
o Industrial: Motor control, process automation.
o IoT: Smart home controllers, wireless sensor networks.
3. What is polling?
o Polling is a method where the CPU continuously checks the status of a
peripheral device to determine if it requires processing.
4. Compare keypad interfacing with switch interfacing in TM4C123.
o Keypad Interfacing: Requires multiple GPIO pins and is used for multi-input
systems like 4x4 keypads.
o Switch Interfacing: Uses fewer GPIO pins and is suitable for single-control
inputs like push buttons.
5. Clarify the concept of I/O synchronization and state its necessity in
microcontrollers.
o Concept: Ensures data transfer between the CPU and peripherals aligns with
clock cycles or states.
o Necessity: Prevents data corruption and ensures peripherals operate reliably
with the processor.
6. Compare the benefits of interrupt-driven and polling methods in handling I/O
operations.
o Interrupt-Driven: CPU is free until an interrupt occurs, improving efficiency
and responsiveness.
o Polling: Simple to implement but inefficient due to constant CPU checking.
7. How is a timer used as an I/O device in microcontrollers?
 o A timer can generate precise delays, periodic signals, or act as a counter to
measure external events.
8. Write an application of a timer as an event counter.
o A timer can count pulses from a tachometer to measure the speed of a rotating
object.
9. Name the two lines used in I2C communication.
o SDA (Serial Data Line) and SCL (Serial Clock Line).

10. Categorize the types of messages supported by the CAN protocol.

o Data Frame: For transmitting data.
o Remote Frame: For requesting data.
o Error Frame: For signaling communication errors.
o Overload Frame: For temporarily stopping data transmission.

Three Marks Questions

1.Interpret the role of the Nested Vector Interrupt Controller (NVIC) in TM4C123
For each role with explanation- One mark
Interrupt Prioritization & Nesting
 NVIC supports up to 138 interrupt sources, each with programmable priority levels.
 It allows nested interrupts, meaning a higher-priority interrupt can preempt a lower-
priority one.
 Priority levels range from 0 (highest priority) to 7 (lowest priority).
Fast Interrupt Handling
 NVIC reduces interrupt latency by using a vector table, which directly stores interrupt
addresses.
 It ensures rapid context switching by automatically saving/restoring registers upon
entering/exiting an interrupt.
Efficient Power Management
 NVIC allows selective enabling/disabling of interrupts, optimizing power consumption
in embedded applications.
Support for Exception Handling
 It manages system exceptions like Hard Faults, Bus Faults, and SysTick interrupts.
 Ensures the microcontroller can recover from faults efficiently.
Interrupt Masking & Software Interrupts
 Developers can mask (disable) specific interrupts to prevent unwanted interruptions
during critical tasks.
 NVIC supports software-triggered interrupts, which can be generated manually via
code.
Vector Table Offset Control
 The vector table location can be changed dynamically, allowing the system to relocate
interrupt vectors in memory.

2.Explain the features of GPIO in the TM4C123 microcontroller.

For any 3 features - Three marks
GPIO with Pull-up/Pull-down Resistors
 Pull-up resistors ensure that system inputs remain at a stable logic level when external
devices are in high-impedance mode (disconnected state).
 When no external device is active, the pull-up resistor pulls the GPIO pin to logic high.
 If an external device becomes active, it overrides the pull-up resistor’s logic level.
 Pull-up resistors are also useful when interfacing devices that operate at different supply
voltages.
 Figure 8.2 demonstrates the use of an external pull-up resistor with an open-drain GPIO
pin.
GPIO Current Sourcing and Sinking Capability
 Each GPIO has a limited ability to source (output mode) or sink (input mode) current.
 Some advanced GPIOs allow configurable current drive levels for precise control of
power consumption and signal strength.
GPIO as Input with Higher Voltage Tolerance
 Certain microcontrollers support voltage-tolerant inputs, allowing GPIOs to accept
voltage levels higher than the operating voltage.
 For example, the TM4C123 microcontroller operates at 3.3V, but its GPIOs can tolerate
5V input signals without damage.
Additional Advanced Features
 Slew Rate Control – Regulates the transition speed of output signals to reduce
electromagnetic interference (EMI).
 Schmitt Trigger Inputs – Improves noise immunity by providing hysteresis, ensuring
stable input signal interpretation.

3.Discuss the memory-mapped peripherals in the TM4C123 microcontroller.

The TM4C123 microcontroller follows a fixed memory map, which provides up to 4GB of
addressable memory. The memory map is structured to include both on-chip memory and
peripheral address spaces. Below is a simplified description of the memory allocation in the
TM4C123 microcontroller:
Code Memory (Flash Memory): 1 mark
Size: 256KB
Address Range: 0x00000000 to 0x0003FFFF
This is where the program code is stored.
Data Memory (RAM): 1 mark
Size: 32KB
Address Range: 0x20000000 to 0x20007FFF
This is the on-chip RAM used for data storage.
Peripheral Address Space: 1 mark
After the code and data memory regions, the remaining memory addresses are allocated to
peripherals.
Each peripheral in the microcontroller has its own address range, which corresponds to
different configuration, control, status, and data registers associated with that peripheral.
In this architecture, ARM Cortex-M uses memory-mapped peripherals, meaning that
peripherals can be accessed using memory addresses, simplifying the programming and access
to peripheral devices. The first two regions in the memory map are for Flash and RAM, while
the rest is used by various peripheral modules like GPIO, timers, UARTs, etc.

4.Examine the Blind cycle method of input output synchronization.

Figure - 1 mark
Explanation - 2 marks
Blind cycle synchronization is a simple method used in I/O operations where the software waits
for a fixed time before proceeding, assuming that the hardware has completed its task. This
fixed delay is based on the maximum possible time the hardware may take. Unlike other
synchronization methods, blind cycle does not check the hardware status; it simply waits and
proceeds. While this method is easy to implement and works well for predictable hardware
responses, it can be inefficient if the hardware completes its task faster than the set delay,
leading to wasted processing time. It is best suited for systems where hardware response time
is consistent.

5. Demonstrate direct keypad interfacing method in the TM4C123 microcontroller.

Figure 1 mark
Explanation 2 marks

In direct interface each keypad switch (e.g., push button, slide switch, toggle switch, etc.) is
interfaced directly to a dedicated digital GPIO pin of the microcontroller. This type of
interfacing requires n number of GPIO pins for n switches. One key advantage of this
interfacing approach is its capability to detect all possible combinations of multiple
simultaneous switch presses. For n switches, the possible combinations are 2 n. This method
can be used for specific switch combination that needs to be configured or when multiple
simultaneous key presses are required to be recognized. The negative aspect of this approach
is the fact that it is prohibitively demanding in terms of GPIO pins. Some of the possible uses
of this approach are modifier keys (e.g., Shift, Ctrl, Alt, Func keys on a computer keyboard) as
well as in the music keyboards. Figure illustrates the direct hardware interfacing of an eight
switch keypad

6. Interpret the Interrupt-Driven Keypad Interfacing in TM4C123 microcontroller.

Figure - 2 marks
Explanation - 1 mark

The interrupt-driven keypad interface requires additional hardware modifications for proper
functioning. Figure illustrates the hardware needed to implement interrupt-driven interfacing
for a matrix-type keypad. For this interface to work correctly, an interrupt must be generated
each time a key is pressed. To achieve this, four diodes are used, as shown in Figure, which
help in uniquely identifying the pressed key. During initialization, logic 1 is applied to all four
columns. When a key is pressed, a low-to-high transition is generated at PF4, triggering an
interrupt. The keypad scanning then takes place as part of the Port F Interrupt Service Routine
(ISR). It is important to note that the keypad scan function is executed only once for each key
press.
7. Compare polling and interrupt-driven systems in terms of efficiency.
For any three comparisons - Three marks

Aspect Polling Interrupt-Driven

Less efficient, as the CPU keeps

More efficient, as the CPU is interrupted
CPU Utilization checking for events even when none
only when needed.
occur.

Slower, as the response depends on Faster, as the CPU responds immediately

Response Time
the polling frequency. to interrupts.

Power Higher, because the CPU is active and Lower, as the CPU can sleep until an
Consumption checking events continuously. interrupt occurs.

More complex, as it requires setting up

Simpler to implement, as it involves
Complexity interrupts and ISRs (Interrupt Service
just a loop for checking events.
Routines).

Less scalable, especially with many More scalable, as multiple events can be
Scalability
events to monitor. handled with separate interrupts.

8. Implement a timer-based external event counter and explain its working.

Figure-1 mark
Explanation-2 marks

An external
event can be marked by a rising, a falling or both edges. The external events can be either
periodic or aperiodic. A timer can be easily configured to count external events by connecting
the counter input to the external signal source. The functional diagram of timer as an external
event counter is shown in Figure. From Figure observe that there is a selector switch, which
can be configured for timer input selection as internal or external. When an external signal is
used as an input to the timer, the timer counter value shows the number of external events. If
the event count reaches the maximum count value (e.g., 216 1 for 16 bit timer), then an over
ow interrupt can be generated by the timer. It is also possible to configure the timer as down
counter, while enumerating external events. In this case an under ow interrupt can be generated
after a predefined number of external events, depending on the counter initial value.

9. Apply timer configuration techniques to generate PWM output signals.

For each step - One mark
Pulse Width Modulation (PWM) is a technique that generates a signal with a constant
frequency but varying pulse width. The two main parameters in PWM are:
PWM Generation Using Timer:
1. Timer Configuration:
o The timer is configured as a down counter. It starts at 0 and is loaded with a
value based on the desired PWM time period.
o The timer value is compared to the duty cycle register to determine when the
signal should be high or low.
2. Timer Operation:
o When the timer’s value is higher than the duty cycle value, the output remains
low.
o Once the timer value is less than the duty cycle, the output goes high.
o When the timer reaches 0, it reloads, completing one cycle of PWM.
3. PWM Frequency and Pulse Width:
 o The frequency of the PWM signal is set by the reload value of the timer,
while the pulse width is determined by the duty cycle value.
4. Types of PWM:
o Edge-Aligned PWM: Uses a sawtooth waveform generated by a countdown
timer.
o Center-Aligned PWM: Uses a triangular waveform created by a timer that
counts up and down

10. Compare the I2C and SPI communication protocols based on speed, data transfer,
and complexity.
Any three comparisons – Three marks

Aspect I2C SPI

Speed Up to 3.4 Mbps (typically slower) Up to 50 Mbps or more (faster)
4-wire communication (MISO, MOSI,
Data Transfer 2-wire communication (SDA, SCL)
SCK, SS)
Communication Full-duplex (bidirectional
Half-duplex (one direction at a time)
Mode communication)
Requires addressing each device (7- No addressing needed; uses slave
Addressing
bit/10-bit) select line
Requires 4 or more wires (MISO,
Hardware Pins Requires only 2 wires (SDA, SCL)
MOSI, SCK, SS)
Multi-Master Supports multi-master (complex) Supports only one master
Protocol More complex, especially in multi-
Simpler, with fewer protocol rules
Complexity master mode
Best for low-speed devices and Best for high-speed data transfer and
Use Case
multiple peripherals fewer devices
 Five Marks Questions

1. Summarize the functions of TM4C123 microcontroller with a neat block

diagram.
Block Diagram-2 marks
Function -3 marks

Key Functional Blocks and Features

1. ARM Cortex-M4 Core (CPU):
o The TM4C123 is powered by the ARM Cortex-M4 core, which is a high-
performance, low-power processor optimized for embedded systems.
o The Cortex-M4 supports single-cycle multiply and hardware divide, making it
well-suited for mathematical and real-time applications.
o It also features a Floating Point Unit (FPU) that accelerates mathematical
calculations involving real numbers, particularly useful in signal processing or
motor control applications.
2. System Clock and Power Management:
 o The microcontroller has a flexible system clock capable of running at a
frequency of up to 80 MHz. This high clock speed allows the processor to
handle more tasks per second, which is important for real-time applications.
o The power management system allows for different power modes such as Run,
Sleep, and Deep Sleep to minimize power consumption. These modes help in
battery-operated or low-energy devices.
3. Memory (Flash and SRAM):
o The Flash memory stores the program code and is non-volatile, meaning it
retains data even when the power is turned off. The TM4C123 offers up to 256
KB of Flash memory.
o The SRAM (Static RAM) is used for temporary data storage during program
execution, with the TM4C123 having up to 32 KB of SRAM.
4. Peripheral Interfaces and General-Purpose I/O (GPIO):
o GPIO pins are used for general-purpose digital input and output operations.
These pins are highly configurable and can be used for controlling external
devices like LEDs, switches, and sensors.
o Timers and PWM (Pulse Width Modulation) modules are available for
generating precise time delays and controlling motors, lights, or other
actuators with varying duty cycles.
o The ADC (Analog-to-Digital Converter) allows the microcontroller to read
analog signals (from sensors like temperature or light sensors) and convert
them into digital values for processing.
o The DAC (Digital-to-Analog Converter) can generate analog output from
digital values, useful for generating analog signals or controlling devices that
require an analog input.
5. Communication Interfaces:
o The TM4C123 offers several communication protocols:
 UART (Universal Asynchronous Receiver/Transmitter): For serial
communication with other devices.
 I2C (Inter-Integrated Circuit): A synchronous, multi-master, multi-
slave, packet-switched communication protocol commonly used for
connecting low-speed peripheral devices like sensors or EEPROMs.
 SPI (Serial Peripheral Interface): For high-speed data transfer between
the microcontroller and external devices such as sensors, memory
chips, or displays.
6. Interrupt Handling:
o The microcontroller includes an Interrupt Controller that allows external and
internal events to interrupt the main program flow. This ensures that high-
priority tasks are handled immediately without waiting for the main program
to complete. This feature is critical for real-time applications where time-
sensitive data must be processed promptly.
7. Analog to Digital Conversion (ADC):
 o The ADC module in the TM4C123 has 12-bit resolution and can sample
analog signals from sensors. It is capable of operating in single-ended or
differential modes and has multiple channels, allowing the microcontroller to
interface with a variety of analog sensors.
8. Digital to Analog Conversion (DAC):
o The DAC module converts digital values into analog voltages. This is useful
for applications such as controlling the brightness of an LED, generating audio
signals, or controlling motors with varying speeds.

2. Discuss how to configure the pad control for a GPIO pin on the TM4C123
microcontroller.

Flow chart-1 mark

Configuration steps-4 marks

GPIO Configuration Steps

Before using GPIO port pins, they must be configured for the desired operation. Different
configurations may require a varying number of steps.
A generalized flow for GPIO configuration is shown in Figure. The key steps include:
1. Enable Peripheral Clock – The clock for the GPIO module must be activated by
setting the appropriate bit in the clock configuration register.
 2. Wait for Clock Stabilization – A delay of at least three system clock cycles is
recommended before further configuration.
3. Alternate Function Select – If the pin will be used for functions like UART, SPI,
I²C, or Timer, the alternate function must be enabled.
4. Tri-State Control – Configures the pin as a high-impedance input if needed.
5. Digital Enable – Activates digital functionality for the pin.
6. Direction Control – Specifies whether the pin will act as input or output.
7. PAD Control for Input – Configures pull-up, pull-down, or floating modes.
8. Port Control – Further configures the pin for specific peripheral functions like
UART, SPI, or timers.
9. PAD Control for Output – Sets output characteristics such as drive strength, open-
drain mode, and slew rate.
If the peripheral clock is not enabled, accessing GPIO registers may cause a bus fault. The
order of Digital Enable and Alternate Function Select steps can be switched without
affecting functionality.
This structured configuration ensures the proper operation of GPIO pins for digital inputs,
outputs, or alternate functions.

3. Demonstrate input output interfacing of LED and a switch using TM4C123

microcontroller.
Diagram-2 marks
Explanation -3 marks

The TM4C123 microcontroller platform (TI’s ARM Cortex-M4F-based TivaC) has three
onboard color LEDs (red, green, and blue) and two switches for simple input-output
interfacing. Both LEDs and switches function as digital devices. This section explains how to
interface each of these two different types of devices. LEDs are connected to GPIO pins as
digital outputs, while switches are configured as digital inputs.
The LEDs are connected using digital NPN transistors. A digital transistor integrates base (bias)
resistors inside the transistor package. Unlike ordinary transistors, a digital transistor operates
only in two states: off and saturation. The purpose of using transistors in this setup is to prevent
current overloading, which could occur if the GPIO pin is not capable of handling enough
current. The current that the GPIO pin has to sink depends on both the diode current-limiting
series resistor and the supply voltage.
The switch interfacing is not complete as shown in Figure 8.10. When the switch is pressed, a
logic low signal is applied to the GPIO port pin. However, when the switch is released, there
is no source connection to ensure a logic high signal at the GPIO port pin. Simple
microcontrollers may not function properly with this interface. However, the TM4C123
resolves this issue by using an internal pull-up resistor. When enabled, the pull-up resistor pulls
the GPIO pin to a logic high state when the switch is released. The internal pull-up resistor
values are generally greater than 10kΩ. Since the current drawn by the GPIO port pin, when
configured as an input, is very low due to its high input impedance, the voltage drop across the
pull-up resistor is almost negligible, ensuring that the voltage level remains close to the supply
voltage. This voltage level is interpreted as logic high by the internal logic.
An alternative configuration involves connecting the switch terminal to the supply voltage
(Vcc) instead of ground. In this case, enabling the internal pull-down resistor ensures proper
switch functionality. With this setup, a logic high signal is detected when the switch is pressed.
Similarly, for LED interfacing, an alternative approach is to reverse the LED direction by using
a PNP transistor, which requires reversing the driving logic.
Output Interfacing for LED
To interface LEDs, Port F pins 1, 2, and 3 need to be configured as outputs. The basic steps for
configuring the required Port F pins are:
 Enable the clock to the GPIO port.
 Select the general-purpose IO functionality by clearing the alternate function select
register (GPIOAFSEL).
 Configure the GPIO direction for digital output.
 Configure the PAD for digital operation.
Input Interfacing for Switch
Mechanical switches are commonly used for input in digital systems. These switches can be
interfaced with a microcontroller using digital inputs. The software program for switch
interfacing can be implemented using one of two methods:
1. Polling-Based Method:
o In this method, the GPIO pin connected to the switch is frequently polled in
software to avoid missing key presses.
o The polling interval should be shorter than the minimum time the switch is held
down by the user.
2. Interrupt-Based Method:
o The GPIO pin is configured as an external interrupt.
o A key press triggers an interrupt, which can be edge-triggered on either the
rising or falling edge, depending on the switch hardware.
4. Explain the Polling-Based Methods of input-output synchronization.
Continuous Polling (Busy Wait)-3 mark
Periodic Polling-2 mark
Polling is a mechanism in which the software continuously or periodically checks the status
of a hardware device to determine whether an operation has been completed. This method
helps in managing input/output (I/O) operations by allowing the software to respond only
when necessary. Polling-based synchronization can be classified into two types:
1. Continuous Polling (Busy Wait)
Working Principle
 In continuous polling, also called busy waiting, the software runs an infinite loop to
check the device status repeatedly.
 Once the device completes its operation, it updates a status flag. The software detects
this change and proceeds with the next operation.
Examples
 Input Device (e.g., Keyboard, Sensor, or Network Card)
o The software continuously checks if new data is available from the input
device.
o Once data is available, it is read and processed.
o Example: A program continuously checking for user input from a keyboard.
 Output Device (e.g., Printer, Display, or Hard Drive)
o The software first writes data to the output device and then continuously
checks its status to confirm whether the operation is complete.
o In another variation, the software first checks if the device is ready before
writing data, allowing some level of parallel execution.
Advantages
✔ Simple to implement.
✔ Ensures immediate response as the software is constantly checking the status.
Disadvantages
✖ Wastes CPU time, as the processor remains occupied in checking the status instead of
performing other useful tasks.
✖ Can cause software blocking, where the processor remains stuck in the loop indefinitely
in case of hardware failure.
2. Periodic Polling
Working Principle
 To avoid software blocking, periodic polling uses a timer to generate interrupts at
regular intervals.
 Instead of continuously checking the device status, the software checks only when an
interrupt occurs.
Examples
 Input Device (e.g., Sensor, Network Receiver)
o When new data is available, the device sets a status flag.
o At the next timer interrupt, the software reads and processes the data.
 Output Device (e.g., Printer, Display Buffer)
o The device sets a status flag when it completes an operation.
o The software checks the flag at the next interrupt and, if the device is ready, it
initiates the next operation.
Advantages
✔ Prevents software blocking, as the CPU is free to perform other tasks between polling
intervals.
✔ More efficient compared to continuous polling, as the CPU is not occupied with unnecessary
status checks.
Disadvantages
✖ Can introduce a delay in response time.
✖ The maximum delay can be equal to the timer interrupt period, meaning there might be a
waiting time before the software detects that the device is ready.
✖ Increasing the frequency of timer interrupts can improve performance but leads to higher
CPU overhead due to frequent ISR executions.
.

5. Explain the concept of input-output device synchronization using interrupts in the

TM4C123 microcontroller.
Figure -2 marks
Explanation-3 marks
Interrupt-based I/O synchronization overcomes the limitations of traditional synchronization
approaches, such as software execution blocking and serial execution of software and hardware
operations. In conventional methods, the processor wastes valuable time waiting for hardware
operations to complete instead of performing other tasks.
With interrupt-based synchronization, the hardware generates an interrupt signal when an input
device has data ready, prompting the corresponding software Interrupt Service Routine (ISR)
to process it, as illustrated in Figure (a). Similarly, for an output device, an interrupt is triggered
upon completion of an operation, allowing the software to initiate another output task while
executing the ISR, as shown in Figure (b).
When multiple peripheral devices use interrupt-based synchronization, priorities and masking
can be assigned to different interrupts. In contrast, polling-based synchronization does not
allow priority assignment. Interrupt-based synchronization is particularly beneficial for real-
time applications and event-driven systems. Its key advantage lies in enabling parallel
execution of software and hardware operations with minimal overhead, thereby eliminating
software blocking and enhancing overall system performance.

6. Examine the working of a multiplexed-type keypad when interfaced with the TM4C123
microcontroller.
Diagram -2 marks
Working - 3 marks
In scanned keypad interfacing, the switches are arranged in a matrix format, typically in an m
× n configuration, where m represents the number of rows and n represents the number of
columns. This arrangement allows the use of fewer GPIO pins for interfacing the keypad with
the microcontroller. The software scans the keypad by configuring m rows as inputs and n
columns as outputs. The scanning process involves driving one column at a time, setting it to
a low state (active), and reading the rows to detect which key is pressed in the active column.
This is repeated for each column to detect all key presses in the keypad.
For example, in the TM4C123 microcontroller, you can configure the rows as input pins and
the columns as output pins. The rows may use internal pull-down resistors available in the
microcontroller, eliminating the need for external pull-down resistors in the circuit. This
capability simplifies the design and reduces the number of components required, making the
system more efficient.
One of the key advantages of the scanned keypad interfacing approach is the reduced number
of GPIO pins required. Specifically, a keypad with m × n keys can be interfaced using only m
+ n GPIO pins. This reduces the number of pins compared to direct individual key interfacing,
where each key would need a dedicated pin. For example, for a 4x4 keypad (16 keys), only 8
GPIO pins are needed—4 for the rows and 4 for the columns—versus the 16 GPIO pins
required for a direct interface.
However, this approach has its limitations. One significant drawback is its handling of
simultaneous key presses. The scanned approach is capable of detecting only two simultaneous
key presses. If more than two keys are pressed at the same time, the system can experience key
ghosting or key bouncing. For instance, when keys are pressed in an L-shaped pattern (e.g.,
keys 1, 4, and 5), the system may falsely detect a fourth key press (key 2 in this case) as pressed,
even if it is not physically pressed. This issue arises due to the way the rows and columns
interact during the scanning process, which results in the erroneous detection of additional key
presses when multiple keys are simultaneously pressed.
Thus, while the scanned keypad interface is efficient and works well for detecting a few key
presses, it cannot reliably detect three or more simultaneous key presses. This limitation must
be considered when designing systems that require accurate detection of multiple key presses
at once, such as in complex user input scenarios or systems that need to handle simultaneous
multi-key input.

7. Develop a method to interface a multiplexed-type keypad with the TM4C123

microcontroller.
Diagram-2 marks
Interfacing method-3 marks
In a multiplexed keypad interface, the process involves using a combination of GPIO output
and input pins to reduce the number of connections needed to interface a keypad with a
microcontroller. In this setup, the microcontroller's GPIO output pins are connected to a
demultiplexer, which then drives the columns of the keypad, while the GPIO input pins are
interfaced with a multiplexer that handles the rows. This approach significantly reduces the
number of GPIO pins needed compared to a direct connection method.

For instance, if n = m = 4, the setup would involve using 4 GPIO output pins to drive a 4-to-
16 demultiplexer, which then controls the 16 columns of the keypad. At the same time, the 16
rows of the keypad are connected to a 16-to-4 multiplexer that interfaces with 4 GPIO input
pins on the microcontroller. This allows for the interfacing of a keypad with 2^4 × 2^4 = 16 ×
16 = 256 keys using only 8 GPIO pins, which is the maximum number of keys that can be
handled for this configuration. The multiplexing technique optimizes the use of GPIO pins,
allowing a more efficient and scalable interface for larger keypads.

However, since a large number of keys are connected in a multiplexed fashion, the process of
scanning the entire keypad to detect a key press takes significant processing time. The
microcontroller must sequentially scan the rows and columns, activating one row at a time and
reading the corresponding columns to identify which key is pressed. This scanning process
takes time and is one of the drawbacks of multiplexed interfacing.

The relationship between the number of GPIO pins and the number of keys that can be
interfaced is summarized as follows: using m GPIO input pins and n GPIO output pins, the
system can interface a keypad with 2^m × 2^n keys. This method is far more efficient than
connecting each key individually, which would require a separate GPIO pin for each key,
greatly increasing the number of pins needed for larger keypads.

However, this method has some limitations, such as the inability to handle situations like the
"two-key rollover." In a two-key rollover scenario, the first key is pressed and then released
before the second key is pressed. The multiplexed keypad interfacing method described here
assumes that each key is pressed and released before the next key is detected, which could
cause problems in situations where multiple keys are pressed simultaneously.

To illustrate this method, consider a 16-button keypad arranged in a 4x4 matrix. In this case, 8
GPIO pins are used: 4 output pins control the columns, and 4 input pins read the rows. The
microcontroller scans the keypad by sequentially activating the rows and reading the columns,
identifying which key is pressed based on the row-column combination. This process is
relatively straightforward, but due to the multiplexed nature of the interface, it requires careful
handling of timing and key press detection to avoid issues like key bouncing or missed presses.
8. Illustrate the working principle of the I2C communication protocol with respect to
the TM4C123 microcontroller.
Working principle Step 1 -2 – 2 marks
Step 3 - 5 - 3 marks
I2C (Inter-Integrated Circuit) is a communication protocol designed for connecting
multiple devices (master and slave) over a two-wire interface: the Serial Data Line (SDA)
and the Serial Clock Line (SCL). It is commonly used for communication between
microcontrollers and peripheral devices such as sensors, EEPROMs, and ADCs.
Communication Process:
1. Start Condition: The communication begins when the SDA line transitions from high
to low while the SCL line is high, indicating that a data transfer is about to occur.
2. Addressing: The master sends a 7-bit or 10-bit address of the target slave. The 8th bit
indicates the type of operation (0 for write, 1 for read).
3. Data Transfer: Data is transmitted in 8-bit chunks, with each byte followed by an
acknowledgment (ACK) bit to confirm successful reception. If a byte is not received
correctly, a negative acknowledgment (NACK) can be sent.
4. Stop Condition: The communication ends when the SDA line transitions from low to
high while the SCL line is high, marking the end of data transmission.

I2C Implementation on the TM4C123 Microcontroller

The TM4C123 microcontroller from Texas Instruments supports I2C communication via its
hardware I2C modules. The process of configuring and using I2C on the TM4C123 involves
the following steps:
1. Enable the Clock for the I2C Module:
o The clock for the I2C module must be enabled before it can be used. This is
done by accessing the system control register to activate the clock for the
specific I2C module (e.g., I2C0 or I2C1).
2. Configure GPIO Pins for I2C:
o The TM4C123 uses specific GPIO pins for the I2C interface (SDA and SCL).
These pins need to be configured for their alternate function to enable I2C
communication. This involves setting the GPIO pins to the appropriate
alternate function mode.
3. Set Up the I2C Module:
o The I2C module must be configured to work in master mode (if the
TM4C123 is acting as a master device) or slave mode (if it is acting as a
slave).
o The baud rate (speed) of communication is set by adjusting the timing
parameters in the I2C configuration.
o The I2C module is then enabled to begin communication.
4. Sending Data to a Slave Device:
 o When transmitting data, the master sends the 7-bit address of the slave along
with a write/read bit. If the operation is a write, the master sends the data byte
after the address. For each byte, an acknowledgment (ACK) is expected from
the slave.
o The communication can be stopped after the data transfer by sending a stop
condition.
5. Receiving Data from a Slave Device:
o For reading data, the master sends the slave address with the read bit set. The
slave responds by sending data back to the master, which receives the data
byte and sends an acknowledgment after each byte.
o The master can stop the communication after receiving the desired amount of
data by sending a stop condition.
6. Error Handling and Interrupts:
o The I2C module provides flags and interrupt sources to handle errors and
manage the completion of data transfers. These can be used to trigger
interrupts in the microcontroller to handle specific events like data reception
or transmission errors.
7. Disabling the I2C Module (Optional):
o After communication is complete, the I2C module can be disabled to save
power or free up the module for other tasks. This is done by disabling the I2C
master function.

9. Outline the steps to configure SPI module for data transfer in TM4C123.
For each step - One mark
To configure the SPI (Serial Peripheral Interface) module for data transfer in the TM4C123
microcontroller (from Texas Instruments), you need to follow a series of steps. These steps
include enabling the clock for the SPI module, configuring the relevant SPI parameters (such
as mode, bit order, and data rate), setting up the data frame format, and finally initiating data
transfers.
Here’s a detailed outline of the steps to configure SPI for data transfer in the TM4C123
microcontroller:
1. Enable Clock for the SPI Module
Before configuring the SPI module, the clock for the module must be enabled in the system
control register.
 Enable the clock to the SPI peripheral (e.g., SPI0).
 Set the clock source for the SPI module.
2. Configure GPIO Pins for SPI
The TM4C123 microcontroller uses dedicated GPIO pins for SPI communication (e.g., SCK,
MOSI, MISO). These pins need to be configured as alternate functions.
  Set the pins for SCK (clock), MOSI (Master Out Slave In), and MISO (Master In
Slave Out).
 Configure the pin direction (input/output) and select the alternate function for the SPI.
3. Configure the SPI Module (SSI)
Set up the SSI0 (or another SPI instance) for the desired operation. This involves configuring
the SSI Control Register (SSI0_CR1) and SSI Configuration Register (SSI0_CR0).
 Set the master/slave mode.
 Set the clock polarity (CPOL) and clock phase (CPHA) for communication.
 Set the data frame format (typically 8-bit).
 Configure the baud rate (divide the system clock to achieve the desired rate).
4. Enable the SPI Interrupts
If you need to handle data transfer via interrupts (for asynchronous operation), enable the
interrupts for the SPI module.
5. Send Data Using SPI
Once everything is set up, you can begin sending and receiving data using the SPI module.
Data is written to the SSI Data Register (SSI0_DR), and you can check the SSI Status
Register for flags to check if the transmission is complete or if the data register is ready.

10. Infer the different types of data frames in CAN protocol.

Figure 2 marks
Standard Data frame 1.5 marks
Extended Data frame 1.5 marks
Data Frame in CAN
In Controller Area Network (CAN), data frames are used for communication between devices
in a network. CAN frames come in two primary types: Standard Data Frame and Extended
Data Frame. These types are based on the identifier used to distinguish the messages.

1. Standard Data Frame

The Standard Data Frame is the original format for CAN communication. It uses an 11-bit
identifier, which provides 2,048 unique identifiers for the messages. This frame is used in most
basic CAN implementations where there’s no need for an excessively large number of
identifiers.
Structure of Standard Data Frame:
 Start of Frame (1 bit): A dominant bit indicating the start of the frame.
 Identifier (11 bits): This is the most important part of the frame, where the 11-bit
identifier is placed. It is used for prioritization and message filtering. Lower numbers
have higher priority.
 RTR (Remote Transmission Request, 1 bit): This bit indicates whether the frame is a
data frame (dominant) or a remote frame (recessive).
 Control (6 bits):
o Data Length Code (DLC, 4 bits): It specifies how many bytes of data are being
transmitted (0–8 bytes).
o Reserved Bit (1 bit): Reserved for future use (typically 0).
o IDE (Identifier Extension, 1 bit): This is always 0 in a standard frame
(indicating that the identifier is not extended).
 Data (0–8 bytes): The actual data being transmitted, with a maximum of 8 bytes.
 CRC (Cyclic Redundancy Check, 15 bits): Used for error detection.
 ACK (Acknowledge, 2 bits): The receiver sends an acknowledgment bit if the frame
is correctly received.
 End of Frame (7 bits): Marks the end of the frame.
2. Extended Data Frame
The Extended Data Frame is an expanded version of the standard frame. It uses a 29-bit
identifier instead of 11 bits, allowing for a much larger number of unique message identifiers
(over 500 million). This frame type is useful in more complex CAN networks, where there is
a need for more identifiers, such as in automotive or industrial applications.
Structure of Extended Data Frame:
 Start of Frame (1 bit): Same as the standard frame, marking the beginning of the
frame.
 Identifier (29 bits): The 29-bit identifier allows for a significantly larger number of
message identifiers. This helps in differentiating messages in large systems.
 RTR (1 bit): Identifies whether the frame is data or remote (same as the standard
frame).
 Control (6 bits):
 o Data Length Code (DLC, 4 bits): Specifies the number of bytes in the data
field (0–8 bytes).
o Reserved Bit (1 bit): Reserved for future use (typically 0).
o IDE (1 bit): In an extended frame, this bit is set to 1, indicating that the frame
uses the extended 29-bit identifier.
 Data (0–8 bytes): The payload or data transmitted, up to 8 bytes.
 CRC (15 bits): Error detection part, similar to the standard frame.
 ACK (2 bits): Acknowledge bits sent by the receiver.
 End of Frame (7 bits): Marks the end of the frame.