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DV Interview

The document contains a comprehensive list of design verification interview questions across various topics including digital design, Verilog, SystemVerilog, and Universal Verification Methodology (UVM). Each section features specific tasks such as designing circuits, implementing modules, and explaining key concepts related to digital logic and verification methodologies. The questions are aimed at assessing knowledge and practical skills in digital design and verification techniques.

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N180243 GOLLA SAILAJA
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46 views5 pages

DV Interview

The document contains a comprehensive list of design verification interview questions across various topics including digital design, Verilog, SystemVerilog, and Universal Verification Methodology (UVM). Each section features specific tasks such as designing circuits, implementing modules, and explaining key concepts related to digital logic and verification methodologies. The questions are aimed at assessing knowledge and practical skills in digital design and verification techniques.

Uploaded by

N180243 GOLLA SAILAJA
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Design

Verification
Interview Questions
Digital:
1. Design a combinational circuit that can detect the presence of two consecutive 1's in a 6-bit input
sequence.

2. Implement a 4-bit binary multiplier using a hierarchical approach.

3. Explain the concept of race-around conditions in sequential circuits and how they can be avoided.

4. Design a finite state machine (FSM) that recognizes the sequence "1011" in a serial input stream.

5. Implement a 4-bit binary to Gray code converter using a combinational circuit.

6. Explain the concept of hazards in combinational logic circuits and how they can be eliminated using
Karnaugh maps.

7. Design a priority encoder that can handle 8 input lines and generate a 3-bit binary code representing
the highest priority input.

8. Implement a 3-bit synchronous up/down counter using D flip-flops and combinational logic.

9. Explain the concept of critical race in asynchronous sequential circuits and how it can be resolved.

10. Design a combinational circuit that can detect an odd parity in a 7-bit input.

11. Implement a 4-bit binary to BCD (Binary-Coded Decimal) converter using a combinational circuit.

12. Explain the concept of glitches in combinational logic circuits and how they can be minimized.

13. Design a sequential circuit that can detect the sequence "101010" in a serial input stream.

14. Implement a 4-bit ring counter using D flip-flops and combinational logic.

15. Explain the concept of state assignment in finite state machines and its impact on circuit complexity.
Verilog:

1. Write a Verilog module that implements a 8-bit shift register with parallel load, shift left, and shift
right capabilities.

2. Write a Verilog module that implements a parameterized n-bit binary counter with synchronous reset
and enable signals.

3. Write a Verilog module that implements a parameterized n-bit binary comparator with outputs for
equal, greater than, and less than conditions.

4. Difference between Wire & Reg and what are the default values ?

5. difference between while & Do_While ?

6. Write a Verilog module that implements a parameterized n-bit ripple carry adder with carry input and
carry output signals.

7. Write a Verilog module that implements a parameterized n-bit binary multiplier using the shift-and-
add algorithm.

8. Write a Verilog Code for 5:1 Mux

9. Design D-ff using JK-ff Using NAND Gate

10. Verilog Code For Full ADDER using Conditional Operator

11. Serial adder is sequential (or) combinational circuit write a verilog code for it ?

12. difference between normal encoder and priority encoder and write verilog codes for it ?

13. What is the use of Generate in Verilog ?


SystemVerilog (SV):

1. Difference between $strobe,$write,$display & $write ?

2. how can we randomie varibles without using rand and randc ?

3. what is inheritance, Polymorphism,encapsulation ?

4. Constraint to generate pattern (0,0,0,0,0,1,0,0,2,0,0,3......0,0,15)

5. Delete the iteams in the queue without using the push,pop & delete methods

6. Constraint for even address having even value and odd value having odd value ?

7. Types of Functional Coverage ?

8. Enumeration datatype and how it is used ?

9. write constraint for chess board ?

10. write a property check that if the signal "A" is high on given posedge of the clock, the signal "B"
should be high for 3 clock cycles followed by "C" should be high after "B" is high for the third time.

11. can you write a functional coverage for a 12 bit variable and ensure functional coverage 100% if and
only if all the values are covered ?

12. write a constraint to generate the prime numbers 50 to 100 and all values should be unique but dont
use "unique keyword"
Universal Verification Methodology (UVM):

1. With using TLM write the scoreboard logic for FIFO

2. Write the UVM Top Module Code ?

3. Why dont we use mailbox in uvm?

4. How do you terminate simulation in uvm ?

5. m-sequncer vs p-sequencer?

6. Main_phase in uvm ?

7. write uvm connections between sequence & driver via sequencer

8. write config_db setup in uvm ?

9. sequence_item vs transaction class ?

10. explain about the phases in uvm?

11. copy and clone in uvm ?

12. difference between uvm_object & uvm_component ?

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