Digital Electronics and Digital Instruments (EE 4th Semester)

Unit 1: Number Systems

1 Any signed negative binary number is recognised by its ________
a) MSB
b) LSB
c) Byte
d) Nibble
2 The representation of octal number (532.2)8 in decimal is ________
a) (346.25)10
b) (532.864)10
c) (340.67)10
d) (531.668)10
3 The decimal equivalent of the binary number (1011.011)2 is ________
a) (11.375)10
b) (10.123)10
c) (11.175)10
d) (9.23)10
4 An important drawback of binary system is ________
a) It requires very large string of 1’s and 0’s to represent a decimal number
b) It requires sparingly small string of 1’s and 0’s to represent a decimal number
c) It requires large string of 1’s and small string of 0’s to represent a decimal
number
d) It requires small string of 1’s and large string of 0’s to represent a decimal
number
5 The decimal equivalent of the octal number (645)8 is ______
a) (450)10
b) (451)10
c) (421)10
d) (501)10
6 The largest two digit hexadecimal number is ________
a) (FE)16
b) (FD)16
c) (FF)16
d) (EF)16
7 Representation of hexadecimal number (6DE)H in decimal:
a) 6 * 162 + 13 * 161 + 14 * 160
b) 6 * 162 + 12 * 161 + 13 * 160
c) 6 * 162 + 11 * 161 + 14 * 160
d) 6 * 162 + 14 * 161 + 15 * 160
8 The given hexadecimal number (1E.53)16 is equivalent to ____________
a) (35.684)8
b) (36.246)8
c) (34.340)8
d) (35.599)8
9 The octal number (651.124)8 is equivalent to ______
a) (1A9.2A)16
b) (1B0.10)16
 c) (1A8.A3)16
d) (1B0.B0)16
10 The octal equivalent of the decimal number (417)10 is _____
a) (641)8
b) (619)8
c) (640)8
d) (598)8
11 Convert the hexadecimal number (1E2)16 to decimal:
a) 480
b) 483
c) 482
d) 484
12 (170)10 is equivalent to
a) (FD)16
b) (DF)16
c) (AA)16
d) (AF)16
13 Convert (214)8 into decimal:
a) (140)10
b) (141)10
c) (142)10
d) (130)10
14 Convert (0.345)10 into an octal number:
a) (0.16050)8
b) (0.26050)8
c) (0.19450)8
d) (0.24040)8
15 Convert the binary number (01011.1011)2 into decimal:
a) (11.6875)10
b) (11.5874)10
c) (10.9876)10
d) (10.7893)10
16 Octal to binary conversion: (24)8 =?
a) (111101)2
b) (010100)2
c) (111100)2
d) (101010)2
17 Convert binary to octal: (110110001010)2 =?
a) (5512)8
b) (6612)8
c) (4532)8
d) (6745)8
18 What is the addition of the binary numbers 11011011010 and 010100101?
a) 0111001000
b) 1100110110
c) 11101111111
d) 10011010011
19 Perform binary addition: 101101 + 011011 = ?
a) 011010
b) 1010100
 c) 101110
d) 1001000
20 Perform binary subtraction: 101111 – 010101 = ?
a) 100100
b) 010101
c) 011010
d) 011001
21 Binary subtraction of 100101 – 011110 is
a) 000111
b) 111000
c) 010101
d) 101010
22 Perform multiplication of the binary numbers: 01001 × 01011 = ?
a) 001100011
b) 110011100
c) 010100110
d) 101010111
23 100101 × 0110 = ?
a) 1011001111
b) 0100110011
c) 101111110
d) 0110100101
24 On multiplication of (10.10) and (01.01), we get
a) 101.0010
b) 0010.101
c) 011.0010
d) 110.0011
25 Divide the binary numbers: 111101 ÷ 1001 and find the remainder
a) 0010
b) 1010
c) 1100
d) 0011
26 Divide the binary number (011010000) by (0101) and find the quotient
a) 100011
b) 101001
c) 110010
d) 010001
27 Binary subtraction of 101101 – 001011 = ?
a) 100010
b) 010110
c) 110101
d) 101100
28 1’s complement of 1011101 is ____________
a) 0101110
b) 1001101
c) 0100010
d) 1100101
29 2’s complement of 11001011 is ____________
a) 01010111
b) 11010100
 c) 00110101
d) 11100010
30 If the number of bits in the sum exceeds the number of bits in each added
numbers, it results in _________
a) Successor
b) Overflow
c) Underflow
d) Predecessor
31 1’s complement can be easily obtained by using _________
a) Comparator
b) Inverter
c) Adder
d) Subtractor
32 The advantage of 2’s complement system is that _________
a) Only one arithmetic operation is required
b) Two arithmetic operations are required
c) No arithmetic operations are required
d) Different Arithmetic operations are required
33 The 1’s complements requires _________
a) One operation
b) Two operations
c) Three operations
d) Combined Operations
34 Which one is used for logical manipulations?
a) 2’s complement
b) 9’s complement
c) 1’s complement
d) 10’s complement
35 For arithmetic operations only _________
a) 1’s complement is used
b) 2’s complement
c) 10’s complement
d) 9’s complement
36 Binary coded decimal is a combination of __________
a) Two binary digits
b) Three binary digits
c) Four binary digits
d) Five binary digits
37 The decimal number 10 is represented in its BCD form as __________
a) 10100000
b) 01010111
c) 00010000
d) 00101011
38 Add the two BCD numbers: 1001 + 0100 = ?
a) 10101111
b) 01010000
c) 00010011
d) 00101011
39 Code is a symbolic representation of __________ information.
a) Continuous
 b) Discrete
c) Analog
d) Both continuous and discrete
40 When numbers, letters or words are represented by a special group of symbols,
this process is called __________
a) Decoding
b) Encoding
c) Digitizing
d) Inverting
41 The excess-3 code for 597 is given by __________
a) 100011001010
b) 100010100111
c) 010110010111
d) 010110101101
42 The decimal equivalent of the excess-3 number 110010100011.01110101 is
_____________
a) 970.42
b) 1253.75
c) 861.75
d) 1132.87
43 Positive integers can be represented as

A. Signed numbers
B. Unsigned numbers
C. Negative integers
D. both A and B

44 Representation of -9 with signed magnitude equals to

A. 10001001
B. 11110110
C. 11110111
D. 11110011

45 The more convenient system for representing the negative numbers is

A. Signed-complement system
B. Unsigned-complement system
C. Negative integer system
D. Positive integer system

46 1's complement as a logical operation is equivalent to

A. Logical design
 B. Illogical design
C. Logical complement
D. Illogical complement

47 The most commonly used system for representing signed binary numbers is the:
A. 2's-complement system.

B. 1's-complement system.

C. 10's-complement system.

D. sign-magnitude system.
48 The decimal value for E16 is:
A. 1210

B. 1310

C. 1410

D. 1510
49 The binary subtraction 0 – 0 =
difference = 0
A.
borrow = 0

difference = 1
B.
borrow = 0

difference = 1
C.
borrow = 1

difference = 0
D.
borrow = 1
50 Adding in binary, a decimal 26 + 27 will produce a sum of:
A. 111010

B. 110110

C. 110101

D. 101011

Unit 3: Boolean Algebra and Combinational Circuits

1 A full adder logic circuit will have __________
a) Two inputs and one output
b) Three inputs and three outputs
 c) Two inputs and two outputs
d) Three inputs and two outputs
2 The gates required to build a half adder are __________
a) EX-OR gate and NOR gate
b) EX-OR gate and OR gate
c) EX-OR gate and AND gate
d) EX-NOR gate and AND gate
3 Don’t care conditions can be used for simplifying Boolean expressions in
___________
a) Registers
b) Terms
c) K-maps
d) Latches
4 There are ______ cells in a 4-variable K-map.
a) 12
b) 16
c) 18
d) 8
5 The involution of A is equal to _________
a) A
b) A’
c) 1
d) 0
6 A (A + B) = ?
a) AB
b) 1
c) (1 + AB)
d) A
7 The basic building blocks of the arithmetic unit in a digital computers are
__________
a) Subtractors
b) Adders
c) Multiplexer
d) Comparator
8 A digital system consists of _____ types of circuits.
a) 2
b) 3
c) 4
d) 5
9 DeMorgan’s theorem states that _________
a) (AB)’ = A’ + B’
b) (A + B)’ = A’ * B
c) A’ + B’ = A’B’
d) (AB)’ = A’ + B
10 All logic operations can be obtained by means of __________
a) AND and NAND operations
b) OR and NOR operations
c) OR and NOT operations
d) NAND and NOR operations
11 The design of an ALU is based on __________
a) Sequential logic
b) Combinational logic
c) Multiplexing
d) De-Multiplexing
12 (A + B)(A’ * B’) = ?
a) 1
b) 0
c) AB
d) AB’
13 Complement of the expression A’B + CD’ is _________
a) (A’ + B)(C’ + D)
b) (A + B’)(C’ + D)
c) (A’ + B)(C’ + D)
d) (A + B’)(C + D’)
14 Total number of inputs in a half adder is __________
a) 2
b) 3
c) 4
d) 1
15 In which operation carry is obtained?
a) Subtraction
b) Addition
c) Multiplication
d) Both addition and subtraction
16 If A and B are the inputs of a half adder, the sum is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
17 If A and B are the inputs of a half adder, the carry is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
18 In boolean algebra, the OR operation is performed by which properties?
a) Associative properties
b) Commutative properties
c) Distributive properties
d) All of the Mentioned
19 The expression for Absorption law is given by _________
a) A + AB = A
b) A + AB = B
c) AB + AA’ = A
d) A + B = B + A
20 According to boolean law: A + 1 =?
a) 1
b) A
c) 0
d) A’
21 Half subtractor is used to perform subtraction of ___________
a) 2 bits
b) 3 bits
c) 4 bits
d) 5 bits
22 For subtracting 1 from 0, we use to take a _______ from neighbouring bits.
a) Carry
b) Borrow
c) Input
d) Output
23 How many outputs are required for the implementation of a subtractor?
a) 1
b) 2
c) 3
d) 4
24 Let the input of a subtractor is A and B then what the output will be if A = B?
a) 0
b) 1
c) A
d) B
25 Let A and B is the input of a subtractor then the output will be ___________
a) A XOR B
b) A AND B
c) A OR B
d) A EXNOR B
26 Full subtractor is used to perform subtraction of ___________
a) 2 bits
b) 3 bits
c) 4 bits
d) 8 bits
27 The output of a subtractor is given by (if A, B and X are the inputs).
a) A AND B XOR X
b) A XOR B XOR X
c) A OR B NOR X
d) A NOR B XOR X
28 The output of a full subtractor is same as ____________
a) Half adder
b) Full adder
c) Half subtractor
d) Decoder
29 Which of the following logic expressions represents the logic diagram shown?
 a) X=AB’+A’B
b) X=(AB)’+AB
c) X=(AB)’+A’B’
d) X=A’B’+AB
30 The device shown here is most likely a ________

a) Comparator
b) Multiplexer
c) Inverter
d) Demultiplexer
31 3 bits full adder contains ________
a) 3 combinational inputs
b) 4 combinational inputs
c) 6 combinational inputs
d) 8 combinational inputs
32 What is a multiplexer?
a) It is a type of decoder which decodes several inputs and gives one output
b) A multiplexer is a device which converts many signals into one
c) It takes one input and results into many output
d) It is a type of encoder which decodes several inputs and gives one output
33 What is the function of an enable input on a multiplexer chip?
a) To apply Vcc
b) To connect ground
c) To active the entire chip
d) To active one half of the chip
34 In a multiplexer, the selection of a particular input line is controlled by
___________
a) Data controller
b) Selected lines
c) Logic gates
d) Both data controller and selected lines
35 If the number of n selected input lines is equal to 2^m then it requires _____ select
lines.
a) 2
b) m
c) n
d) 2n
36 How many select lines would be required for an 8-line-to-1-line multiplexer?
a) 2
b) 4
c) 8
d) 3
37 How many NOT gates are required for the construction of a 4-to-1 multiplexer?
a) 3
 b) 4
c) 2
d) 5
38 In 1-to-4 demultiplexer, how many select lines are required?
a) 2
b) 3
c) 4
d) 5
39 How many AND gates are required for a 1-to-8 multiplexer?
a) 2
b) 6
c) 8
d) 5
40 How many OR gates are required for an octal-to-binary encoder?
a) 3
b) 2
c) 8
d) 10
41 Can an encoder be called as multiplexer?
a) No
b) Yes
c) Sometimes
d) Never
42 How many inputs are required for a 1-of-10 BCD decoder?
a) 4
b) 8
c) 10
d) 2
43 How many inputs are required for a 1-of-16 decoder?
a) 2
b) 16
c) 8
d) 4
44 Reflected binary code is also known as ___________
a) BCD code
b) Binary code
c) ASCII code
d) Gray Code
45 Why do we use gray codes?
a) To count the no of bits changes
b) To rotate a shaft
c) Error correction
d) Error Detetction
46 Convert binary number into gray code: 100101.
a) 101101
b) 001110
c) 110111
d) 111001
47 One that is not the outcome of magnitude comparator is ____________
a) a > b
 b) a – b
c) a < b
d) a = b
48 If two numbers are not equal then binary variable will be ____________
a) 0
b) 1
c) A
d) B
49 In a comparator, if we get input as A>B then the output will be ____________
a) 1
b) 0
c) A
d) B
50 Which one is a basic comparator?
a) XOR
b) XNOR
c) AND
d) NAND

Unit 5: Digital to Analog and Analog to Digital and Converters

and Display Devices
1 A system that converts a digital signal into analog signal is called
a)ADC
b)DAC
c)AAC
d)DDC
ANS:B
2 Pulse width modulator is type of
1) ADC
b)DAC
c)AAC
d)DDC
ANS:B
3 A measurement of the maximum speed at which the DACs circuitry can operate
and still produce correct output called
a)maximum sampling rate
b)minimum sampling rate
c)maximum summation rate
d)minimum summation rate
4 An ideal DAC converts the abstract numbers into a conceptual sequence of
a)impulses
b)signals
c)quantization’s
d)summations
5 A measurement of the difference between the largest and smallest signals the
DAC is referred as
a)dynamic range
b)static range
c)determinate range
 d)stable range
ans:A
6 The equivalent weight of LSB in a four bit variable resistive divider D/A
converter is
a)1/4
b)1/16
c)1/15
d)8/15
ans:1/15
7 For a 5-bit resistive divider network the weight assigned to MSB is
A)1/31
b)1/32
c)8/31
d)16/31
ans: 16/31
8 The number of resistors required for a five bit resistor divider, D/A converter are
a)10
b)5
c)8
d)31
ans:5
9 The error in the D/A converter output may be due to
a)Errors in the values of resistors used
b)monotonicity
c)small resolution
d)It’s a higher D/A speed

10 The fastest A/D converter is

a)single slope ramp comparator A/D converter
b)dual slope integrator A/D convertor
c)successive approximation A/D converter
d)counter type A/D converter
ans:c
11 Which system converts analog to digital signal?
a)analog to digital converter
b)digital to analog converter
c)a and b both
d)none of above
ans:a
12 which is example of ADC.
a)sound from microphone
b)mike
c)button
d)all of above
ans:a
13 how many state digital signal have?
a)one
b)two
c)three
d)four
 Ans:b
14 Why is ADC needed?
a)microprocessor can only perform complex processing
b)Adc provide link between analog to digital world
c)When signals are in digital form they are less susceptible to the deleterious
effect of noise
d)all of above
ans:d
15 Which are the following types of ADC?
a)ramp type ADC
b)Dual slope type ADC
c)Integrating type ADC
d)all of above
ans:d
16 This type of ADC also known as voltage to time conversion.
a)ramp type ADC
b)Dual slope type ADC
c)Integrating type ADC
d)all of above
ans:a
17 Which of the following are advantages of ramp type ADC?
a)It is easy to design
b)low cast
c)ADC output can be send over long distance
d)all of above
ans:d
18 Which of the following are disadvantages of ramp type ADC?
a)larger error possible due to noise
b)filters are required
c)excellent ramp linearity requirement
d)all of above
ans:d
19 Which of the following are advantages of dual slope type ADC?
a)The conversation result is intensive
b)fewer adverse effect from noise
c)High accuracy
d) all of above
ans:d
20 Which of the following are disadvantages of dual slope type ADC?
a)slow
b)costly
c)accuracy is depend on use of precision external component
d)all of above
ans:d
21 Which of the following ADC better in seed than among all other ADC?
a)ramp
b)dual slope
c)successive approximation
d)flash
ans:d
22 Which of the following ADC better in resolution than among all other ADC?
a)ramp
b)dual slope
c)successive approximation
d)flash
ans:a
23 Which of the following ADC’s cost is high than among all other ADC?
a)ramp
b)dual slope
c)successive approximation
d)flash
ans:d
24 Which of the following type output is provided by ADC?
a) Serial type
b) Parallel type
c) Both serial and parallel type
d) None of the mentioned
25 Which of the following method is employed for ADC?
a) Ladder network
b) Successive approximation type
c) PWM type
d) None of the mentioned
26 Dynamic range of ADC is depended on _______________
a) Resolution
b) Linearity
c) Accuracy
d) All of the mentioned
27 ADC input is sampled by

A. Nyquist rate
B. Newton rate
C. Ohms rate
D. Lens rate

28 The full form of LCD is ____________

a) Liquid Crystal Display
b) Liquid Crystalline Display
c) Logical Crystal Display
d) Logical Crystalline Display
29 By which properties, the orientation of molecules in a layer of liquid crystals can
be changed?
a) Magnetic field
b) Electric field
c) Electromagnetic field
d) Gallois field
30 The direction of electric field in an LCD is determined by ___________
a) the molecule’s chemical structure
b) Crystalline surface structure
 c) Molecular Orbital Theory
d) Quantum Cellular Automata
31 LCDs operate from a voltage ranges from ___________
a) 3 to 15V
b) 10 to 15V
c) 10V
d) 5V
32 In 7 segment display, how many LEDs are used?
a) 8
b) 7
c) 10
d) 9
33 A light emitting diode is _________
a) Heavily doped
b) Lightly doped
c) Intrinsic semiconductor
d) Zener diode
34 What should be the biasing of the LED?
a) Forward bias
b) Reverse bias
c) Forward bias than Reverse bias
d) No biasing required
35 Which process of the Electron-hole pair is responsible for emitting of light?
a) Generation
b) Movement
c) Recombination
d) Diffusion
36 Which of the following is not a characteristic of LED?
a) Fast action
b) High Warm-up time
c) Low operational voltage
d) Long life
37 Which of the following are used in DAC?
a) Ladder network
b) Successive approximation technique
c) Both Ladder and successive approximation technique
d) None of the mentioned
38 Which of the following is an indication by settling time?
a) Accuracy of conversion
b) Speed of conversion
c) Precision in conversion
d) All of the mentioned
39 Filling data between impulses in DAC is known as __________________
a) Reconstruction
b) Sampling
c) Interpolation
d) None of the mentioned
40 Which of the following is a binary weighted DAC?
a) R-2R ladder DAC
b) PWM DAC
 c) Switched resistor DAC
d) Sampling DAC
41 In binary resistor DAC, which terminal of the opamp is grounded?
a. Negative terminal
b. Positive terminal
c. Both terminals
d. None
42 In binary resistor DAC, Ri and Ro are related as
a. Ri is independent of Ro
b. Ri is Ro times 2 raised to the power i
c. Ri is Ro times 2 raised to the power (-i)
d. Ri is equal to Ro
43 In binary resistor DAC, the scale factor K is
a. -(Rf/Ro)
b. (Rf/Ro)
c. (Rf*Ro)
d. -(Rf*Ro)
44 Which ADC does not use clock signal?
a. Flash ADC
b. Counter comparator ADC
c. Double ramp ADC
d. Successive approximation AD
45 Digital to analog conversion can be done by
a. Weighted resistor method
b. R-2R ladder
c. Inverted R-2R-ladder method
d. All of the above
46 Which ADC has a fixed conversion time?
a. Counter comparator ADC
b. Wilkinson ADC
c. Double ramp ADC
d. Successive approximation ADC
47 Only two values of resistor are required for the DAC
a. Weighted resistor method
b. R-2R ladder
c. Binary weighted method
d. None of the above
48 The R-2R ladder DAC has the drawback
a. Higher values of resistance are required
b. Lesser word length
c. Non-linearity due to power dissipation
d. none of the above
49 The advantage of ADC of dual slope type is
a. Excellent noise rejection
b. Long conversion time
c. Fastest in operation
d. Slow varying in nature
50 In Counter Comparator ADC using DAC, the counter gets disabled when
a. output Va exceeds input Vi
b. output Va becomes zero
c. output Va becomes smaller than input Vi
d. None of the above