1st IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES-2016)

Review on Realization of AES Encryption and

Decryption with Power and Area Optimization
Mohini Mohurle l and Vishal V. Panchbhai2
'Electronics and Communication Engineering, Priyadarshini College of Engineering, Nagpur, India
2Dept.ofElectronics and Telecommunication Engineering, Priyadarshini College of Engineering, Nagpur, India
E-mail: ·mohinimohurle@gmail . com . [email protected]

Abstract-In this project, a hardware implementation of respectively controlled by the clock. The pipelining
the AES-256 encryption and decryption algorithm is technology was utilized in the 13 round transformations so
proposed. The AES cryptography algorithm can be used to that the new algorithm formed a balance between speed
encryption and decryption blocks of 128 bits and is capable and chip area.AES use different key-lengths, the standard
of using cipher keys of 256 bits. Feature of the proposed
defines three lengths and the resulting algorithms are
pipeline design is depending on the round keys, which are
consumed different round of encryption, are generated in named AES-128, AES-192 and AES-256 respectively
parallel way with the encryption process. This lowers delay with different length in bits of the key. In AES-256
of the each round of encryption and reduces the encryption encryption and decryption with 256-bit key is
delay of a plaintext block. Xilinx ISE.14.7 (64-bit) is used for considered.AES provides combination of security,
simulation by using VHDL and hardware implementation on performance and efficiency. For any security, here key
FPGA (Xilinx Spartan 6 or A1tera Cyclone 2 FPGA device). size is important because of this it determines the strength
Keywords-Cryptography; Cipher; FPGA; Advanced of security, area optimization and power consumption [5].
Encryption Standard (AES); VHDL
II. LITERATURE REVI EW
I. INTRODUCTION
Pritam Kumar Khose et ai., implementing AES
An encryption is the conversion of data into a secret hardware to achieve less area and low power consumption
code. It is the most effective way to achieve the data which maintain throughput of data, to achieve high speed
security. To read an encrypted file, one must have an data processing and reduce time for key generating. The
access to a secret key or password that enables us to
implementation of AES algorithm uses pipeline structure for
decrypt the information. The unprocessed data is called
repeated computation by lower down speed and data rate is
the plain text, the encrypted data is referred to as the
capable to support USB protocol[l]. Hrushikesh Deshpande
cipher text. To break the password, et al., proposed AES architecture is based on optimizing area
there are different types of attacks that include Brute in terms of reducing number of slices required for design of
force attack, Known plaintext attack, Chosencipher text AES algorithm in YHDL. The AES algorithm optimized
attack, Cipher textattack. The Brute force attack on AES- throughput per number of slices. Efficiency parameter being
128 bit up to 5th roundand the further analysis get stop. the reliable one for purposes of comparison with other
There are various algorithms available in cryptography platform like ASIC, ALTERA designs[5]. Yuwen Zhu,
like MARS, RSA, TWOFISH, SERPENT and Hongqi Zhang and Yibao Bao et ai., proposed AES
RIJNDAEL. Advanced Encryption Standard is called as a realization method on the reconfigurable hardware ideas, the
Rijndael Cryptography. AES is better than Data design uses a state machine to control encryption round
Encryption Standard (DES). The DES algorithm broken module according to the different lengths. The design using
because of short keys.AES can be implemented both on HDL Verilog to support serial key length 1281192/256 bits
hardware and software. Main aim of AES hardware AES encryption and decryption circuit[7]. R.y. Kshirsagar,
implementation to minimize hardware and lower the M.V. Vyawahare et al., proposed high data throughput AES
power consumption and also maintain high throughput at hardware architecture by partitioning 10 rounds into sub
highest operating frequency [1]. blocks of repeated AES modules. The key feature is having
AES is a symmetric encryption algorithm process high throughput by partitioning the AES into 10 sub-blocks
data in block of 128 bits. A 128-bit block is encrypted by with intermediate buffer between them , thus creating a deep
transforming it in a same way into a new block of the pipelining structure for complete 10 AES blocks. [9].
same size. The only secret necessary to keep for security is
III. PROPOSED WORK
the key. AES algorithm with encryption and decryption
was desgin in Verilog Hardware Description Language. The AES block diagram, the encryption part of this
Thel28-bit plaintext, 128-bit key expansion and 128-bit algorithm, the data to be secured or encrypted is called a
output data all divided into four 32-bit consecutive units plain text (M). The length of plain text will be of 128 bits,

978-1-4673-8587-9/16/$31 .00 ©2016 IEEE [1]

 1st IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES-2016)

with a cipher key/ shared key (K) of 256 bits. The plain B. Steps
text (M) and shared key (K) will be converted into cipher
text (C) using Encryption part of Rijndael algorithm. In • Initial Round: In initial round128 bit cipher key
is EXOR with 128 bit plain text in the form state
the decryption part, the cipher text (C) will be considered
matrix [4x4].
as the input, which will be again operated with the shared
key (K). Following are the terminologies which are widely • Sub-Byte: The Sub byte transformation is done
used in ciphering: using a once-precalculated substitution Table called
S-box. AES S- box is 256 bit, the Table consist of
• Plain Text: Plain text is the information a sender
two transformations such as multiplicative inverse
wishes to transmit to one or more receiving
in Galois field GF (Y'8) and affine transformation.
Medias. Plain text refers to any message that is
not encrypted. • Encryption S-Box:

-
y
• Encryption Algorithm: The encryption part of 0 1 2 3 4 5 6 7 8 9 b c d e f

-"
0 k 77 Th H ~ H ~ ~ ~ n Th ~ ~ ~ 76
Rijndael algorithm encodes plain text into the 1 ~ ~ u ~ 59 47 ~ ~ ~ d d % d H ~

cipher text by performing several operations 2 M

" 26 36 II n = d n 71 31

•
~ ~ ~ ~ ~
3 04 ~ 23 ~ 18 96 05 h 07 12 80 d 27 ~ H

--
which will be discuss in algorithm. 4
5
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84
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• Shared K ey: Shared key is a particular 256 bit key 6 ~ ~ fu 43
"N 33 85 45 f9 ~ 7f R k 9f d

- -" - -
7 M d 40 8f H 38 ~ ~ hl ~ 21 10 ff H ~

generated by the key schedule. It can also be called x 8

as Secret or cryptographic key that is used by the

9
cl
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81
13
4f ~
M
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h
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46
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64
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19
~
n
~
~ H h ~ 49 06 24 ~ d a u 91 95 e4 79

Key Expansion to generate a set of Round Keys -

b ~ d 37 M U ~ h _9 k 56 e 7_ 08

-
c ~ 78 25 h k d ~ c6 d ~ 74 1f ~ W ~ h
H M
• Cipher Text: It is the result of encryption d 70 ~ hl 66 48 ~ f6 ~ U ~ 86 ci ~ h

""
performed on the plain text and shared kay using
e
f
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k "
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89
11
N
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e6
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42
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41
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99
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algorithm. It is the encrypted form ofthe plain text. Fig. 3: AES Encryption S-Box
• Decryption Algorithm: The decryption part of
Rijndael algorithm decodes the cipher text into • Shift Rows: In shift row operation, rows of state
plain text. are cyclically shifted with a certain number of
Encryption
steps. The bytes are arranged in the form of
P l a inText
J\f
Algoritbm
C - E(M,K) matrix. The first row of the matrix is unchanged,
the second row is shifted by one byte, the third is
shifted by two bytes and the fourth row is shifted
C iphe r
Text by 3 positions to the left.
C
• Mixcolumns: Mixcolumns transformation deals
independently with every column of the state array.
To calculate the Mixcolumn transformation, the
columns of the present state are considered as
polynomials over GF(21\8).If the multiplication of
the columns exceeds 21\8 then the resultant
polynomial go beyond the GF and the algorithm
will not work. hence to bring back the polynomial
Fig. 1: Block Diagram of AES in the field it is multiplied by an irreducible
polynomial.
A. AES Encryption Algorithm • Add Round Key: The round key is applied to the
resultant polynomial from mix column by
lip 32'S- 25Sbito Pla in Text
performing bitwise EXOR operation between the
resultant polynomial and new cipher key
generated by key schedule into four rounds of 32
bit round operating elements.
~ _ .. ~_~ ' L_ : 113roonds
• Last Round: The final round is 128 bit processor
after thirteen rounds of operation included
TheClpher Text
Key Expansion 128 bb shiftrows, sub bytes and mi column s, 128bit
intermediate encrypted data will be used in
., EXOR operation with the final expanded key
B<t (4*32 bit),which is provided by key expansion
E9 module. The output of final round in processor is
AddRoundKev
desired 128 bit ciphertext, The ciphertext is
divided into four packets of 32 bit data by an
Fig. 2: Block Diagram of Rijndael AE S Encryption Algorithm external enable signal.

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 1st IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES-2016)

IV. METHODOLOGY [2] Wenfeng Zhao, Yajun HaandMassimoAiioto,"Novel Self-Body-

Biasing and Statistical Design for Near-Threshold Circuits With
1. Implementation of AES encryption algorithm Ultra Energy-Efficient AES as Case Study",IEEE transactions on
using VHDL to convert plaintext into ciphertext very large scale integration (VLSI) systems, vol. 23, no . 8, august
2015.
with initial key.
[3] MostafaTaha, and PatrickSchaumont,"Key Updating for Leakagez
2. Implementation of AES decryption algorithm using Resiliency With Application to AES Modes of Operation",IEEE
VHDL will giving the output of encryption to the transactions on information forensic s and security, vol. 10, no. 3,
decryption module to get same output will be march 2015.
regenerated the original plaintext with same key. [4] Franck Courbon, Jacques J. A. Fournier,PhilippeLoubet-Moundi,
3. Utilizing pipeline technology in the round and AssiaTria, "Combining Image Processing and Laser Fault
transformation for high throughput. Injections for Characterizing a Hardware AES",IEEE transactions
on computer-aided design of integrated circuits and systems, vol.
4. Optimizing the design to keep balance between 34, no. 6, June 2015.
throughput and area. [5] Hrushikesh.SDeshpande,KailasJ.KarandeAltaaf.O.Mulani,"Efficie
5. To implement the AES encryption and decryption nt implementation of AES algorithm on FPGA",lnternational
on FPGA for the verification of the design. Conference on Communication and Signal Processing, April 3-5,
2014, India.
V. CONCLUSION [6] Kyungtae Kang, Member, IEEE, JunheeRyu, and Dong Kun Noh,
" Accommodating the Variable Timing of Software AES
The Rijndael cipher design is well suited for hardware Decryption on Mobile Receiver",IEEE systems journal, vol. 8, no.
use. This implementation can be carried out through 3, September 2014.
different trade-offs between area and speed. The trade-offs [7] Yuwen Zhu, Hongqi Zhang, YibaoBao, "Study of the AES
is that AES requires additional power and may not be realization method on the reconfigurable hardware",2013
supported by hardware, also there is wide range of International conference on Computer Science and application.
equipment used for encryption which is needed for [8] An Wang, Man Chen, Zongyue Wang, and Xiaoyun Wang, "Fault
Rate Analysis: Breaking Masked AES Hardware Implementations
authentication and security. AES can be programmed in Efficiently",IEEE transactions on circuits and systems-ii : express
software or built with pure hardware. The AES is the latest briefs, vol. 60, no. 8, august 2013.
standard for cryptography and has been taken wide [9] Dr. R.V. Kshirsagar, M.V.Vyawahare, " FPGA implementation of
support to secure digital data. high speed VLSI Architecture for AES algorithm", 2012 fifth
International Conferernce on emerging trends in engineering and
REFERENCES technology.
[10] Bin Liu and Bevan M. Baas, " Parallel AES Encryption Engines for
[I] Pritamkumar N . Khose, Prof. Vrushali G. Raut, "Implementation of
Many-Core Processor Arrays",IEEE transactions on computers,
AES Algorithm on FPGA for Low Area Consumption",2015
vol. 62, no. 3, march 2013.
International Conference on Pervasive Computing (JCPC).

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