Computer Architecture (BCAC201) -

Comprehensive Detailed Notes

Unit 1: Data Representation (Expanded)

Number Systems
 Decimal Number System (Base-10): Uses digits 0–9. It is the standard system for
human-centric arithmetic operations. Each digit has a place value that is a power of 10.
 Binary Number System (Base-2): Uses only 0 and 1. Used internally by digital
computers and devices due to its compatibility with binary logic (transistors).
 Octal Number System (Base-8): Uses digits 0 to 7. Often used in computing as a
shorthand for binary (3 bits = 1 octal digit).
 Hexadecimal Number System (Base-16): Uses 0–9 and A–F. Widely used in
programming and digital systems to represent binary data more compactly (4 bits = 1
hex digit).
 Alphanumeric Representation: Used for text processing and communication. Includes
letters, digits, and symbols encoded using standards like ASCII or Unicode.

Complements
 1’s Complement: Represents negative numbers by inverting all bits of the number. For
example, 1’s complement of 1010 is 0101.
 2’s Complement: Adds 1 to the 1’s complement. It simplifies arithmetic logic because
subtraction can be implemented as addition of a negative number.
 9’s Complement: Found by subtracting each digit of a decimal number from 9. Used in
manual decimal subtraction.
 10’s Complement: Found by adding 1 to the 9’s complement. It is the decimal analog of
2’s complement.
 [r-1]’s and r’s Complement: Generalization of complements for any base r. Used for
error detection and subtraction in non-decimal systems.

Fixed Point Representation

 In fixed-point representation, numbers are stored with a fixed number of digits after the
binary (or decimal) point.
 Typically used when hardware does not support floating point or for performance
reasons in embedded systems.
 Signed values are typically stored using 2’s complement. Overflow occurs when the
result exceeds the storage range.
Floating Point Representation
 Floating point uses scientific notation, i.e., numbers are represented in the form:
±mantissa × base^exponent.
 Provides a wide range of values suitable for scientific and real-world calculations.
 Includes normalization (adjusting mantissa so only one non-zero digit is to the left of
the point).

IEEE 754 Floating Point Representation

 IEEE 754 is a standard for floating-point arithmetic used in computers.
 Single Precision (32-bit): 1 bit for sign, 8 bits for exponent, 23 bits for mantissa
(fractional part).
 Double Precision (64-bit): 1 bit for sign, 11 bits for exponent, 52 bits for mantissa.
 Supports special values: Zero, Infinity, NaN (Not a Number), denormalized numbers for
very small magnitudes.
 Bias is used in exponent: For single precision, bias = 127. Actual exponent = stored
exponent - bias.

Unit 2: Computer Arithmetic (Expanded)

Arithmetic Operations
 Sign Magnitude Addition: Both numbers have sign bits. If signs are the same, add
magnitudes; if different, subtract the smaller magnitude from the larger and keep the
sign of the larger.
 2’s Complement Addition: Handles positive and negative numbers uniformly. Add both
binary numbers and discard any final carry out.
 2’s Complement Subtraction: Convert the subtrahend to its 2’s complement and perform
binary addition.
 Example: 5 - 3 = 5 + (-3) = 0101 + 1101 = 0010 (2 in decimal)

Multiplication Algorithms
 Binary Multiplication: Similar to decimal long multiplication. Shift multiplicand and add
to partial products based on the bits of multiplier.
 Booth’s Algorithm: Optimizes multiplication of signed binary numbers by encoding
strings of 1s in the multiplier to reduce the number of additions/subtractions.

Division Algorithms
 Restoring Division: Subtract divisor from partial dividend, restore if result is negative.
 Non-Restoring Division: Continues without restoring the dividend even if result is
negative, simplifies logic.

Overflow Detection
 Occurs when the result of an arithmetic operation exceeds the range that can be
represented with the given number of bits.
 In 2’s complement: Overflow when adding two positives yields a negative, or two
negatives yield a positive.

Unit 3: Register Transfer and Micro-Operations (Expanded)

Register Transfer Language (RTL)

 RTL is used to describe operations at the register level using symbolic notation.
 Example: R1 <- R2 means data in R2 is transferred to R1.

Bus System for Registers

 A bus is a shared communication pathway. It allows multiple registers to send and
receive data efficiently through multiplexing.

Memory Transfers
 Memory Read: Data is fetched from memory and placed into a register (e.g., MDR).
 Memory Write: Data in a register is written to a memory location.

Micro-Operations
 Arithmetic: ADD, SUB, INCREMENT, DECREMENT, etc.
 Logic: AND, OR, NOT, XOR for performing bitwise logical operations.
 Shift: Logical (fills with 0), Arithmetic (maintains sign), Circular (rotates bits).
 Register Transfer: Simple move of data from one register to another.

Other Circuits
 Binary Adder/Subtractor: A single circuit capable of both addition and subtraction
based on a control input.
 Incrementer: Adds 1 to its input binary number.
 Masking: Logical operation to isolate or zero out specific bits.
 Selective Operations: Used to set, clear or complement specific bits using control logic.

Unit 4: Basic Computer Organization and Design (Expanded)

Instruction Codes
 Binary representations of operations supported by the computer. Each instruction
includes an opcode and possibly operand addresses.
 Example: ADD 1000 might mean 'add the contents of memory location 1000 to the
accumulator'.

Basic Registers
 AC (Accumulator): Temporary storage for arithmetic and logic results.
 DR (Data Register): Holds memory operands.
 AR (Address Register): Holds memory addresses.
 IR (Instruction Register): Stores the current instruction.
 PC (Program Counter): Points to the next instruction to be executed.

Addressing Modes
 Direct: Address field contains the effective address of operand.
 Indirect: Address field contains the location of memory that holds the address of the
operand.
 Effective Address: The final address where data is located or needs to be stored.

Instruction Types
 Memory Reference: Operate on memory data (e.g., LDA, STA).
 Register Reference: Operate on CPU registers (e.g., CLA, CMA).
 Input/Output: Control external devices (e.g., INP, OUT).

Instruction Cycle
 Fetch: Get instruction from memory.
 Decode: Determine operation and addressing mode.
 Execute: Perform the specified operation.
 Store: Save results back if necessary.

Unit 5: Microprogrammed Control (Expanded)

Control Memory
 Microprogrammed control uses a control memory to store microinstructions that define
the control signals for each machine instruction.
 Each instruction in the control memory triggers a sequence of control signals required
to execute machine-level instructions.

Microinstructions and Microprograms

 Microinstruction: A binary control word that specifies one or more micro-operations to
be executed.
 Microprogram: A sequence of microinstructions that perform a complete machine
instruction.

Address Sequencing
 Defines how the address of the next microinstruction is determined.
 Can be linear (incrementing) or based on branching (conditional/unconditional).

Advantages of Microprogrammed Control

 Easier to modify and understand compared to hardwired control.
 More flexible in implementing complex instruction sets.
Unit 6: Central Processing Unit (Expanded)

General Register Organization

 Uses multiple registers to allow for fast access to data and instructions.
 Includes control logic for selecting source and destination registers and ALU operations.

Stack Organization
 LIFO structure useful for evaluating expressions and managing subroutine calls.
 PUSH inserts data into the top of the stack, and POP removes it.
 Implemented using a register called Stack Pointer (SP).

Instruction Formats
 Specifies the layout of bits in an instruction, typically including operation code (opcode),
addressing mode bits, and operand fields.
 Formats vary depending on CPU architecture.

CPU Organization Types

 Single Accumulator: All operations done using the accumulator register.
 General Register: Uses multiple registers for intermediate storage.
 Stack Organization: Operands are implicitly taken from the stack top.

Instruction Types
 Three-address: Specifies two sources and one destination.
 Two-address: One source is overwritten.
 One-address: Uses accumulator implicitly.
 Zero-address: Uses stack-based operations (e.g., postfix expressions).

Instruction Classification
 Data Transfer: MOV, LOAD, STORE.
 Data Manipulation: ADD, SUB, AND, OR.
 Program Control: JMP, CALL, RETURN.

Interrupts
 External: I/O operations or user actions.
 Internal: Errors like division by zero or overflow.
 Software: Generated by instructions such as system calls.

RISC vs CISC
 RISC (Reduced Instruction Set Computing): Simple instructions, uniform instruction
format, faster execution.
 CISC (Complex Instruction Set Computing): Rich set of instructions, fewer instructions
per program, complex decoding.
Unit 7: Pipeline and Vector Processing (Expanded)

Flynn’s Classification
 SISD: Single instruction, single data stream.
 SIMD: Single instruction, multiple data streams. Suitable for parallel tasks.
 MISD: Rare in practice. Multiple instructions on single data stream.
 MIMD: Multiple instruction and data streams. Used in multiprocessor systems.

Pipelining
 Breaks instruction execution into discrete stages that operate in parallel.
 Improves instruction throughput. Ideal speedup = number of stages.

Space-Time Diagram
 Shows the overlap of instruction execution over time across pipeline stages.

Speedup
 Speedup = Time without pipelining / Time with pipelining.
 Not linear due to overheads and pipeline hazards.

Arithmetic Pipeline
 Used to implement arithmetic operations like floating-point addition, multiplication.
 Divides operation into smaller sub-operations performed in pipeline stages.

Unit 8: Input – Output Organization (Expanded)

Peripheral Devices
 Include keyboards, mice, printers, scanners, disk drives, etc.
 Interface with CPU through I/O ports and controllers.

Input – Output Interfaces

 Connect CPU to peripheral devices, handling electrical and timing characteristics.
 Examples include PCI, USB, and SATA interfaces.

I/O Techniques
 Isolated I/O: Separate I/O address space.
 Memory Mapped I/O: Devices are addressed as if they are memory locations.

Asynchronous Data Transfer

 Strobe Method: Uses a single control line to indicate data validity.
 Handshaking: Uses two-way signals (e.g., Request and Acknowledge) for
synchronization.
I/O Modes
 Programmed I/O: CPU actively waits and handles I/O operations.
 Interrupt Initiated I/O: CPU is interrupted when device is ready, improving efficiency.
 DMA: Direct Memory Access allows devices to transfer data without CPU involvement.

Unit 9: Memory Organization (Expanded)

Memory Hierarchy
 Organized by access speed and cost. Registers > Cache > Main Memory > Secondary
Storage.
 Higher levels are faster and more expensive; lower levels are slower and cheaper.

Main Memory
 RAM: Volatile memory used for active processes.
 SRAM: Faster and expensive, used in cache.
 DRAM: Slower and cheaper, used in main memory.
 ROM: Non-volatile memory for permanent storage.

Cache Memory
 Small, fast memory placed between CPU and RAM.
 Mapping Techniques:
 Direct Mapping: Each block maps to exactly one cache line.
 Associative Mapping: Any block can go into any cache line.
 Set-Associative Mapping: A combination of both.

CAM (Content Addressable Memory)

 Also known as associative memory. Accessed by content rather than address.
 Used in TLB (Translation Lookaside Buffer) and fast lookups.

Virtual Memory
 Provides illusion of large memory using disk space.
 Divides memory into pages or segments.
 Handles page faults and uses TLB for address translation.

Auxiliary Memory
 Non-volatile memory such as hard disks, SSDs, CDs, magnetic tapes.
 Used for long-term data storage.

Timing Terminologies
 Seek Time: Time to move the read/write head to desired track.
 Rotational Delay: Time waiting for desired sector to rotate under head.
 Access Time: Sum of seek time and rotational delay.
 Transfer Time: Time taken to actually read/write the data.
 Latency: Overall delay in data retrieval.