Course

Course Credits
Course Syllabus
 1. The Intel Microprocessors 8086
Architecture
• 1 The Intel Microprocessors 8086 Architecture
• 1.1 8086CPU Architecture,
• 1.2 Programmer’s Model
• 1.3 Functional Pin Diagram
• 1.4 Memory Segmentation
• 1.5 Banking in 8086
• 1.6 Demultiplexing of Address/Data bus
• 1.7 Functioning of 8086 in Minimum mode and
Maximum mode
• 1.8 Timing diagrams for Read and Write operations in
minimum and maximum mode
• 1.9 Interrupt structure and its servicing
 8086
Microprocessor

Overview
First 16- bit processor
released by INTEL in the year
1978

Originally HMOS, now

manufactured using HMOS
III technique

Approximately 29, 000

transistors, 40 pin DIP, 5V
supply

Does not have internal clock;

external asymmetric clock
source with 33% duty cycle

20-bit address to access

memory ⇒ can address up to
220 = 1 megabytes of
8
memory space.
 8086
Microprocessor

Architecture

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions BIU fetches instructions,

that have already been reads data from memory
fetched by the BIU. and I/O ports, writes data
to memory and I/ O ports.
BIU and EU functions 9
separately.
 8086
Bus Interface Unit
Microprocessor
(BIU)
ArchitectureDedicated Adder to
generate 20 bit
address

Four 16-bit segment

registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

Segment Registers >> 10

 8086
Bus Interface Unit
Microprocessor
(BIU)
Architecture
Segment Code Segment Register
Registers
• 16-bit

• CS contains the base or start of the current code

segment; IP contains the distance or offset from this
address to the next instruction byte to be fetched.

• BIU computes the 20-bit physical address by logically

shifting the contents of CS 4-bits to the left and then
adding the 16-bit contents of IP.

• That is, all instructions of a program are relative to the

contents of the CS register multiplied by 16 and then
offset is added provided by the IP.

11
 8086
Bus Interface Unit
Microprocessor
(BIU)
Architecture
Segment Data Segment Register
Registers
• 16-bit

• Points to the current data segment; operands for most

instructions are fetched from this segment.

• The 16-bit contents of the Source Index (SI) or

Destination Index (DI) or a 16-bit displacement are used
as offset for computing the 20-bit physical address.

12
 8086
Bus Interface Unit
Microprocessor
(BIU)
Architecture
Segment Stack Segment Register
Registers
• 16-bit

• Points to the current stack.

• The 20-bit physical stack address is calculated from the

Stack Segment (SS) and the Stack Pointer (SP) for stack
instructions such as PUSH and POP.

• In based addressing mode, the 20-bit physical stack

address is calculated from the Stack segment (SS) and the
Base Pointer (BP).

13
 8086
Bus Interface Unit
Microprocessor
(BIU)
Architecture
Segment Extra Segment Register
Registers
• 16-bit

• Points to the extra segment in which data (in excess of

64K pointed to by the DS) is stored.

• String instructions use the ES and DI to determine the

20-bit physical address for the destination.

14
 8086
Bus Interface Unit
Microprocessor
(BIU)
Architecture
Segment Instruction Pointer
Registers
• 16-bit

• Always points to the next instruction to be

executed within the currently executing
code segment.

• So, this register contains the 16-bit offset

address pointing to the next instruction
code within the 64Kb of the code segment
area.

• Its content is automatically incremented

as the execution of the next instruction
takes place.

15
 8086
Bus Interface Unit
Microprocessor
(BIU)
Architecture
Instruction queue

• A group of
First-In-First-Out (FIFO)
in which up to 6 bytes
of instruction code are
pre fetched from the
memory ahead of time.

• This is done in order to

speed up the execution
by overlapping
instruction fetch with
execution.

• This mechanism is
known as pipelining.

16
 8086
Execution Unit (EU)
Microprocessor

EU decodes and Architecture

executes
instructions.

A decoder in the
EU control
system translates
16-bit ALU for
instructions.
performing
arithmetic and
logic operation
Four general
purpose
registers(AX, BX,
CX, DX);

Pointer registers
(Stack Pointer,
Base Pointer);

and Some of the 16 bit registers

can be used as two 8 bit
Index registers registers as :
(Source Index,
Destination Index) AX can be used as AH and AL
each of 16-bits BX can be used as BH and BL 17
CX can be used as CH and CL
 8086
Execution Unit (EU)
Microprocessor

Architecture
EU Accumulator Register (AX)
Registers
• Consists of two 8-bit registers AL and AH,
which can be combined together and used
as a 16-bit register AX.

• AL in this case contains the low order byte

of the word, and AH contains the
high-order byte.

• The I/O instructions use the AX or AL for

inputting / outputting 16 or 8 bit data to
or from an I/O port.

• Multiplication and Division instructions

also use the AX or AL.

18
 8086
Execution Unit (EU)
Microprocessor

Architecture
EU Base Register (BX)
Registers
• Consists of two 8-bit registers BL and BH,
which can be combined together and used
as a 16-bit register BX.

• BL in this case contains the low-order byte

of the word, and BH contains the
high-order byte.

• This is the only general purpose register

whose contents can be used for addressing
the 8086 memory.

• All memory references utilizing this

register content for addressing use DS as
the default segment register.

19
 8086
Execution Unit (EU)
Microprocessor

Architecture
EU Counter Register (CX)
Registers
• Consists of two 8-bit registers CL and CH,
which can be combined together and used
as a 16-bit register CX.

• When combined, CL register contains the

low order byte of the word, and CH
contains the high-order byte.

• Instructions such as SHIFT, ROTATE and

LOOP use the contents of CX as a counter.

Example:

The instruction LOOP START

automatically decrements CX by 1
without affecting flags and will check if
[CX] = 0.

If it is zero, 8086 executes the next

instruction; otherwise the 8086 branches
to the label START.
20
 8086
Execution Unit (EU)
Microprocessor

Architecture
EU
Registers

21
 8086
Execution Unit (EU)
Microprocessor

Architecture
EU Stack Pointer (SP) and Base
Registers Pointer (BP)

• SP and BP are used to access data in the

stack segment.

• SP is used as an offset from the current SS

during execution of instructions that
involve the stack segment in the external
memory.

• SP contents are automatically updated

(incremented/ decremented) due to
execution of a POP or PUSH instruction.

• BP contains an offset address in the

current SS, which is used by instructions
utilizing the based addressing mode.

22
 8086
Execution Unit (EU)
Microprocessor

Architecture
EU Source Index (SI) and Destination
Registers Index (DI)

• Used in indexed addressing.

• Instructions that process data strings use

the SI and DI registers together with DS
and ES respectively in order to distinguish
between the source and destination
addresses.

23
 8086
Execution Unit (EU)
Microprocessor

Architecture
EU Source Index (SI) and Destination
Registers Index (DI)

• Used in indexed addressing.

• Instructions that process data strings use

the SI and DI registers together with DS
and ES respectively in order to distinguish
between the source and destination
addresses.

24
 8086
Execution Unit (EU)
Microprocessor

Architecture
Auxiliary Carry Flag
Carry Flag
This is set, if there is a carry
Flag Register from the lowest nibble, i.e, This flag is set, when
bit three during addition, or there is a carry out of
borrow for the lowest nibble, MSB in case of
i.e, bit three, during addition or a borrow
subtraction.
Zero Flag in case
Parity of subtraction.
Flag
Sign Flag
This flag is set, if the This flag is set to 1, if
This flag is set, result of the the lower byte of the
when the result of computation or result contains even
any computation is comparison performed number of 1’s ; for odd
negative by an instruction is number of 1’s set to
zero zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF
Tarp Flag
Over flow Flag If this flag is set, the
This flag is set, if an overflow occurs, i.e, if the processor enters the
result of a signed operation is large enough to single step execution
accommodate in a destination register. The
mode by generating
result is of more than 7-bits in size in case of
8-bit signed operation and more than 15-bits in internal interrupts after
size in case of 16-bit sign Direction
operations, Flag
then the the execution of each
overflow
This is will
usedbe set.
by string manipulation instruction
Interrupt Flag
instructions. If this flag bit is ‘0’, the string is
processed beginning from the lowest address Causes the 8086 to
to the highest address, i.e., auto recognize external mask
incrementing mode. Otherwise, the string is interrupts; clearing IF
processed from the highest address towards disables these interrupts. 25
the lowest address, i.e., auto incrementing
 8086
Microprocessor Architecture

8086
registers 1
5
1
4
1
3
1
2
11 10 9 8 7 6 5 4 3 2 1 0

categorize
O D IF TF S Z AF P C
d into 4 F F F F F F

groups

Sl.No Type Register Name of register

. width
1 General purpose 16 bit AX, BX, CX, DX
register
8 bit AL, AH, BL, BH, CL, CH,
DL, DH
2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register 26