1. Explain the important blocks of a computer ?

Various Components of Computer

Computer is an electronic device which performs tasks given by user with

extremely fast speed and accuracy. Like any other device or machine, a computer
system has also a number of parts. A computer system can be blocked into mainly
three parts:

1. Input Unit
2. Central Processing Unit
3. Output Unit

1. Input unit – Input unit is a unit that accepts any input device. The input device is
used to input data into the computer system.

Function of input unit:

1. It converts inputted data into binary codes.

2. It sends data to main memory of computer .

2. Central Processing Unit (CUP) – CPU is called the brain of a computer. An

electronic circuitry that carries out the instruction given by a computer program.

CPU can be sub classified into three parts.

i .Control unit (CU) ii. Arithmetic & Logic unit (ALU)

The main function of the control unit is to fetch and execute instructions from the
memory of a computer.
i. Control unit (CU)- the control unit manages the various components of the
computer. It reads instructions from memory and interpretation and changes in a
series of signals to activate other parts of the computer. It controls and co-ordinate
is input output memory and all other units.

ii. Arithmetic & Logic unit (ALU) – The arithmetic logic unit (ALU), which performs
simple arithmetic operation such as +,-, *, / and logical operation such as >, <, =<,
<= etc.

iii. Memory Unit (MU)- Memory is used to store data and instructions before and
after processing. Memory is also called Primary memory or internal memory. It is
used to store data temporary or permanently.

Function of CPU-

1. It controls all the parts and software and data flow of computer.
2. It performs all operations.
3. It accepts data from input device.
4. It sends information to output device.
5. Executing programs stored in memory
6. It stores data either temporarily or permanent basis.
7. It performs arithmetical and logical operations.

3. Output Unit –Output unit is a unit that constituents a number of output device. An
output device is used to show the result of processing.

Function of Output unit:

1. it accepts data or information sends from main memory of computer

2. It converts binary coded information into HLL or inputted languages.

2. Explain the architecture of 8086 with neat diagram

8086 Microprocessor is divided into two functional units, i.e., EU (Execution Unit)

and BIU (Bus Interface Unit).

EU (Execution Unit)
Execution unit gives instructions to BIU stating from where to fetch the data and

then decode and execute those instructions. Its function is to control operations

on data using the instruction decoder & ALU. EU has no direct connection with

system buses as shown in the above figure, it performs operations over data

through BIU.

Let us now discuss the functional parts of 8086 microprocessors.

ALU
It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT

operations.

Flag Register
It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status

according to the result stored in the accumulator. It has 9 flags and they are

divided into 2 groups − Conditional Flags and Control Flags.

Conditional Flags
It represents the result of the last arithmetic or logical instruction executed.

Following is the list of conditional flags −

● Carry flag − This flag indicates an overflow condition for arithmetic

operations.

● Auxiliary flag − When an operation is performed at ALU, it results

in a carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble

(i.e. D4 – D7), then this flag is set, i.e. carry given by D3 bit to D4 is
 AF flag. The processor uses this flag to perform binary to BCD

conversion.

● Parity flag − This flag is used to indicate the parity of the result, i.e.

when the lower order 8-bits of the result contains even number of

1’s, then the Parity Flag is set. For odd number of 1’s, the Parity

Flag is reset.

● Zero flag − This flag is set to 1 when the result of arithmetic or

logical operation is zero else it is set to 0.

● Sign flag − This flag holds the sign of the result, i.e. when the result

of the operation is negative, then the sign flag is set to 1 else set to

0.

● Overflow flag − This flag represents the result when the system

capacity is exceeded.

Control Flags
Control flags controls the operations of the execution unit. Following is the list

of control flags −

● Trap flag − It is used for single step control and allows the user to

execute one instruction at a time for debugging. If it is set, then the

program can be run in a single step mode.

● Interrupt flag − It is an interrupt enable/disable flag, i.e. used to

allow/prohibit the interruption of a program. It is set to 1 for

interrupt enabled condition and set to 0 for interrupt disabled

condition.

● Direction flag − It is used in string operation. As the name suggests

when it is set then string bytes are accessed from the higher

memory address to the lower memory address and vice-a-versa.

General purpose register
There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL.

These registers can be used individually to store 8-bit data and can be used in

pairs to store 16bit data. The valid register pairs are AH and AL, BH and BL, CH

and CL, and DH and DL. It is referred to the AX, BX, CX, and DX respectively.

● AX register − It is also known as accumulator register. It is used to

store operands for arithmetic operations.

● BX register − It is used as a base register. It is used to store the

starting base address of the memory area within the data segment.

● CX register − It is referred to as counter. It is used in loop instruction

to store the loop counter.

● DX register − This register is used to hold I/O port address for I/O

instruction.

Stack pointer register

It is a 16-bit register, which holds the address from the start of the segment to

the memory location, where a word was most recently stored on the stack.

BIU (Bus Interface Unit)

BIU takes care of all data and addresses transfers on the buses for the EU like

sending addresses, fetching instructions from the memory, reading data from the

ports and the memory as well as writing data to the ports and the memory. EU

has no direction connection with System Buses so this is possible with the BIU.

EU and BIU are connected with the Internal Bus.

It has the following functional parts −

● Instruction queue − BIU contains the instruction queue. BIU gets

upto 6 bytes of next instructions and stores them in the instruction

queue. When EU executes instructions and is ready for its next

instruction, then it simply reads the instruction from this instruction

queue resulting in increased execution speed.

● Fetching the next instruction while the current instruction executes

is called pipelining.

● Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It

holds the addresses of instructions and data in memory, which are

used by the processor to access memory locations. It also contains 1

pointer register IP, which holds the address of the next instruction

to executed by the EU.

○ CS − It stands for Code Segment. It is used for

addressing a memory location in the code segment of

the memory, where the executable program is stored.

○ DS − It stands for Data Segment. It consists of data

used by the program andis accessed in the data

segment by an offset address or the content of other

register that holds the offset address.

○ SS − It stands for Stack Segment. It handles memory to

store data and addresses during execution.

○ ES − It stands for Extra Segment. ES is additional data

segment, which is used by the string to hold the extra

destination data.

● Instruction pointer − It is a 16-bit register used to hold the address

of the next instruction to be executed.

3. Explain the difference between Von-Neumann vs Harvard
Architecture?

Parameters Von Neumann Architecture Harvard Architecture

Definition The Von Neumann Harvard Architecture is a modern

Architecture is an ancient type of computer architecture that
type of computer architecture follows the concept of the
that follows the concept of a relay-based model by Harvard
stored-program computer. Mark I.

Physical It uses one single physical It uses two separate physical

Address address for accessing and addresses for storing and
storing both data and accessing both instructions and
instructions. data.

Buses (Signal One common signal path It uses separate buses for the
Paths) (bus) helps in the transfer of transfer of both data and
both instruction and data. instructions.

Number of It requires two clock cycles It executes any instruction using

Cycles for executing a single only one single cycle.
instruction.

Cost It is comparatively cheaper in It is comparatively more

cost than Harvard expensive than the Von Neumann
Architecture. Architecture.

Access to The CPU is not able to The CPU can easily read/write
CPU read/write data and access data as well as access the
instructions at the same time. instructions at any given time.

Uses This method comes to play in This architecture is best for signal
the case of small computers processing as well as
and personal computers. microcontrollers.
Requirement As compared to Harvard This one requires more hardware.
of Hardware Architecture, Von Neumann It is because it requires separate
Architecture requires lesser sets of data as well as address
architecture. It is because it buses for individual memory.
only needs to reach one
common memory.

Requirement This architecture basically This architecture comparatively

of Space requires less space. requires more space.

Usage of This architecture does not This type of architecture can

Space waste any space. It is result in space wastage. It is
because the instruction because the instruction memory
memory can utilize the left cannot utilize the leftover space in
space of the data memory. It the data memory. It also cannot
can also happen vice-versa. happen vice-versa.

Execution The speed of execution of the The overall speed of execution of

Speed Von Neumann Architecture is Harvard Architecture is
comparatively slower. It is comparatively faster. It is because
because it is not capable of the processor, in this case, is
fetching the instructions and capable of fetching both
data both at the same time. instructions and data at the very
same time.

Controlling The process of controlling The process of controlling

becomes comparatively becomes comparatively complex
simpler with this architecture. with this architecture. It is
It is because it fetches either because it basically fetches both
instructions or data at any instructions and data
given time. simultaneously at the very same
time.
4. Difference between RISC and CISC Processor

S.No. RISC CISC

1. RISC is a reduced instruction set. CISC is a complex instruction set.

2. The number of instructions is less The number of instructions is more

as compared to CISC. as compared to RISC.

3. The addressing modes are less. The addressing modes are more.

4. It works in a fixed instruction It works in a variable instruction

format. format.

5. The RISC consumes low power. The CISC consumes high power.

6. The RISC processors are highly The CISC processors are less
pipelined. pipelined.

7. It optimizes the performance by It optimizes the performance by

focusing on software. focusing on hardware.

8. Requires more RAM. Requires less RAM.

5. How do you justify the instruction queue speed of 8086

microprocessor?

The Instruction Queue:

1. The execution unit (EU) is supposed to decode or execute an
instruction.
2. Decoding does not require the use of buses.
3. When EU is busy in decoding and executing an instruction, the BIU
fetches up to six instruction bytes for the next instructions.
4. These bytes are called as the pre-fetched bytes and they are stored in a
first in first out (FIFO) register set, which is called as a queue.
 The 8086/8088 instruction queue is a buffer that holds opcode bytes that
have been prefetched by the bus interface unit. This speed up operations of
the processor by helping to reduce fetches latency, i.e. to improve the
probability that an opcode byte fetched by the processor is already
available.

6. Draw and explain the pin diagram of 8051 micro controller and
8086 microprocessor?

8051 micro controller

 ● Pins 1 to 8 − These pins are known as Port 1. This port doesn’t

serve any other functions. It is internally pulled up, bi-directional I/O

port.

● Pin 9 − It is a RESET pin, which is used to reset the microcontroller

to its initial values.

● Pins 10 to 17 − These pins are known as Port 3. This port serves

some functions like interrupts, timer input, control signals, serial

communication signals RxD and TxD, etc.

● Pins 18 & 19 − These pins are used for interfacing an external

crystal to get the system clock.

● Pin 20 − This pin provides the power supply to the circuit.

● Pins 21 to 28 − These pins are known as Port 2. It serves as I/O

port. Higher order address bus signals are also multiplexed using

this port.

● Pin 29 − This is PSEN pin which stands for Program Store Enable. It

is used to read a signal from the external program memory.

● Pin 30 − This is EA pin which stands for External Access input. It is

used to enable/disable the external memory interfacing.

● Pin 31 − This is ALE pin which stands for Address Latch Enable. It is

used to demultiplex the address-data signal of port.

● Pins 32 to 39 − These pins are known as Port 0. It serves as I/O

port. Lower order address and data bus signals are multiplexed

using this port.

● Pin 40 − This pin is used to provide power supply to the circuit.

8086 microprocessor
Power supply and frequency signals

It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its

operation.

Clock signal

Clock signal is provided through Pin-19. It provides timing to the processor for

operations. Its frequency is different for different versions, i.e. 5MHz, 8MHz and

10MHz.

Address/data bus

AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data

and AD8AD15 carries higher order byte data. During the first clock cycle, it carries

16-bit address and after that it carries 16-bit data.

Address/status bus
A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle,

it carries 4-bit address and later it carries status signals.

S7/BHE

BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the

transfer of data using data bus D8-D15. This signal is low during the first clock

cycle, thereafter it is active.

Read($\overline{RD}$)

It is available at pin 32 and is used to read signal for Read operation.

Ready

It is available at pin 22. It is an acknowledgement signal from I/O devices that data

is transferred. It is an active high signal. When it is high, it indicates that the device

is ready to transfer data. When it is low, it indicates wait state.

RESET

It is available at pin 21 and is used to restart the execution. It causes the processor

to immediately terminate its present activity. This signal is active high for the first 4

clock cycles to RESET the microprocessor.

INTR

It is available at pin 18. It is an interrupt request signal, which is sampled during the

last clock cycle of each instruction to determine if the processor considered this as

an interrupt or not.

NMI

It stands for non-maskable interrupt and is available at pin 17. It is an edge

triggered input, which causes an interrupt request to the microprocessor.

$\overline{TEST}$

This signal is like wait state and is available at pin 23. When this signal is high, then

the processor has to wait for IDLE state, else the execution continues.

MN/$\overline{MX}$

It stands for Minimum/Maximum and is available at pin 33. It indicates what mode

the processor is to operate in; when it is high, it works in the minimum mode and

vice-aversa.

INTA

It is an interrupt acknowledgement signal and id available at pin 24. When the

microprocessor receives this signal, it acknowledges the interrupt.

ALE

It stands for address enable latch and is available at pin 25. A positive pulse is

generated each time the processor begins any operation. This signal indicates the

availability of a valid address on the address/data lines.

DEN

It stands for Data Enable and is available at pin 26. It is used to enable

Transreceiver 8286. The transreceiver is a device used to separate data from the

address/data bus.

DT/R

It stands for Data Transmit/Receive signal and is available at pin 27. It decides the

direction of data flow through the transreceiver. When it is high, data is transmitted

out and vice-a-versa.

M/IO
This signal is used to distinguish between memory and I/O operations. When it is

high, it indicates I/O operation and when it is low indicates the memory operation. It

is available at pin 28.

WR

It stands for write signal and is available at pin 29. It is used to write the data into

the memory or the output device depending on the status of M/IO signal.

HLDA

It stands for Hold Acknowledgement signal and is available at pin 30. This signal

acknowledges the HOLD signal.

HOLD

This signal indicates to the processor that external devices are requesting to access

the address/data buses. It is available at pin 31.

QS1 and QS0

These are queue status signals and are available at pin 24 and 25. These signals

provide the status of instruction queue. Their conditions are shown in the following

table −

QS0 QS1 Status

0 0 No operation

0 1 First byte of opcode from the queue

1 0 Empty the queue

 1 1 Subsequent byte from the queue

S0, S1, S2

These are the status signals that provide the status of operation, which is used by

the Bus Controller 8288 to generate memory & I/O control signals. These are

available at pin 26, 27, and 28. Following is the table showing their status −

S2 S1 S0 Status

0 0 0 Interrupt acknowledgement

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive
LOCK

When this signal is active, it indicates to the other processors not to ask the CPU to

leave the system bus. It is activated using the LOCK prefix on any instruction and is

available at pin 29.

RQ/GT1 and RQ/GT0

These are the Request/Grant signals used by the other processors requesting the

CPU to release the system bus. When the signal is received by CPU, then it sends

acknowledgment. RQ/GT0 has a higher priority than RQ/GT1.

7. Addressing mode of 8051 micro controller .

In 8051 There are six types of addressing modes.

● Immediate AddressingMode

● Register AddressingMode

● Direct AddressingMode

● Register IndirectAddressing Mode

● Indexed AddressingMode

● Implied AddressingMode

Immediate addressing mode

In this Immediate Addressing Mode, the data is provided in the instruction itself.

The data is provided immediately after the opcode. These are some examples of

Immediate Addressing Mode.

MOVA, #0AFH;

MOVR3, #45H;

MOVDPTR, #FE00H;
In these instructions, the # symbol is used for immediate data. In the last

instruction, there is DPTR. The DPTR stands for Data Pointer. Using this, it points

the external data memory location. In the first instruction, the immediate data is

AFH, but one 0 is added at the beginning. So when the data is starting with A to F,

the data should be preceded by 0.

Register addressing mode

In the register addressing mode the source or destination data should be present in

a register (R0 to R7). These are some examples of RegisterAddressing Mode.

MOVA, R5;

MOVR2, #45H;

MOVR0, A;

In 8051, there is no instruction like MOVR5, R7. But we can get the same result by

using this instruction MOV R5, 07H, or by using MOV 05H, R7. But this two

instruction will work when the selected register bank is RB0. To use another

register bank and to get the same effect, we have to add the starting address of

that register bank with the register number. For an example, if the RB2 is selected,

and we want to access R5, then the address will be (10H + 05H = 15H), so the

instruction will look like this MOV 15H, R7. Here 10H is the starting address of

Register Bank 2.

Direct Addressing Mode

In the Direct Addressing Mode, the source or destination address is specified by

using 8-bit data in the instruction. Only the internal data memory can be used in

this mode. Here some of the examples of direct Addressing Mode.

MOV80H, R6;
MOVR2, 45H;

MOVR0, 05H;

The first instruction will send the content of registerR6 to port P0 (Address of Port

0 is 80H). The second one is forgetting content from 45H to R2. The third one is

used to get data from Register R5 (When register bank RB0 is selected) to register

R5.

Register indirect addressing Mode

In this mode, the source or destination address is given in the register. By using

register indirect addressing mode, the internal or external addresses can be

accessed. The R0 and R1 are used for 8-bit addresses, and DPTR is used for 16-bit

addresses, no other registers can be used for addressing purposes. Let us see

some examples of this mode.

MOV0E5H, @R0;

MOV@R1, 80H

In the instructions, the @ symbol is used for register indirect addressing. In the first

instruction, it is showing that theR0 register is used. If the content of R0 is 40H,

then that instruction will take the data which is located at location 40H of the

internal RAM. In the second one, if the content of R1 is 30H, then it indicates that

the content of port P0 will be stored at location 30H in the internal RAM.

MOVXA, @R1;

MOV@DPTR, A;

In these two instructions, the X in MOVX indicates the external data memory. The

external data memory can only be accessed in register indirect mode. In the first

instruction if the R0 is holding 40H, then A will get the content of external RAM
location40H. And in the second one, the content of A is overwritten in the location

pointed by DPTR.

Indexed addressing mode

In the indexed addressing mode, the source memory can only be accessed from

program memory only. The destination operand is always the register A. These are

some examples of Indexed addressing mode.

MOVCA, @A+PC;

MOVCA, @A+DPTR;

The C in MOVC instruction refers to code byte. For the first instruction, let us

consider A holds 30H. And the PC value is1125H. The contents of program

memory location 1155H (30H + 1125H) are moved to register A.

Implied Addressing Mode

In the implied addressing mode, there will be a single operand. These types of

instruction can work on specific registers only. These types of instructions are also

known as register specific instruction. Here are some examples of Implied

Addressing Mode.

RLA;

SWAPA;

These are 1- byte instruction. The first one is used to rotate the A register content

to the Left. The second one is used to swap the nibbles in A.