MIRPUR UNIVERSITY OF SCIENCE AND TECHNOLOGY (MUST), MIRPUR

DEPARTMENT OF ELECTRICAL ENGINEERING

 DIGITAL SYSTEM DESIGN
EE-474

Module No. 03: Basic Verilog Concepts (Cont’d)

Engr. Jabbar Younis

Lecturer

Date: December 04, 2020

 Learning Objectives

• Understand lexical conventions for operators, comments, whitespace, numbers,

strings, and identifiers

• Define the logic value set and data types such as nets, registers, vectors, numbers,
simulation time, arrays, parameters, memories, and strings

• Identify useful system tasks for displaying and monitoring information, and for
stopping and finishing the simulation

• Learn basic compiler directives to define macros and include files.

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 Lecture 1: Key Points

• Data Types

• System Tasks

• Compiler Directives

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 Data Types: Value Set

• Verilog supports four values and eight strengths to model

the functionality of real hardware

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 Value Set
• In addition to logic values, strength levels are often used
to resolve conflicts between drivers of different strengths
in digital circuits.

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 Nets
• Nets represent connections between hardware
elements
• Nets have values continuously driven on them by the
outputs of devices that they are connected to.

• Net a will continuously assume the value computed at the

output of gate g1, which is b & c.

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 Nets

• Nets are declared primarily with the keyword wire

• Nets are one-bit values by default unless they are
declared explicitly as vectors.
• Examples:
• wire a; // Declare net a for the above circuit
• wire b,c; // Declare two wires b,c for the above
circuit
• wire d = 1'b0; // Net d is fixed to logic value 0 at
declaration.

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 Registers
• Registers represent data storage elements
• Registers retain value until another value is placed onto
them.
• Unlike a net, a register does not need a driver
• Register data types are commonly declared by the
keyword reg.
reg reset; // declare a variable reset that can hold its value
initial // this construct will be discussed later
begin
reset = 1'b1; //initialize reset to 1 to reset the digital circuit.
#100 reset = 1'b0; // after 100 time units reset is deasserted.
end

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 Vectors
• Nets or reg data types can be declared as vectors
(multiple bit widths).
• If bit width is not specified, the default is scalar (1-bit).
• Example:
• wire a; // scalar net variable, default
• wire [7:0] bus; // 8-bit bus
• wire [31:0] busA,busB,busC; // 3 buses of 32-bit width.
• reg clock; // scalar register, default

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 Vectors (Cont’d)

• Vectors can be declared at [high# : low#] or [low# :

high#]
• The left number in the squared brackets is always
the most significant bit of the vector.
• In the example shown below, bit 0 is the most
significant bit of vector virtual_addr.
• Example:
• reg [0:40] virtual_addr; // Vector register, virtual
address 41 bits wide
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 Vector Part Select

• It is possible to address bits or parts of vectors

• busA[7] // bit # 7 of vector busA
• bus[2:0] // Three least significant bits of vector bus,
// using bus[0:2] is illegal because the significant
//bit should
// always be on the left of a range specification
• virtual_addr[0:1] // Two most significant bits of
vector virtual_addr

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 Variable Vector Part Select

• Another ability provided in Verilog HDl is to have

variable part selects of a vector
• There are two special part-select operators:
• [<starting_bit>+:width] - part-select increments from
starting bit
• [<starting_bit>-:width] - part-select decrements from
starting bit

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 Variable Vector Part Select (Example)
• reg [255:0] data1; //Little endian notation
• reg [0:255] data2; //Big endian notation
• reg [7:0] byte;
• //Using a variable part select, one can choose parts
• byte = data1[31-:8]; //starting bit = 31, width =8 => data[31:24]
• byte = data1[24+:8]; //starting bit = 24, width =8 => data[31:24]
• byte = data2[31-:8]; //starting bit = 31, width =8 => data[24:31]
• byte = data2[24+:8]; //starting bit = 24, width =8 => data[24:31]

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 Variable Vector Part Select (Example)
• The starting bit can also be a variable. The width has //to be
constant. Therefore, one can use the variable part select //in a
loop to select all bytes of the vector.
for (j=0; j<=31; j=j+1)
byte = data1[(j*8)+:8]; //Sequence is [7:0], [15:8]...
[255:248]
//Can initialize a part of the vector
data1[(byteNum*8)+:8] = 8'b0; //If byteNum = 1,
clear 8 bits [15:8]

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 Integer

• An integer is a general purpose register data type used

for manipulating quantities
• Integers are declared by the keyword integer
• Integers store values as signed quantities.
integer counter; // general purpose variable used as
a counter.
initial
counter = -1; // A negative one is stored in the
counter

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 Real

• Real number constants and real register data types are

declared with the keyword real
• They can be specified in decimal notation (e.g., 3.14) or
in scientific notation (e.g., 3e6, which is 3 x 106 ).
• When a real value is assigned to an integer, the real
number is rounded off to the nearest integer.

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 Real (Example)
real delta; // Define a real variable called delta
initial
begin
delta = 4e10; // delta is assigned in scientific notation
delta = 2.13; // delta is assigned a value 2.13
end
integer i; // Define an integer i
initial
i = delta; // i gets the value 2 (rounded value of 2.13)

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 Time

• Verilog simulation is done with respect to simulation

time
• A time variable is declared with the keyword time
• The system function $time is invoked to get the
current simulation time
time save_sim_time; // Define a time variable
initial
save_sim_time = $time; // Save the current
simulation time
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 Arrays

• Arrays are allowed in Verilog for reg, integer, time, real,

realtime and vector register data types.
• Multi-dimensional arrays can also be declared with
any number of dimensions.
• Arrays are accessed by <array_name>[<subscript>]
• For multi-dimensional arrays, indexes need to be
provided for each dimension

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 Arrays (Example)
• integer count[0:7]; // An array of 8 count variables
• reg bool[31:0]; // Array of 32 one-bit boolean register
variables
• time chk_point[1:100]; // Array of 100 time checkpoint
variables
• reg [4:0] port_id[0:7]; // Array of 8 port_ids; each port_id
is 5 bits wide
• integer matrix[4:0][0:255]; // Two dimensional array of
integers
• reg [63:0] array_4d [15:0][7:0][7:0][255:0]; //Four
dimensional array

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 Arrays (Example)
• It is important not to confuse arrays with net or register vectors.
• A vector is a single element that is n-bits wide.
• On the other hand, arrays are multiple elements that are 1-bit or
n-bits wide.
• Examples of assignments to elements of arrays discussed above
are shown below:
• count[5] = 0; // Reset 5th element of array of count variables
• chk_point[100] = 0; // Reset 100th time check point value
• port_id[3] = 0; // Reset 3rd element (a 5-bit value) of port_id
• array_4d[0][0][0][0][15:0] = 0; //Clear bits 15:0 of the register
accessed by indices [0][0][0][0]

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 Memories
• Memories are modeled in Verilog simply as a one-
dimensional array of registers.
• Each element of the array is known as an element or
word and is addressed by a single array index
• reg mem1bit[0:1023]; // Memory mem1bit with 1K 1-
bit words
• reg [7:0] membyte[0:1023]; // Memory membyte with
1K 8-bit words(bytes)
• membyte[511] // Fetches 1 byte word whose address
is 511.
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 Parameters
• Verilog allows constants to be defined in a module by the
keyword parameter
• Parameters cannot be used as variables
• Parameter types and sizes can also be defined
• parameter port_id = 5; // Defines a constant port_id
• parameter cache_line_width = 256; // Constant
defines width of cache line
• parameter signed [15:0] WIDTH; // Fixed sign and
range for parameter

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 Strings

• Strings can be stored in reg

• The width of the register variables must be large
enough to hold the string
• Each character in the string takes up 8 bits (1 byte)
• If the width of the register is greater than the size of
the string, Verilog fills bits to the left of the string with
zeros.
• If the register width is smaller than the string width,
Verilog truncates the leftmost bits of the string.
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 Strings (cont’d)

• It is always safe to declare a string that is slightly

wider than necessary.
reg [8*18:1] string_value; // Declare a variable that is
18 bytes wide
initial
string_value = "Hello Verilog World"; // String can be
stored in variable

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 System Tasks

• Verilog provides standard system tasks for certain

routine operations
• All system tasks appear in the form $<keyword>
• Operations such as displaying on the screen,
monitoring values of nets, stopping, and finishing are
done by system tasks.

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 System Tasks (Displaying Information)

• $display is the main system task for displaying values

of variables or strings or expressions
• Usage: $display(p1, p2, p3,....., pn);
• p1, p2, p3,..., pn can be quoted strings or variables or
expressions

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 System Tasks (Monitoring Information)
• Verilog provides a mechanism to monitor a signal
when its value changes. This facility is provided by the
$monitor task.
• Usage: $monitor(p1,p2,p3,....,pn);
• $monitor continuously monitors the values of the
variables or signals specified in the parameter list and
displays all parameters in the list whenever the value
of any one variable or signal changes
• Unlike $display, $monitor needs to be invoked only
once

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System Tasks (Monitoring Information)

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 Stopping and Finishing a Simulation

• The task $stop is provided to stop during a simulation

• Usage: $stop;
• The $stop task is used whenever the designer wants to
suspend the simulation and examine the values of
signals in the design
• The $finish task terminates the simulation
• Usage: $finish;

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Stopping and Finishing a Simulation

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 Compiler Directives
• Compiler directives are defined by using the `<keyword>
construct
• We deal with the two most useful compiler directives
• `define
• The `define directive is used to define text macros in
Verilog
• The Verilog compiler substitutes the text of the macro
wherever it encounters a `<macro_name>
• The defined constants or text macros are used in the
Verilog code by preceding them with a ` (back tick).

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Compiler Directives

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 Compiler Directives (cont’d)

• `include
• The `include directive allows you to include entire
contents of a Verilog source file in another Verilog file
during compilation
• Two other directives, `ifdef and `timescale, are used
frequently.

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 References

• VERILOG HDL”-A guide to digital design and synthesis by Samir

Palnitkar, Prentice Hall Publisher

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End of Lecture