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Digital System Design-Module03-Basic Verilog Concepts (1)

The document outlines basic Verilog concepts for digital system design, including lexical conventions, data types, system tasks, and compiler directives. It explains the structure of comments, operators, number specifications, and identifiers in Verilog HDL. Additionally, it covers special symbols like x and z for unknown and high impedance values, as well as the use of escaped identifiers.

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Muhammad Faizan
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0 views

Digital System Design-Module03-Basic Verilog Concepts (1)

The document outlines basic Verilog concepts for digital system design, including lexical conventions, data types, system tasks, and compiler directives. It explains the structure of comments, operators, number specifications, and identifiers in Verilog HDL. Additionally, it covers special symbols like x and z for unknown and high impedance values, as well as the use of escaped identifiers.

Uploaded by

Muhammad Faizan
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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MIRPUR UNIVERSITY OF SCIENCE AND TECHNOLOGY (MUST), MIRPUR

DEPARTMENT OF ELECTRICAL ENGINEERING


DIGITAL SYSTEM DESIGN
EE-474

Module No. 03: Basic Verilog Concepts

Engr. Jabbar Younis


Lecturer

Date: December 04, 2020


Learning Objectives

• Understand lexical conventions for operators, comments, whitespace, numbers,


strings, and identifiers

• Define the logic value set and data types such as nets, registers, vectors, numbers,
simulation time, arrays, parameters, memories, and strings

• Identify useful system tasks for displaying and monitoring information, and for
stopping and finishing the simulation

• Learn basic compiler directives to define macros and include files.

Digital System Design EE-474 (Fall 2020) 3


Lecture 1: Key Points

• Lexical Conventions

• Data Types

• System Tasks

• Compiler Directives

Digital System Design EE-474 (Fall 2020) 4


Lexical Conventions

• The basic lexical conventions used by Verilog HDL are similar to those
in the C programming language.
• Verilog HDL is a case-sensitive language.
• All keywords are in lowercase

Digital System Design EE-474 (Fall 2020) 5


Lexical Conventions
• Whitespace
• Comments
• Operators
• Number Specification
• Strings
• Identifiers and Keywords
• Escaped Identifiers

Digital System Design EE-474 (Fall 2020) 6


WhiteSpace
• Blank spaces (\b) , tabs (\t) and newlines (\n)
comprise the whitespace. Whitespace is ignored by
Verilog except when it separates tokens.
• Whitespace is not ignored in strings.

Digital System Design EE-474 (Fall 2020) 7


Comments

• Comments can be inserted in the code for readability and


documentation
• One Line comment: starts with “//”
• Multiple line comment: starts with “/*” and ends with “*/”
• Multiple-line comments cannot be nested
• One-line comments can be embedded in multiple-line
comments

Digital System Design EE-474 (Fall 2020) 8


Comments (Example)

• a = b && c; // This is a one-line comment


• /* This is a multiple line
comment */
• /* This is /* an illegal */ comment */
• /* This is //a legal comment */

Digital System Design EE-474 (Fall 2020) 9


Operators

• Operators are of three types:


• Unary: Unary operators precede the operand
• Binary: Binary operators appear between two
operands
• Ternary: Ternary operators have two separate
operators that separate three operands.

Digital System Design EE-474 (Fall 2020) 10


Operators (Example)

• a = ~ b; // ~ is a unary operator. b is the operand

• a = b && c; // && is a binary operator. b and c are


operands

• a = b ? c : d; // ?: is a ternary operator. b, c and d


are operands

Digital System Design EE-474 (Fall 2020) 11


Number Specification

• There are two types of number specification in


Verilog:

• Sized
• Unsized

Digital System Design EE-474 (Fall 2020) 12


Number Specification

• Sized Numbers
They are represented as <size> '<base format> <number>.
• <size> is written only in decimal and specifies the
number of bits in the number
• Legal <base formats> are decimal ('d or 'D),
hexadecimal ('h or 'H), binary ('b or 'B) and octal ('o or
'O)
• <number> is specified as consecutive digits from 0, 1,
2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f.
Digital System Design EE-474 (Fall 2020) 13
Sized Number (Example)

• 4'b1111 // This is a 4-bit binary number

• 12'habc // This is a 12-bit hexadecimal number

• 16'd255 // This is a 16-bit decimal number.

Digital System Design EE-474 (Fall 2020) 14


UnSized Number

• Numbers that are specified without a <base format>


specification are decimal numbers by default
• Numbers that are written without a <size>
specification have a default number of bits that is
simulator- and machine-specific (must be at least 32).

Digital System Design EE-474 (Fall 2020) 15


UnSized Number (Example)

• 23456 // This is a 32-bit decimal number by default

• 'hc3 // This is a 32-bit hexadecimal number

• 'o21 // This is a 32-bit octal number

Digital System Design EE-474 (Fall 2020) 16


X or Z Values

• Verilog has two symbols for unknown and high


impedance values
• An unknown value is denoted by an x
• A high impedance value is denoted by z.

Important for modeling real circuits.

Digital System Design EE-474 (Fall 2020) 17


X or Z Values (Example)

• 12'h13x // This is a 12-bit hex number; 4 least


significant bits unknown

• 6'hx // This is a 6-bit hex number

• 32'bz // This is a 32-bit high impedance number

Digital System Design EE-474 (Fall 2020) 18


Negative Numbers

• Negative numbers can be specified by putting a minus


sign before the size for a constant number
• Size constants are always positive
• It is illegal to have a minus sign between <base
format> and <number>

Digital System Design EE-474 (Fall 2020) 19


Negative Numbers (Example)

• -6'd3 // 8-bit negative number stored as 2's


complement of 3

• -6'sd3 // Used for performing signed integer math

• 4'd-2 // Illegal specification

Digital System Design EE-474 (Fall 2020) 20


Underscore Character and Question Mark

• An underscore character "_" is allowed anywhere in a


number except the first character
• Underscore characters are allowed only to improve
readability of numbers and are ignored by Verilog.
• A question mark "?" is the Verilog HDL alternative for z
in the context of numbers.
• The ? is used to enhance readability in the casex and
casez statements

Digital System Design EE-474 (Fall 2020) 21


Strings

• A string is a sequence of characters that are enclosed


by double quotes
• String must be contained on a single line, that is,
without a carriage return.
• Strings are treated as a sequence of one-byte ASCII
values.
• "Hello Verilog World" // is a string
• "a / b" // is a string

Digital System Design EE-474 (Fall 2020) 22


Identifiers and Keywords
• Keywords are special identifiers reserved to define the
language constructs
• Keywords are in lowercase.
• Identifiers are names given to objects so that they can be
referenced in the design
• Identifiers are made up of alphanumeric characters, the
underscore ( _ ), or the dollar sign ( $ ).
• Identifiers start with an alphabetic character or an
underscore
• They cannot start with a digit or a $ sign

Digital System Design EE-474 (Fall 2020) 23


Identifiers and Keywords (Example)

• reg value; // reg is a keyword; value is an identifier

• input clk; // input is a keyword, clk is an identifier

Digital System Design EE-474 (Fall 2020) 24


Escaped Identifiers
• Escaped identifiers begin with the backslash ( \ )
character and end with whitespace
• All characters between backslash and whitespace are
processed literally
• Any printable ASCII character can be included in escaped
identifiers
• Neither the backslash nor the terminating whitespace is
considered to be a part of the identifier.
• \a+b-c
• \**my_name**

Digital System Design EE-474 (Fall 2020) 25


Escaped Identifiers
• Escaped identifiers begin with the backslash ( \ )
character and end with whitespace
• All characters between backslash and whitespace are
processed literally
• Any printable ASCII character can be included in escaped
identifiers
• Neither the backslash nor the terminating whitespace is
considered to be a part of the identifier.
• \a+b-c
• \**my_name**

Digital System Design EE-474 (Fall 2020) 26


References

• VERILOG HDL”-A guide to digital design and synthesis by Samir


Palnitkar, Prentice Hall Publisher

Digital System Design EE-474 (Summer 2020) 27


End of Lecture

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