Week 1: Introduction to Architecture and Instruction Execution

1. Overview of Computer Architecture

• Definition: Computer architecture refers to the design and structure of computer

systems. It involves the layout and interaction of various components to perform
computing tasks efficiently.
• Key Components:
o CPU (Central Processing Unit): Executes instructions and performs
calculations. Often considered the brain of the computer.
o Memory: Temporary storage (RAM) for data and instructions being used by the
CPU; permanent storage (ROM, hard drives) for long-term data retention.
o Input/Output Devices: Hardware used to interact with the computer, including
keyboards, mice, monitors, and printers.
o Storage: Devices like SSDs and HDDs that store data persistently.
• Architectural Models:
o Von Neumann Architecture

Overview of Von Neumann Architecture

The Von Neumann Architecture is a foundational model for designing computer systems.
Named after mathematician and computer scientist John von Neumann, it describes a computer
architecture that uses a single memory space to store both instructions and data.

Key Components of von Neumann Architecture

1. Central Processing Unit (CPU):

o Arithmetic Logic Unit (ALU): Performs all arithmetic and logical operations.
o Control Unit (CU): Directs the operations of the CPU by interpreting instructions from
memory and executing them.
o Registers: Small, fast storage locations within the CPU used to hold temporary data
and instructions.
2. Memory:
o Primary Memory (RAM): Stores data and instructions that are currently in use. It is
volatile, meaning its contents are lost when power is off.

MERU UNIVERSITY OF SCIENCE AND TECHNOLOGY-KAJE DAVID MURITHI

 o Secondary Memory (e.g., Hard Drives, SSDs): Stores data and instructions
permanently. It is non-volatile.
3. Input/Output (I/O) Devices:
o Input Devices: Allow users to input data into the computer (e.g., keyboard, mouse).
o Output Devices: Allow the computer to output data to users (e.g., monitor, printer).
4. Bus System:
o Data Bus: Transfers data between the CPU, memory, and I/O devices.
o Address Bus: Carries the address of data to be read or written.
o Control Bus: Carries control signals to manage the operations of the CPU, memory,
and I/O devices.

Operation Cycle of von Neumann Architecture

1. Fetch: The CPU fetches an instruction from memory.

2. Decode: The Control Unit decodes the instruction to understand what action is required.
3. Execute: The CPU executes the instruction using the ALU or other components.
4. Store: The result of the execution is stored back in memory or sent to an I/O device.

Key Characteristics of von Neumann Architecture

1. Stored Program Concept:

o Instructions and data are stored in the same memory space, which allows the
computer to modify and execute instructions dynamically.
2. Sequential Execution:
o Instructions are processed sequentially, which means one instruction is executed at a
time in the order they are fetched from memory.
3. Single Memory:
o Uses a single memory system for both instructions and data, which simplifies the
design but can lead to contention for memory access (known as the "Von Neumann
Bottleneck").

Advantages of Von Neumann Architecture

1. Simplicity: The design is straightforward and easy to implement.

2. Flexibility: Programs can be modified easily because instructions and data are stored in the
same memory.

MERU UNIVERSITY OF SCIENCE AND TECHNOLOGY-KAJE DAVID MURITHI

 3. Cost-Efficiency: Using a single memory space reduces hardware costs.

Disadvantages of Von Neumann Architecture

1. Von Neumann Bottleneck: The shared bus system can lead to performance limitations due to
the contention between data and instruction access.
2. Security Risks: The ability to execute self-modifying code can pose security risks.

Evolution and Variants of von Neumann Architecture

1. Harvard Architecture:
o Uses separate memory systems for instructions and data, which can reduce the
bottleneck issues present in the Von Neumann Architecture.
2. Modern Architectures:
o Many modern processors use variations of the Von Neumann model with
enhancements, such as pipelining, caching, and multiple cores, to address
performance limitations.

Applications of Von Neumann Architecture

• General-Purpose Computers: Most traditional PCs and laptops use Von Neumann
Architecture.
• Embedded Systems: Many embedded systems also employ variations of Von Neumann
Architecture, especially those that do not require high performance.

Conclusion on Von Neumann Architecture

The Von Neumann Architecture has been a cornerstone in the development of computer
systems. Despite its limitations, its principles form the basis of many modern computing
systems and continue to influence computer design and architecture.

o Harvard Architecture:

Overview of Harvard Architecture

The Harvard Architecture is a type of computer architecture that uses separate memory systems
for storing instructions and data. This separation allows for simultaneous access to both

MERU UNIVERSITY OF SCIENCE AND TECHNOLOGY-KAJE DAVID MURITHI

instructions and data, potentially improving performance compared to the Von Neumann
Architecture, which uses a single memory space for both.

Key Components of Harvard Architecture

1. Central Processing Unit (CPU):

o Arithmetic Logic Unit (ALU): Performs arithmetic and logical operations.
o Control Unit (CU): Directs the CPU's operations and interprets instructions.
o Registers: Fast storage locations within the CPU for temporary data and instructions.
2. Memory:
o Instruction Memory: Dedicated memory for storing instructions. It is typically read-
only in many implementations.
o Data Memory: Dedicated memory for storing data. It can be read and written to.
3. Bus System:
o Instruction Bus: Connects the CPU to the instruction memory for fetching
instructions.
o Data Bus: Connects the CPU to the data memory for reading and writing data.
o Address Bus: Carries addresses to access both instruction and data memory.
4. Input/Output (I/O) Devices:
o Input Devices: Allow users to input data (e.g., keyboard, mouse).
o Output Devices: Display or output data (e.g., monitor, printer).

Operation Cycle of Harvard Architecture

1. Fetch Instruction: The CPU fetches an instruction from the instruction memory via the
instruction bus.
2. Decode Instruction: The Control Unit decodes the fetched instruction to understand the
required action.
3. Execute Instruction: The CPU executes the instruction using the ALU or other components.
4. Access Data: If the instruction involves data, the CPU accesses the data memory via the data
bus.
5. Store Results: Results from the execution are written back to data memory if necessary.

Key Characteristics of Harvard Architecture

1. Separate Memory Spaces:

MERU UNIVERSITY OF SCIENCE AND TECHNOLOGY-KAJE DAVID MURITHI

 o Instructions and data are stored in separate memories, which allows simultaneous
access to both.
2. Parallelism:
o The separation of instruction and data paths can enable simultaneous fetching of
instructions and data, leading to increased performance.
3. Reduced Bottleneck:
o By separating instruction and data access, the Harvard Architecture reduces the
contention present in the Von Neumann Architecture.
4. Complexity:
o The design is more complex due to the need for separate memory systems and buses.

Advantages of Harvard Architecture

1. Improved Performance:
o Simultaneous access to instructions and data can lead to higher performance,
particularly in systems with high instruction and data throughput requirements.
2. Reduced Bottleneck:
o Separate memory and buses for instructions and data mitigate the performance
limitations associated with the Von Neumann bottleneck.
3. Efficient Processing:
o The architecture can optimize instruction processing and data handling more
effectively.

Disadvantages of Harvard Architecture

1. Increased Hardware Complexity:

o Maintaining separate memory systems and buses adds complexity and cost to the
hardware design.
2. Less Flexibility:
o Modifying instructions may require additional mechanisms if instruction memory is
read-only, which can limit flexibility in certain applications.
3. Memory Usage:
o Separate memories might lead to inefficient use of memory space, especially if one
memory is underutilized compared to the other.

MERU UNIVERSITY OF SCIENCE AND TECHNOLOGY-KAJE DAVID MURITHI

Applications of Harvard Architecture

1. Embedded Systems:
o Harvard Architecture is commonly used in embedded systems where performance
and real-time processing are critical. Examples include microcontrollers and digital
signal processors (DSPs).
2. Digital Signal Processing:
o In DSPs, the need for fast and efficient processing of data often benefits from the
Harvard Architecture’s separation of instruction and data pathways.
3. Specialized Computing:
o Used in some high-performance and real-time computing applications where the
performance benefits outweigh the added complexity.

Evolution and Variants of Harvard Architecture

1. Modified Harvard Architecture:

o Some modern systems use a Modified Harvard Architecture, which combines aspects
of Harvard and Von Neumann architectures to offer a balance between performance
and complexity.
2. Superscalar Architectures:
o Many contemporary processors incorporate elements of Harvard Architecture, such
as multiple pipelines or separate execution units, to further enhance performance.

Conclusion on Harvard Architecture

The Harvard Architecture, with its separation of instruction and data memory, provides
significant performance advantages by allowing concurrent access to instructions and data.
While it introduces additional complexity in design, its benefits make it a preferred choice for
many high-performance and embedded systems.

2. Instruction Execution Cycle

• Fetch: The CPU retrieves the next instruction from memory. This involves reading the
instruction from the memory address specified by the program counter (PC).

MERU UNIVERSITY OF SCIENCE AND TECHNOLOGY-KAJE DAVID MURITHI

 • Decode: The instruction fetched is translated into a format that the CPU can understand
and execute. This step involves the instruction decoder which breaks down the
instruction into components.
• Execute: The CPU performs the operation specified by the decoded instruction. This
may involve arithmetic operations, data manipulation, or control operations.
• Store: The result of the execution is written to a register or memory location, depending
on the instruction.
• Example: For a simple instruction like ADD R1, R2, R3, the fetch stage retrieves this
instruction, the decode stage identifies it as an addition operation, the execute stage
performs the addition of values in R2 and R3, and the store stage places the result in R1.

3. Instruction Set Architectures (ISAs)

Overview

An Instruction Set Architecture (ISA) is a set of instructions that a CPU can execute. It defines
the interface between software and hardware, specifying the set of operations the CPU can
perform, how data is accessed and manipulated, and how instructions are encoded.

Key Components

1. Instruction Set:
o Instructions: The basic operations the CPU can perform, such as arithmetic operations
(add, subtract), data movement (load, store), and control operations (branch, jump).
o Instruction Formats: Defines how instructions are structured, including fields such as
operation code (opcode), source and destination operands, and addressing modes.
2. Registers:
o General-Purpose Registers: Used for a variety of operations and hold intermediate
data.
o Special-Purpose Registers: Include program counters (PC), stack pointers (SP), and
status registers (flags).
3. Addressing Modes:
o Immediate Addressing: The operand is directly specified in the instruction.
o Register Addressing: The operand is in a CPU register.
o Direct Addressing: The instruction specifies the memory address of the operand.

MERU UNIVERSITY OF SCIENCE AND TECHNOLOGY-KAJE DAVID MURITHI

 o Indirect Addressing: The instruction specifies a register that contains the memory
address of the operand.
o Indexed Addressing: The effective address is generated by adding a constant value to
the contents of a register.
4. Data Types:
o Defines the types of data the CPU can process, such as integers, floating-point
numbers, and characters.
5. Instruction Execution:
o Fetch: Retrieve the instruction from memory.
o Decode: Interpret the instruction to determine what actions are needed.
o Execute: Perform the operation specified by the instruction.
o Store: Write the result back to memory or a register.

Types of ISAs

1. Complex Instruction Set Computer (CISC):

o Characteristics: Rich set of instructions, with some instructions capable of performing
complex operations in a single instruction.
o Examples: x86, VAX.
o Advantages: More powerful instructions can simplify programming.
o Disadvantages: Can lead to longer execution times for some instructions and
increased hardware complexity.
2. Reduced Instruction Set Computer (RISC):
o Characteristics: Simplified set of instructions, with each instruction designed to
execute in a single clock cycle.
o Examples: ARM, MIPS, PowerPC.
o Advantages: Simpler hardware and often faster execution due to uniform instruction
execution times.
o Disadvantages: May require more instructions to perform complex tasks, which can
increase program size.
3. Very Long Instruction Word (VLIW):
o Characteristics: Uses long instruction words that specify multiple operations to be
performed simultaneously.
o Examples: Intel Itanium.

MERU UNIVERSITY OF SCIENCE AND TECHNOLOGY-KAJE DAVID MURITHI

 o Advantages: Can exploit parallelism by executing multiple operations in a single
instruction cycle.
o Disadvantages: Requires complex compilers to generate efficient VLIW code and can
have larger instruction sizes.
4. Explicitly Parallel Instruction Computing (EPIC):
o Characteristics: Similar to VLIW but with more explicit support for parallel execution
of instructions.
o Examples: Intel Itanium.
o Advantages: Enables high levels of parallelism and efficient use of multiple execution
units.
o Disadvantages: Complexity in compiler design and potential code bloat.

Instruction Set Design Considerations

1. Instruction Set Size:

o Large ISA: Offers a wide range of instructions, which can make programming easier
but may increase hardware complexity.
o Small ISA: Provides a minimal set of instructions, which simplifies hardware design
and can lead to faster execution.
2. Instruction Complexity:
o Simple Instructions: Easier to implement in hardware but may require more
instructions to perform complex tasks.
o Complex Instructions: Can perform multiple operations in one instruction but may
complicate the hardware design.
3. Instruction Execution Time:
o Affects the overall performance of the CPU. RISC architectures often aim for uniform
instruction execution times, while CISC architectures may have variable execution
times.
4. Operand Handling:
o How operands are specified and accessed affects the efficiency of instruction
execution. Different addressing modes provide flexibility in how data is accessed.
5. Compatibility:
o Backward Compatibility: Ensures that newer processors can run software written for
older versions of the ISA.

MERU UNIVERSITY OF SCIENCE AND TECHNOLOGY-KAJE DAVID MURITHI

 o Cross-Platform Compatibility: Allows software to run on different hardware
platforms that support the same ISA.

Evolution and Trends

1. Microarchitectural Innovations:
o Modern processors often employ techniques such as pipelining, superscalar
execution, and out-of-order execution to enhance performance beyond what is
defined by the ISA.
2. Application-Specific ISAs:
o Some ISAs are designed for specific applications, such as digital signal processing (DSP)
or cryptographic operations, to optimize performance for those tasks.
3. Custom and Extensible ISAs:
o Some processors allow for custom extensions to the ISA to support specific
application needs or enhance performance.

Conclusion

Instruction Set Architectures (ISAs) form the critical interface between software and hardware
in computing systems. Understanding different ISAs, their design considerations, and their
trade-offs is essential for developing efficient and effective computer systems.

4. Execution Stages: Fetch, Decode, Execute

Overview

The execution stages—Fetch, Decode, and Execute—represent the core phases of instruction
processing in a CPU. These stages are part of the instruction cycle, which is the sequence of
steps a CPU follows to execute a single instruction.

1. Fetch

Objective: Retrieve the next instruction from memory.

Process:

• Program Counter (PC): Holds the address of the next instruction to be executed.

MERU UNIVERSITY OF SCIENCE AND TECHNOLOGY-KAJE DAVID MURITHI

 • Memory Access: The instruction is fetched from the instruction memory using the address in
the PC.
• Instruction Register (IR): Once fetched, the instruction is placed in the Instruction Register for
further processing.
• Increment PC: After fetching the instruction, the PC is updated to point to the next instruction
in the sequence.

Considerations:

• Cache: Modern CPUs use instruction caches (I-Cache) to speed up the fetch process by storing
recently accessed instructions.
• Memory Hierarchy: The fetch stage can be influenced by the memory hierarchy, including
RAM and cache levels.

2. Decode

Objective: Interpret the fetched instruction to determine the required operations and operands.

Process:

• Instruction Decoding: The Control Unit decodes the instruction from the Instruction Register
to understand what operation is required.
• Operand Identification: The decoder identifies the source and destination operands based on
the instruction format and addressing mode.
• Control Signals: The Control Unit generates control signals that will direct the ALU and other
components on how to execute the instruction.

Considerations:

• Instruction Format: Different ISAs have different instruction formats, which can affect the
complexity of the decode stage.
• Complex Instructions: In CISC architectures, decoding can be more complex due to variable-
length instructions and multiple addressing modes.

3. Execute

Objective: Perform the operation specified by the decoded instruction.

MERU UNIVERSITY OF SCIENCE AND TECHNOLOGY-KAJE DAVID MURITHI

Process:

• Arithmetic and Logical Operations: If the instruction involves arithmetic or logical operations,
the ALU (Arithmetic Logic Unit) performs the computation.
• Data Transfer: For instructions that involve moving data (e.g., load or store operations), the
data is transferred between registers and memory.
• Branch Operations: If the instruction involves a branch or jump, the CPU updates the PC to
the target address if the branch condition is met.
• Status Flags: The ALU may set or clear status flags (e.g., Zero, Carry, Overflow) based on the
result of the operation, which may affect subsequent instructions.

Considerations:

• Pipelining: Modern CPUs use pipelining to overlap the Fetch, Decode, and Execute stages of
multiple instructions to increase throughput.
• Parallelism: Advanced CPUs may have multiple execution units, allowing them to perform
several operations simultaneously.

Instruction Cycle Summary

1. Fetch Stage:
o Action: Retrieve the instruction from memory.
o Components Involved: Program Counter (PC), Memory, Instruction Register (IR).
o Output: The instruction is loaded into the IR.
2. Decode Stage:
o Action: Interpret the instruction and determine necessary actions.
o Components Involved: Control Unit, Instruction Decoder.
o Output: Control signals and operand details for the next stage.
3. Execute Stage:
o Action: Perform the specified operation and update results.
o Components Involved: ALU, Data Path, Registers, Memory.
o Output: Results of the operation, updated registers or memory locations.

Additional Considerations

• Pipelining and Hazards:

MERU UNIVERSITY OF SCIENCE AND TECHNOLOGY-KAJE DAVID MURITHI

 o Pipeline Hazards: Issues like data hazards, control hazards, and structural hazards can
affect the smooth flow through these stages.
o Stalling: Techniques like inserting NOPs (no-operation instructions) or using branch
prediction to handle pipeline stalls.
• Superscalar and Out-of-Order Execution:
o Superscalar: Multiple instructions can be processed simultaneously, requiring
multiple parallel execution stages.
o Out-of-Order Execution: Instructions may be executed out of order to improve
performance and utilize available resources more efficiently.

Conclusion

The Fetch, Decode, and Execute stages form the core of instruction processing in a CPU.
Understanding these stages is crucial for grasping how instructions are processed and executed,
and how performance can be optimized through various techniques like pipelining and
superscalar execution.

MERU UNIVERSITY OF SCIENCE AND TECHNOLOGY-KAJE DAVID MURITHI