Digital Electronic Circuits

(EC2L004)

Lecture 15: Counters

Learning Objectives

• Counters
• Introduction: Counters
• Asynchronous (Ripple) Counters
• Asynchronous Counters with MOD number < 2n
• Asynchronous Down Counters
• Synchronous (Parallel) Counters
• Up/Down Synchronous Counters
• Designing Synchronous Counters
• Decoding A Counter
• Counters with Parallel Load
• Cascading Asynchronous/Synchronous Counters
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Introduction: Counters
• Counters are circuits that cycle through a specified number of
states.

• Two types of counters:

• synchronous (parallel) counters
• asynchronous (ripple) counters

• Ripple counters allow some flip-flop outputs to be used as a

source of clock for other flip-flops.

• Synchronous counters apply the same clock to all flip-flops.

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Asynchronous (Ripple) Counters
• Asynchronous counters: the flip-flops do not change states at
the same time as they do not have a common clock pulse.

• Also known as ripple counters, as the input clock pulse

“ripples” through the counter – cumulative delay is a
drawback.

• n flip-flops → a MOD (modulus) 2 counter. (Note: A MOD-x

n

counter cycles through x states.)

• Output of the last flip-flop (MSB) divides the input clock

frequency by the MOD number of the counter; hence a
counter is also a frequency divider.

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Asynchronous (Ripple) Counters
• Example: 2-bit ripple binary counter.
• Output of one flip-flop is connected to the clock input of the
next more-significant flip-flop.

HIGH

J Q0 J Q1
CLK C C
Q0
K K

FF0 FF1

CLK 1 2 3 4

Q0 Timing diagram
00 → 01 → 10 → 11 → 00 ...
Q0 0 1 0 1 0

Q1 0 0 1 1 0

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Asynchronous (Ripple) Counters
• Example: 3-bit ripple binary counter.
HIGH

J Q0 J Q1 J Q2
CLK C Q0 C Q1 C
K K K
FF0 FF1 FF2

CLK 1 2 3 4 5 6 7 8

Q0 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0

Q2 0 0 0 0 1 1 1 1 0

Recycles back to 0

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Asynchronous (Ripple) Counters
• Propagation delays in an asynchronous (ripple-clocked)
binary counter.
• If the accumulated delay is greater than the clock pulse, some
counter states may be misrepresented!

CLK 1 2 3 4

Q0

Q1

Q2
tPHL (CLK to Q0) tPHL (CLK to Q0)
tPLH (Q0 to Q1) tPHL (Q0 to Q1)
tPLH
(CLK to Q0) tPLH (Q1 to Q2)

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Asynchronous (Ripple) Counters
• Example: 4-bit ripple binary counter (negative-edge
triggered).
HIGH
Q0 Q1 Q2 Q3
J J J J
CLK C C C C
K K K K
FF0 FF1 FF2 FF3

CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Q0

Q1

Q2

Q3

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Asyn. Counters with MOD no. < 2n
• States may be skipped resulting in a truncated sequence.
• Technique: force counter to recycle before going through all of
the states in the binary sequence.
• Example: Given the following circuit, determine the counting
sequence (and hence the modulus no.)

C B A
Q J Q J Q J
All J, K CLK CLK CLK
inputs Q K Q K Q K
CLR CLR CLR
are 1
(HIGH). B
C

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Asyn. Counters with MOD no. < 2n
• Example (cont’d):
C B A
Q J Q J Q J
All J, K CLK CLK CLK
inputs Q K Q K Q K
CLR CLR CLR
are 1
(HIGH). B
C

1 2 3 4 5 6 7 8 9 10 11 12
Clock MOD-6 counter
A produced by
clearing (a MOD-8
B
binary counter)
C when count of six
NAND 1 (110) occurs.
Output 0

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Asyn. Counters with MOD no. < 2n
• Example (cont’d): Counting sequence of circuit (in CBA
order).

111 000
Temporary 001
state
Counter is a MOD-6
110 010 counter.

101 011
100

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Asyn. Counters with MOD no. < 2n
• Exercise: How to construct an asynchronous MOD-5 counter?
MOD-7 counter? MOD-12 counter?

• Question: The following is a MOD-? counter?

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Asyn. Counters with MOD no. < 2n
• Decade counters (or BCD counters) are counters with 10
states (modulus-10) in their sequence. They are commonly
used in daily life (e.g.: utility meters, odometers, etc.).
• Design an asynchronous decade counter.

(A.C)'

HIGH
D C B A
J Q J Q J Q J Q

CLK C C C C
K K K K
CLR CLR CLR CLR

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Asyn. Counters with MOD no. < 2n
• Asynchronous decade/BCD counter (cont’d).

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Asynchronous Down Counters
• So far we are dealing with up counters. Down counters, on
the other hand, count downward from a maximum value to
zero, and repeat.
• Example: A 3-bit binary (MOD-8) down counter.

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Asynchronous Down Counters
• Example: A 3-bit binary (MOD-8) down counter.

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Synchronous Counters
• Synchronous (parallel) counters: the flip-flops are clocked at
the same time by a common clock pulse.

• We can design these counters using the sequential logic

design process.

• Example: 2-bit synchronous binary counter (using T flip-flops,

or JK flip-flops with identical J,K inputs).

Present Next Flip-flop

state state inputs
00 01 A1 A0 A1+ A0+ TA1 TA0
0 0 0 1 0 1
0 1 1 0 1 1
11 10
1 0 1 1 0 1
1 1 0 0 1 1

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Synchronous Counters
• Example: 2-bit synchronous binary counter (using T flip-flops,
or JK flip-flops with identical J,K inputs).

Present Next Flip-flop

state state inputs
TA1 = A0
A1 A0 A1+ A0+ TA1 TA0
TA0 = 1
0 0 0 1 0 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 0 1 1

A0 J A1
J Q Q
C C
Q' K Q'
K

CLK

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Synchronous Counters
• Example: 3-bit synchronous binary counter (using T flip-flops,
or JK flip-flops with identical J, K inputs).
Present Next Flip-flop
state state inputs
A2 A1 A 0 A2+ A1+ A0+ TA2 TA1 TA0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
A1 A1 A1

1 1 1 1 1 1 1
A2 1 A2 1 1 A2 1 1 1 1

A0 A0 A0
TA2 = A1.A0 TA1 = A0 TA0 = 1
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Synchronous Counters
▪ Example: 3-bit synchronous binary counter (cont’d).
TA2 = A1.A0 TA1 = A0 TA0 = 1

A2 A1 A0

Q Q Q
J K J K J K
CP
1

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Synchronous Counters
• Note that in a binary counter, the nth bit (shown underlined) is
always complemented whenever
011…11 → 100…00
or 111…11 → 000…00

• Hence, Xn is complemented whenever

Xn-1Xn-2 ... X1X0 = 11…11.

• As a result, if T flip-flops are used, then

TXn = Xn-1 . Xn-2 . ... . X1 . X0

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Synchronous Counters
• Example: 4-bit synchronous binary counter.
TA3 = A2 . A1 . A0
TA2 = A1 . A0
TA1 = A0
TA0 = 1

1 A1.A0 A2.A1.A0

A0 J A1 J A2 J A3
J Q Q Q Q
C C C C
Q' K Q' K Q' K Q'
K

CLK

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Synchronous Counters
• Example: Synchronous decade/BCD counter.

Clock pulse Q3 Q2 Q1 Q0
Initially 0 0 0 0 T0 = 1
1 0 0 0 1
2 0 0 1 0
T1 = Q3'.Q0
3 0 0 1 1 T2 = Q1.Q0
4 0 1 0 0 T3 = Q2.Q1.Q0 + Q3.Q0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 (recycle) 0 0 0 0

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Synchronous Counters
• Example: Synchronous decade/BCD counter (cont’d).

T0 = 1
T1 = Q3'.Q0
T2 = Q1.Q0
T3 = Q2.Q1.Q0 + Q3.Q0

Q0

1 T T Q1 T Q2 T Q3
Q Q Q Q
C C C C
Q' Q' Q' Q'

CLK

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Up/Down Synchronous Counters
• Up/down synchronous counter: a bidirectional counter that
can count either up or down.

• An input (control) line Up/Down (or simply Up) specifies the

direction of counting.
Up/Down = 1 → Count upward

Up/Down = 0 → Count downward

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Up/Down Synchronous Counters
• Example: A 3-bit up/down synchronous binary counter.
Clock pulse Up Q2 Q1 Q0 Down
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

TQ0 = 1 Up counter Down counter

TQ1 = (Q0.Up) + (Q0'.Up' ) TQ0 = 1 TQ0 = 1
TQ1 = Q0 TQ1 = Q0’
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )
TQ2 = Q0.Q1 TQ2 = Q0’.Q1’

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Decoding A Counter
• Decoding a counter involves determining which state in the
sequence the counter is in.

Decoding of state 6 (110).

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Decoding A Counter

A 3-bit counter with active-HIGH decoding

of count 2 and count 7
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Counters with Parallel Load
• Counters could be augmented with parallel load capability for
the following purposes:

• To start at a different state

• To count a different sequence

• As more sophisticated register with increment/decrement

functionality.

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Counters with Parallel Load

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Counters with Parallel Load

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Cascading Asynchronous Counters
• Larger asynchronous (ripple) counter can be constructed by
cascading smaller ripple counters.
• Connect last-stage output of one counter to the clock input of
next counter to achieve higher-modulus operation.
• Example: A modulus-32 ripple counter constructed from a
modulus-4 counter and a modulus-8 counter.

Q0 Q1 Q2 Q3 Q4

J Q J Q J Q J Q J Q
CLK C C C C C
Q' K Q' Q' K Q' K Q'
K K

Modulus-4 counter Modulus-8 counter

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Cascading Asynchronous Counters
• Example: A 6-bit binary counter (counts from 0 to 63)
constructed from two 3-bit counters.

A0 A1 A2 A3 A4 A5

Count 3-bit 3-bit

binary counter binary counter
pulse

A5 A4 A3 A2 A1 A0
0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 : : :
0 0 0 1 1 1
0 0 1 0 0 0
0 0 1 0 0 1
: : : : : :

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Cascading Synchronous Counters
• If counter is a not a binary counter, requires additional output.
• Example: A modulus-100 counter using two-decade counters.

• CTEN---Counter Enable, TC= Terminal Count

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References
• Chapter 9, Digital Fundamentals by Thomas L. Floyd

• Chapter 6, Digital Design by M. Morris Mano

• Disclaimer: I don’t own all the slides, these slides are copied
and adopted from various public resources available on the
internet.

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Thank you!!!