Spring 2025 CA Lab-6

Namal University, Mianwali

Department of Computer Science
CSS-242L – Computer Architecture (Lab)

Lab -6

Memory Unit Architecture and Design in Verilog

Student’s Name Gulfam Afzal

Roll No. NUM-BSCS-2023-31
Date Performed 4/28/2025

Marks Obtained

Course Instructor: Lab Instructor:

Dr. Shafiq Ur Rehman Khan Engr. Majid Ali

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Document History
Rev. Date Comment Author
1.0 24/02/2025 Initial draft Engr. Majid Ali

Instructions

 Read the manual carefully before start of any tasks / experiments.

 Carefully handle all equipment available in the lab.
 Carefully write your particulars at first page on the manual.
 In case of simulation at PC, try to avoid opening of unnecessary tabs.
 Submit PDF report of each lab at Q-OBE, attach all findings in report properly.
 Write precise conclusion of every lab.
 Submission time is end of respective lab session for each manual, late submission of
manual is not acceptable.
 Fill manual individually even in case of group work.
 Plagiarism will be dealt with strict consequences.

Objectives

 To design and implement instruction and data memory units in Verilog and
verify their functionality through simulation.
Learning Outcomes

This lab satisfies the following learning outcomes of the course:

 CLO1: Follows fundamental computer architecture concepts through practical
laboratory exercises, following theoretical knowledge to design, measure, and
evaluate the performance of simulated architectural components.
 CLO3: Present concise and comprehensive technical reports

Equipment & Components

 Computer with Ubuntu OS installed.
 Icarus Verilog for simulation.
 GTKWave for waveform analysis.

Introduction

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In modern computer architecture, memory units play a critical role in storing and managing
both program instructions and data required for processing. This lab focuses on designing two
fundamental memory units in Verilog: The Instruction Memory and Data Memory.
Instruction Memory stores all the instructions according to the instruction format. Each
instruction is stored in 32-bit format. The instruction address is also 32-bit wide. RISC-V
deals with everything in byte addresses. The difference between two successive instruction
addresses in 4. Therefore, 4 is added along with pc to fetch next instruction. The layout of
instruction memory is displayed in Fig. 1.

Fig 1: Instruction Memory

The Data Memory on the other hand, is a read-write memory that stores variable data
manipulated during program execution. It allows for both storage and retrieval operations,
essential for tasks such as storing intermediate results and processing data

Fig2: Data Memory

RISC-V operands from memory
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Word-Addressable Memory:

Each 32-bit data word has a unique address

lw t1, 5(s0)
lw <rd>, <offset>(<base register>)

Address calculation:
 add offset (5) to the base address (s0)
 address = (s0 + 5)
Destination register (rd):
 t1 holds the value at address (s0 + 5)

Format to store word:

sw <src1>, <offset>(<base register>)

RISC-V uses byte-addressable memory (i.e. byte has a unique address), so each 32-bit word
uses 4-byte addresses.
32-bit operands in memory occupies 4 bytes. Some processor uses one unique address for
each 32-bit words. MIPS processor is one such example. Everything instruction or data word
has a unique address – it is “word addressable” processor. RISC-V uses byte-addressable to
access memory, where EVERY BYTE has a unique address.

Byte-addressable Memory:
Each data byte has a unique address Load/store words or single bytes: load byte (lb) and store
byte (sb) 32-bit word = 4 bytes, so word address increments by 4.
The address of a memory word must now be multiplied by 4.

For example,
 the address of memory word 2 is 2 × 4 = 8
 the address of memory word 10 is 10 × 4 = 40 (0x28)
 RISC-V is byte-addressed, not word-addressed

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Therefore, in RISC-V, every 32-bit occupies four unique addresses. Since all RISC-V
instructions are 32-bit, addresses of the instruction memory are all aligned to an increment of
4.

Lab Task 1:

Design Instruction Memory Unit for RISC-V Datapath with 32-bit address.

Verilog Code: Testbench:

module dataMem_TB;
module dataMem( clk , rst , mwrite , mread ,
address , wdata , memout ); reg clk , rst , mwrite , mread;
input clk , rst , mwrite , mread; reg [31:0] address , wdata;
input [31:0] address , wdata; wire [31:0] memout;
output [31:0] memout;
dataMem
reg [31:0] Dmem[63:0]; uut( .clk(clk) , .rst(rst) , .mwrite(mwrite
) , .mread(mread) , .address(address) ,
integer a; .wdata(wdata) , .memout(memout) );

always @( posedge clk) always # 10 clk = ~clk;

begin
if(rst) initial begin
begin clk = 1'b0;
for(a=0;a<=63;a=a+1)
begin rst = 1'b1;
Dmem[a]=32'h0000; mwrite = 0;

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end mread = 0;
end #20;
else if (mwrite)
begin rst = 1'b0;
Dmem[address]=wdata; #20;
end
end address = 32'd1;
wdata = 32'h000C;
assign memout= mread ? Dmem[address] : mwrite = 1'b1;
32'h0000; mread = 1'b0;
#20;
endmodule
mwrite = 1'b0;
#20;

address = 32'd1;
mread = 1'b1;
#20;

mread = 1'b0;
#20;

$stop;
end

endmodule

Waveform:

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Lab Task 2:

Design of a Single-Port Data Memory Unit for a RISC-V Datapath with 32-Bit Addressing,
Supporting Read and Write Functionality.

Verilog Code: Testbench:

// use cambria font and size must be 12

Waveform:

Conclusion:

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Marks
Domain Criteria Excellent (10) Good (8-9) Satisfactory (6-7) Improvement (4-5)
Obtained

RISC-V
Designed an efficient Implemented the Designed a basic Incomplete or
Psychomotor Datapath in
RISC-V datapath with RISC-V datapath datapath with some incorrect design with
(P3) HDL
correct functionality with minor errors issues major errors
(CLO-1)

Report Presented Provided basic Unable to answer

Writing Presented outstanding comprehensive answers in reports questions and had
(CLO-3) and detailed reports. reports with some with limited significant knowledge
Affective (A2)

minor gaps. knowledge gaps. gaps.

Answered questions Answered

Answered questions
confidently and questions Unable to answer
Lab Viva with basic
showed exceptional comprehensively questions and was not
(CLO-3) understanding and
knowledge and and exhibited confident.
limited knowledge.
comprehension. strong knowledge

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