18CSC203J – COMPUTER ORGANIZATION

AND ARCHITECTURE

Course Outcome

CLR-1:Utilize the functional units of a computer

CLO-1 :Identify the computer hardware and how

software interacts with computer hardware

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 Topics Covered
• Functional Units of a computer
• Operational Concepts
• Bus Structures
• Memory Location and Addresses
• Memory Operations
• Instructions and Instruction Sequencing
• Addressing modes
• Problem Solving
• Introduction to Microprocessor
• Introduction to Assembly Language
• Writing of Assembly Language Programming
• ARM Processor: The Thumb instruction set
• Processor and CPU CORES
• Instruction Encoding Format
• Memory load and store instruction in ARM
• Basics of IO Operations
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 What is a computer?
• a computer is a sophisticated electronic calculating
machine that:
– Accepts input information,
– Processes the information according to a list of
internally stored instructions and
– Produces the resulting output information.
• Functions performed by a computer are:
– Accepting information to be processed as input.
– Storing a list of instructions to process the information.
– Processing the information according to the list of
instructions.
– Providing the results of the processing as output.
• What are the functional units of a computer? 3
Functional Units of a
Computer

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 FUNCTIONAL UNITS OF COMPUTER
• Input Unit
• Output Unit
• Central processing Unit (ALU and Control Units)
• Memory
• Bus Structure

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6
 Functions
• ALL computer functions are:

– Data PROCESSING
– Data STORAGE Data = Information
– Data MOVEMENT
– CONTROL Coordinates How
Information is Used

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 Functions of a computer
The operations performed by a computer using the
functional units can be summarized as follows:
• It accepts information (program and data) through
input unit and transfers it to the memory.
• Information stored in the memory is fetched, under
program control, into an arithmetic and logic unit for
processing.
• Processed information leaves the computer through
an output unit.
• The control unit controls all activities taking place
inside a computer.
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9
 Information in a computer -- Instructions
• Instructions specify commands to:
– Transfer information within a computer (e.g., from memory to
ALU)
– Transfer information between the computer and I/O devices
(e.g., from keyboard to computer, or computer to printer)
– Perform arithmetic and logic operations (e.g., Add two
numbers, Perform a logical AND).
• A sequence of instructions to perform a task is called a program,
which is stored in the memory.
• Processor fetches instructions that make up a program from the
memory and performs the operations stated in those instructions.

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 Information in a computer -- Data
• Data are the “operands” upon which instructions
operate.
• Data could be:
– Numbers,
– Encoded characters.
• Data, in a broad sense means any digital information.
• Computers use data that is encoded as a string of
binary digits called bits.

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 Input unit
Binary information must be presented to a computer in a specific format. This
task is performed by the input unit:
- Interfaces with input devices.
- Accepts information from the input devices.
- Presents this binary information in a format expected by the computer.
- Transfers this information to the memory or processor.

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 Memory unit
• Memory unit stores instructions and data.
– Recall, data is represented as a series of bits.

– To store data, memory unit thus stores bits.

• Processor reads instructions and reads/writes data from/to the

memory during the execution of a program.
– a group of bits is fetched at a time.
– Group of bits stored or retrieved at a time is termed as “word”
– Number of bits in a word is termed as the “word length” of a computer.
• In order to read/write to and from memory, a processor should
know where to look:
– “Address” is associated with each word location.

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 Memory unit (contd..)
• Processor reads/writes to/from memory based on
the memory address:
– Access any word location in a short and fixed amount of time based on the address.
– Random Access Memory (RAM) provides fixed access time independent of the
location of the word.
– Access time is known as “Memory Access Time”.

• Memory and processor have to “communicate”

with each other in order to read/write information.
– In order to reduce “communication time”, a small amount of RAM (known as Cache)
is tightly coupled with the processor.
• Modern computers have three to four levels of RAM units with different speeds and sizes:
– Fastest, smallest known as Cache
– Slowest, largest known as Main memory.

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 Memory unit (contd..)
• Primary storage of the computer consists of RAM units.
– Fastest, smallest unit is Cache.
– Slowest, largest unit is Main Memory.

• Primary storage is insufficient to store large amounts of

data and programs.
– Primary storage can be added, but it is expensive.

• Store large amounts of data on secondary storage

devices:
– Magnetic disks and tapes,
– Optical disks (CD-ROMS).
– Access to the data stored in secondary storage in slower, but take advantage of the fact that some
information may be accessed infrequently.

• Cost of a memory unit depends on its access time, lesser

access time implies higher cost.
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 Arithmetic and logic unit (ALU)
• Operations are executed in the Arithmetic and
Logic Unit (ALU).
– Arithmetic operations such as addition, subtraction.
– Logic operations such as comparison of numbers .

• In order to execute an instruction, operands need to

be brought into the ALU from the memory.
– Operands are stored in general purpose registers available in the CPU.
– Access times of general purpose registers are faster than the cache.

• Results of the operations are stored back in the

memory or retained in the processor for immediate
use.
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 Output unit
•Computers represent information in a specific binary form. Output units:
- Interface with output devices.
- Accept processed results provided by the computer in specific binary form.
- Convert the information in binary form to a form understood by an
output device.

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 Control unit
• Operation of a computer can be summarized as:
– Accepts information from the input units (Input unit).
– Stores the information (Memory).
– Processes the information (ALU).
– Provides processed results through the output units (Output
unit).
• Operations of Input unit, Memory, ALU and Output unit are
coordinated by Control unit.
• Instructions control “what” operations take place (e.g. data
transfer, processing).
• Control unit generates timing signals which determines “when” a
particular operation takes place.
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 CPU (Central processing Unit)
•The “brain” of the machine
•Responsible for carrying out computational task
•Contains ALU, CU, Registers
•ALU Performs Arithmetic and logical operations
•CU Provides control signals in accordance with some
timings which in turn controls the execution process
•Register Stores data and result and speeds up the
operation

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CONTROL UNIT

•Control unit works with a

reference signal called
T1 Processor clock
T2 •Processor divides the
operations into basic steps

•Each basic step is

R1 R2 executed in one clock
cycle

R2

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Example

Add R2, R1

T1 Enable R1

T2 Enable R2

T3 Enable ALU for addition operation

T4

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Operational Concepts

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 Basic Operational Concepts

Basic Function of Computer

• To Execute a given task as per the appropriate program

• Program consists of list of instructions stored in memory

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 A Typical Instruction

Add R0, LOCA

• Add the operand at memory location LOCA to the
operand in a register R0 in the processor.
• Place the sum into register R0.
• The original contents of LOCA are preserved.
• The original contents of R0 is overwritten.
• Instruction is fetched from the memory into the processor
– the operand at LOCA is fetched and added to the
contents of R0 – the resulting sum is stored in register R0.

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Load R2, LOC
This instruction reads the contents of a memory location by
the label LOC and loads them into processor register R2.
The original contents of location LOC are preserved,
whereas those of register R2 are overwritten.
Execution of this instruction requires several steps.
First, the instruction is fetched from the memory into the
processor.
Next, the operation to be performed is determined by the
control unit.
The operand at LOC is then fetched from the memory into
the processor.
Finally, the operand is stored in register R2
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Add R4, R2, R3
adds the contents of registers R2 and R3, then places their sum
into register R4.
The operands in R2 and R3 are not altered, but the previous value
in R4 is overwritten by the sum.
Store R4, LOC
This instruction copies the operand in register R4 to memory
location LOC.
The original contents of location LOC are overwritten, but those
of R4 are preserved.
For Load and Store instructions, transfers between the memory
and the processor are initiated by sending the address of the
desired memory location to the memory unit and asserting the
appropriate control signals.
The data are then transferred to or from the memory.
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27
Registers
Registers are fast stand-alone storage locations that hold data
temporarily. Multiple registers are needed to facilitate the
operation of the CPU. Some of these registers are
Two registers - MAR (Memory Address Register) and MDR
(Memory Data Register) : To handle the data transfer
between main memory and processor. MAR-Holds
addresses, MDR-Holds data
Instruction register (IR) : Hold the Instructions that is
currently being executed
Program counter (PC) : Points to the next instructions that is
to be fetched from memory
General-purpose Registers: are used for holding data, 28
29
 Instruction Fetch – Steps Involved
• Program gets into the memory through an input device.
• Execution of a program starts by setting the PC to point
to the first instruction of the program.
• The contents of PC are transferred to the MAR and a
Read control signal is sent to the memory.
• The addressed word (here it is the first instruction of the
program) is read out of memory and loaded into the
MDR.
• The contents of MDR are transferred to the IR for
instruction decoding 30
 Instruction Execution – Steps Involved
• The operation field of the instruction in IR is examined to
determine the type of operation to be performed by the
ALU.
• The specified operation is performed by obtaining the
operand(s) from the memory locations or from GP
registers.
1) Fetching the operands from the memory requires
sending the memory location address to the MAR
and initiating a Read cycle.
2) The operand is read from the memory into the
MDR and then from MDR to the ALU.
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Instruction Execution – Steps Involved (Contd..)
3) The ALU performs the desired operation on one or
more operands 13 fetched in this manner and sends
the result either to memory location or to a GP register.
4) The result is sent to MDR and the address of the
location where the result is to be stored is sent to
MAR and Write cycle is initiated.
Thus, the execute cycle ends for the current instruction and
the PC is incremented to point to the next instruction for a
new fetch cycle.

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 Interrupt

• An interrupt is a request from I/O device for

service by processor
• Processor provides requested service by
executing interrupt service routine (ISR)
• Contents of PC, general registers, and some
control information are stored in memory .
• When ISR completed, processor restored, so
that interrupted program may continue

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Bus Structures

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Connecting CPU and memory

• The CPU and memory are normally connected by three

groups of connections, each called a bus
• Group of wires which carries information from CPU to
peripherals or vice – versa.
• data bus, address bus and control bus

Connecting CPU and memory using three buses

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BUS STRUCTURE
•Single bus structure: Common bus used to communicate between
peripherals and microprocessor

INPUT MEMORY PROCESSOR OUTPUT

Single Bus Structure

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TWO BUS STRUCTURE:
• One bus can be used to fetch instruction other can be used to
fetch data, required for execution.
•The bus is said to perform two distinct functions
•The main advantage of this structure is good operating speed
but on account of more cost.

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MULTI BUS STRUCTURE
To improve performance multi bus structure can be used.

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 CONTROL BUS A2 A1 A0 Selected
location
0 0 0 0th
Location
0 0 1 1st Location
0 1 0
W/R
CS RD
A0 PROCESSOR
0 1 1
A1
A2 1 0 0

ADDRESS BUS 1 0 1

D7 D0 1 1 0
D0 D7

1 1 1

DATA BUS

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•23 = 8 i.e. 3 address line is required to select 8 location

•In general 2x = n where x number of address lines (address bit) and

n is number of location

•Address bus : unidirectional : group of wires which carries

address information bits from processor to peripherals (16,20,24 or
more parallel signal lines)
•Data bus: bidirectional : group of wires which carries data
information bit from processor to peripherals and vice – versa
•Control bus: bidirectional: group of wires which carries control
signals from processor to peripherals and vice – versa

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Figure below shows address, data and control bus and their connection with
peripheral and microprocessor

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Memory Locations and Addresses

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 Memory Location and Addresses
• Memory consists of many nbits
first word
millions of storage cells, second word
each of which can store 1
bit. •
• Data is usually accessed in •
•
n-bit groups. n is called i th word
word length.
• The memory of a computer •
can be schematically •
•
represented as a collection
last word
of words as shown in
Figure 1. Main Memory words.
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 Memory Locations And Addresses
•Main memory is the second major subsystem in a computer. It
consists of a collection of storage locations, each with a unique
identifier, called an address.

•Data is transferred to and from memory in groups of bits called

words. A word can be a group of 8 bits, 16 bits, 32 bits or 64 bits
(and growing).

•If the word is 8 bits, it is referred to as a byte. The term “byte” is so

common in computer science that sometimes a 16-bit word is
referred to as a 2-byte word, or a 32-bit word is referred to as a 4-
byte word.
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Main memory

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 Address space

•To access a word in memory requires an identifier. Although

programmers use a name to identify a word (or a collection of
words), at the hardware level each word is identified by an address.

•The total number of uniquely identifiable locations in memory is

called the address space.

•For example, a memory with 64 kilobytes (16 address line

required) and a word size of 1 byte has an address space that ranges
from 0 to 65,535.

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Memory addresses are defined using unsigned
binary integers.
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 Memory
• Holds both instructions and data
• With k address bits and n bits per location address
k Number of locations 0 n-1 ... 1 0
10 210 = 1024 = 1K 1
216 = 65,536 = 64K 2
16 .
20
20 2 = 1,048,576 = 1M .
.
24 224 = 16,777,216 = 16M
k
2 -1

• n is typically 8 (byte), 16 (word), 32 (long word), ….

 Example 1

A computer has 32 MB (megabytes) of memory. How many bits are

needed to address any single byte in memory?
Solution
The memory address space is 32 MB, or 225 (25 × 220). This means that
we need log2 225, or 25 bits, to address each byte.

Example 2
A computer has 128 MB of memory. Each word in this computer is
eight bytes. How many bits are needed to address any single word in
memory?
Solution
The memory address space is 128 MB, which means 227. However,
each word is eight (23) bytes, which means that we have 224 words.
This means that we need log2 224, or 24 bits, to address each word. 49
 Memory Operations
• Today, general-purpose computers use a set of instructions called a
program to process data.
• A computer executes the program to create output data from input
data
• Both program instructions and data operands are stored in memory
• Two basic operations requires in memory access
• Load operation (Read or Fetch)-Contents of specified
memory location are read by processor
• Store operation (Write)- Data from the processor is stored in
specified memory location

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 Assignment of Byte Address
• Big-endian and little-endian are terms that describe
the order in which a sequence of bytes are stored in
computer memory.
• Big-endian is an order in which the "bigend" (most
significant value in the sequence) is stored first (at the
lowest storage address).
• Little-endian is an order in which the “Little end"
(least significant value in the sequence) is stored first
(at the lowest storage address).
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Big endian Assignment
Little – Endian assignment:
In this scheme byte 0 appears as the right most byte of word 0.
Low order bytes represents least significant bytes or right most bytes.
• In case of 16 bit data, aligned words begin at byte
addresses of 0,2,4,………………………….
• In case of 32 bit data, aligned words begin at byte
address of 0,4,8,………………………….
• In case of 64 bit data, aligned words begin at byte
addresses of 0,8,16,………………………..
• In some cases words can start at an arbitrary byte
address also then, we say that word locations are
unaligned
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INSTRUCTION AND
INSTRUCTION
SEQUENCING

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 Introduction
• Instruction: is command to the microprocessor to perform a given
task on specified data.
• Instruction Set: The entire group of these instructions are called
instruction set.
• instruction sequencing : The order in which the instructions in a
program are carried out.
4 TYPES OF OPERATION:-
A computer must have instructions capable of performing 4 types of
operation
• Data transfer between memory and processor register
• Arithmetic and logic operation
• Program sequencing and control
• I/O transfer

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 Register transfer notation (RTN)
Transfer between processor registers & memory, between processor
register & I/O devices
Memory locations, registers and I/O register names are identified by
a symbolic name in uppercase alphabets
• LOC,PLACE,MEM are the address of memory location
• R1 , R2,… are processor registers
• DATA_IN, DATA_OUT are I/O registers
• Contents of location is indicated by using square brackets [ ]
• RHS of RTN always denotes a values, and is called Source
• LHS of RTN always denotes a symbolic name where value is to
be stored and is called destination
• Source contents are not modified
• Destination contents are overwritten
 Data transfer Instructions
They are also called copy instructions.
Some instructions in 8086:
MOV -Copy from the source to the destination
LDA - Load the accumulator
STA - Store the accumulator
PUSH - Push the register pair onto the stack
POP - Pop off stack to the register pair

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 Data Manipulation Instructions

• To perform the operations by the ALU

• Three categories:
– Arithmetic Instructions
– Logical and bit manipulation instructions
– Shift instructions

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 Arithmetic Instructions
Used to perform arithmetic operations
Some instruction in 8086
INC ➔ Increment the data by 1
DEC ➔ Decreases data by 1
ADD ➔ perform sum of data
ADC ➔ Add with carry bit.
MUL ➔ perform multiplication

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 Logical and bit manipulation instructions
Used to perform logical operations
Some instructions are:
AND ➔ bitwise AND operation
OR ➔ bitwise AND operation
NOT ➔ invert each bit of a byte or word
XOR ➔ Exclusive-OR operation over each bit

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 Shift instructions
used for shifting or rotating the contents of the register
Some instructions are:
SHL: shift bits towards the left and put zero(S) in LSBs
SHR : shift bits towards the right and put zero(S) in MSBs
ROL: rotate bits towards the left, i.e. MSB to LSB
ROR: rotate bits towards the right, i.e. LSB to MSB
RCL: rotate bits towards the left, i.e. MSB to CF and CF
to LSB.
RCR: rotate bits towards the right, i.e. LSB to CF and CF
to MSB
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SHL and SHR

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64
65
 Instruction Formats
(Types of instruction based on the address field)
• A instruction in computer comprises of groups of
fields.
• These field contains different information
• The most common fields are:
Operation field : specifies the operation to be
performed like addition.
Address field : contain the location of
operand
Mode field : specifies how to find the operand
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• An instruction is of various length depending upon
the number of addresses it contain.
• On the basis of number of address, instruction are
classified as:
– Zero Address Instructions
– One Address Instructions
– Two Address Instructions
– Three Address Instructions

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 Three Address Instruction

•Syntax: Operation destination, source 1, source 2,

•Eg: ADD D,E,F
where D,E,F are memory location
•Advantage: Single instruction can perform the complete
operation
•Disadvantage : Instruction code will be too large to fit in
one word location in memory

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 Three Address Instruction
This has three address field to specify a register or a memory location.
Program created are much short in size
creation of program much easier
does not mean that program will run much faster
• Suppose we would like to use a single machine instruction to perform the
following addition operation:
• S  [P] + [Q]
• We will have to use a three – address instruction to carry out addition
and to store the sum in a third variable S.

➢ Then three address instruction to perform addition is:

Add S,P, Q
Example: Evaluate (A+B)  (C+D)
Using Three address Instruction
1. ADD R1,A,B ;R1=M[A]+M[B]
2. ADD R2,C,D ;R2=M[C]+M[D]
3. MUL X,R1,R2 ;M[X]=R1*R2
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 Two Address Instruction
•Syntax : Operation destination, source
•Eg: MOVE E,F MOVE D,F

ADD D,F OR ADD E,F

➢To perform S  [P] + [Q]
➢ Use two – address instructions sequence: MOVE S, Q

ADD S,P
Perform ADD A,B,C using 2 instructions

MOVE A,C
ADD A,B
 Two Address Instruction
This is common in commercial computers.
Operation Source, Destination
Here two address can be specified in the instruction.
Example: Evaluate (A+B)  (C+D)
Using Two address Instruction:
1. MOV R1,A ; R1=M[A]
2. ADD R1,B ;R1=R1+M[B]
3. MOV R2,C ;R2=M[C]
4. ADD R2,D ;R2=R2+M[D]
5. MUL R1,R2 ; R1=R1*R2
6. MOV X,R1 ; M[X]=R1
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 One address Instruction
• Syntax- Operation source/destination
• In this type either a source or destination operand is
mentioned in the instruction
• Other operand is implied to be a processor register
called Accumulator
• Eg: ADD B (general)
• Load D; ACC [memlocation _D]
• ADD E; ACC (ACC) +(E)
• STORE F; memlocation_ F (ACC )
 One address Instruction
• This use a implied ACCUMULATOR register for data manipulation.
Operation Destination
• One operand is in accumulator and other is in register or memory location.
Example: Evaluate (A+B)  (C+D)
• Using One-Address Instruction
1. LOAD A ; AC ← M[A]
2. ADD B ; AC ← AC + M[B]
3. STORE T ; M[T] ← AC
4. LOAD C ; AC ← M[C]
5. ADD D ; AC ← AC + M[D]
6. MUL T ; AC ← AC  M[T]
7. STORE X ; M[X] ← AC

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 Zero Address Instructions
Used in stack based computers which do not use address
field in instruction
• Location of all operands are defined implicitly
• Operands are stored in a structure called pushdown
stack

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 Example: Evaluate (A+B)  (C+D)
• Using Zero-Address instruction
1. PUSH A ; TOS ← A
2. PUSH B ; TOS ← B
3. ADD ; TOS ← (A + B)
4. PUSH C ; TOS ← C
5. PUSH D ; TOS ← D
6. ADD ; TOS ← (C + D)
7. MUL ; TOS ← (C+D)(A+B)
8. POP X ; M[X] ← TOS

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 Instruction Cycle
• the basic operational process of a computer.
• also known as fetch-decode-execute cycle
• This process is repeated continuously by CPU from
boot up to shut down of computer.
steps that occur during an instruction cycle:
1. Fetch the Instruction
2. Decode the Instruction
3. Read the Effective Address
4. Execute the Instruction
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1. Fetch the Instruction
The instruction is fetched from memory address that is stored
in PC(Program Counter) and stored in the (instruction register) IR.
At the end of the fetch operation, PC is incremented by 1 and
it then points to the next instruction to be executed.
2. Decode the Instruction
The instruction in the IR is decoded(Interpreted).
3. Read the Effective Address
Effective address of an operand is computed, the effective
address is read from the memory.
Operands are directly read in case of immediate operand instruction.

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4. Execute the Instruction
The Control Unit passes the information in the form of
control signals to the functional unit of CPU.
The result generated is stored in main memory or sent to
an output device.
The cycle is then repeated by fetching the next
instruction.
Thus in this way the instruction cycle is repeated
continuously.

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 start

Load address to PC

Load content of PC to IR

Update PC to next address

Execute Instruction

Interrupts Service Interrupt

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 Instruction execution and straight line sequencing
• Instruction execution needs the following steps, which are
• PC (program counter) register of the processor gives the address of the
instruction which needs to be fetched from the memory.
• If the instruction is fetched then, the instruction opcode is decoded. On
decoding, the processor identifies the number of operands. If there is any
operand to be fetched from the memory, then that operand address is
calculated.
• Operands are fetched from the memory. If there is more than one operand,
then the operand fetching process may be repeated (i.e. address calculation
and fetching operands).
• After this, the data operation is performed on the operands, and a result is
generated.
• If the result has to be stored in a register, the instructions end here.

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 Straight line sequencing
• If the destination is memory, then first the destination address
has to be calculated. Then the result is then stored in the
memory. If there are multiple results which need to be stored
inside the memory, then this process may repeat (i.e.
destination address calculation and store result).
• Now the current instructions have been executed. Side by side,
the PC is incremented to calculate the address of the next
instruction.
• The above instruction cycle then repeats for further
instructions.
• Straight line sequencing means the instruction of a program is
executed in a sequential manner(i.e. every time PC is
incremented by a fixed offset).
• And no branch address is loaded on the PC.

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Example 1:
•First instruction of a program is stored at address i.
•PC gives address i and instruction stored at that address i is fetched from the memory
and then decoded and then the operand A is fetched from the memory and stored in a
temporary register and then the instruction is executed(i.e. content of address A is
copied into processor register R0).
•the PC gets incremented by 4(i.e. it contains the address of the next instruction)
because the instruction and memory segment is of 4 bytes.
•So the instruction at address i is executed.
•So every time, the PC is incremented by 4. Therefore, the program is executing in a
sequential manner. And this process is called straight line sequencing.

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 Address Contents
Execution Starts here I→ Mov R0,A
I+4→ ADD R0,B
I+8→ MOV C,R0

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•The addresses of the memory locations containing the n numbers are represented
as NUM1,NUM2…..NUMn(i.e. NUM1 address includes first number).
•The first number is stored into processor register R0. And every other number is
added to register R0. Finally, when the program ends(i.e. n numbers are added, the
result is placed in memory location SUM

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•The second way is to use a loop to add n number. But here straight line sequencing is not used
because every time loop iteration ends, PC has to load the branch address and program execution
starts from that address.
•Here the location N stores the value of n.
•Processor register R1 is used as a counter to determine the number of times the loop get
executed.
•The contents of the location N are moved into R1 at the start of program execution.
•After that, register R0 is cleared.
•The address LOOP is reloaded again and again until R1 becomes 0.
•Every time a number is added, then the R1 value is decremented.
•When R1 becomes 0, we come out of the loop and the result which is stored at R1 is copied into
memory location SUM.

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 Address Contents
Execution Starts here I→ MOV R1,N
I+4→ CLEAR R0
I+8→ LOOP ADD R0,R1
I+12→ DCR R1
I+16→ BRANCH>0 LOOP
I+20→ MOV SUM,R0

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 Condition Codes
The processor keeps track of information about the results of
various operations for use by subsequent conditional branch
instructions

N – Negative 1 if results are Negative

0 if results are Positive
Z – Zero 1 if results are Zero
0 if results are Non zero
V – Overflow 1 if arithmetic overflow occurs
0 non overflow occurs
C – Carry 1 if carry and from MSB bit
0 if there is no carry from MSB bit
87
Addressing Modes

88
 Addressing Modes
Different ways in which the location of the operand is specified in an instruction is
referred as addressing modes
The purpose of using addressing mode is:
To give the programming versatility to the user.
To reduce the number of bits in addressing field of instruction.
Types of Addressing Modes
• Immediate Addressing
• Direct Addressing
• Indirect Addressing
• Register Addressing
• Register Indirect Addressing
• Relative Addressing
• Indexed Addressing
• Auto Increment
• Auto Decrement 89
 Immediate Addressing
• Operand is given explicitly in the instruction
• e.g. ADD 5
– Add 5 to contents of accumulator
– 5 is operand
• No memory reference to fetch data
• Fast
• Limited range
• MOV AL,25H ; Immediate addressing AL=25
• MOV AX,2345H ; AX=2345 AX=> AH=23
AL=45

90
 Direct Addressing
• Address field contains address of operand
• Effective address (EA) = address field (A)
• e.g. ADD A
– Add contents of cell A to accumulator
– Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations to work out effective address
• Limited address space
• MOV AL,DATA1 ; Direct Addressing AL=23
• MOV AX,DATA2 ; AX=1234

• MOV DATA3,AL ; DATA3=23

• MOV DATA4,AX ; DATA4=1234
91
92
 Indirect Addressing
• Memory cell pointed to by address field contains the address
of (pointer to) the operand
Two references to memory are required to fetch the operand.
• Effective Address = [A]
– Look in A, find address (A) and look there for operand
• e.g. ADD (A)
– Add contents of cell pointed to by contents of A to the
accumulator

93
94
 Register Direct Addressing
In this addressing mode,
• The operand is contained in a register set.
• The address field of the instruction refers to a CPU register
that contains the operand.
• No memory access
• Very fast execution
• Very limited address space
• Limited number of registers
• Very small address field needed
– Shorter instructions
– Faster instruction fetch
95
 Register Direct Addressing
Eg:
ADD R will increment the value stored in the
accumulator by the content of register R.
AC ← AC + [R]
• This addressing mode is similar to direct addressing
mode.
• The only difference is address field of the instruction
refers to a CPU register instead of main memory.

96
97
 Register Indirect Addressing
• The address field of the instruction refers to a CPU
register that contains the effective address of the
operand.
• Only one reference to memory is required to fetch the
operand
Eg:
ADD (R) will increment the value stored in the
accumulator by the content of memory location
specified in register R.
AC ← AC + [[R]]
98
99
 Indexed Addressing
In this addressing mode,
• Effective address of the operand is obtained by
adding the content of index register with the address
part of the instruction.

Effective Address
= Content of Index Register +
Address part of the instruction

100
101
 Relative Addressing
A version of displacement addressing
In this addressing mode,
• Effective address of the operand is obtained by adding
the content of program counter with the address part of the
instruction.
Effective Address
= Content of Program Counter +
Address part of the instruction

102
103
 Auto increment mode
A special case of Register Indirect Addressing Mode where
Effective Address of the Operand
= Content of Register

In this addressing mode,

• After accessing the operand, the content of the register is
automatically incremented by step size ‘d’.
• Step size ‘d’ depends on the size of operand accessed.
• Only one reference to memory is required to fetch the operand.

104
105
 Auto decrement mode
• A special case of Register Indirect Addressing Mode where
Effective Address of the Operand
= Content of Register – Step Size

In this addressing mode

• First, the content of the register is decremented by step size
‘d’.
• Step size ‘d’ depends on the size of operand accessed.
• After decrementing, the operand is read.
• Only one reference to memory is required to fetch the operand.

106
107
Introduction to Microprocessor

108
 Microprocessors
Microprocessor : It is a semiconductor device consisting
of electronic logic circuits. It includes the ALU, register
arrays and control circuits on a single chip, it is a CPU
on a single chip.
Microcontroller: If a microprocessor contains support
circuitry, memory and peripheral I/O components
implemented on a single chip, it is a microcontroller.

109
What is Microprocessor and Microcontroller?

110
111
Internal structure and basic operation of
microprocessor

Address bus
ALU Register
Section
Data bus

Control and timing

section Control bus

Block diagram of a Microprocessor

112
• Microprocessor performs three main tasks:
– data transfer between itself and the memory or I/O
systems
– simple arithmetic and logic operations
– program flow via simple decisions

113
 Microprocessor types
• Microprocessors can be characterized based on
– the word size
• 8 bit, 16 bit, 32 bit, etc. processors
– Instruction set structure
• RISC (Reduced Instruction Set Computer), CISC
(Complex Instruction Set Computer)
– Functions
• General purpose, special purpose such image
processing, floating point calculations
– And more …

114
 Evolution of Microprocessors
• The first microprocessor was introduced in 1971 by Intel
Corp.
• It was named Intel 4004 as it was a 4 bit processor.
Categories according to the generations or size
First Generation (4 - bit Microprocessors)
• could perform simple arithmetic such as addition, subtraction,
and logical operations like Boolean OR and Boolean AND.
• had a control unit capable of performing control functions like
– fetching an instruction from storage memory,
– decoding it, and then
– generating control pulses to execute it.
115
Second Generation (8 - bit Microprocessor)
• The second generation microprocessors were introduced in
1973 again by Intel.
• the first 8 - bit microprocessor which could perform
arithmetic and logic operations on 8-bit words.
Third Generation (16 - bit Microprocessor)
• introduced in 1978
• represented by Intel's 8086, Zilog Z800 and 80286,
• 16 - bit processors with a performance like minicomputers.

116
Fourth Generation (32 - bit Microprocessors)
• Several different companies introduced the 32-bit
microprocessors
• the most popular one is the Intel 80386

Fifth Generation (64 - bit Microprocessors)

• Introduced in 1995
• After 80856, Intel came out with a new processor namely
Pentium processor followed by Pentium Pro CPU
• allows multiple CPUs in a single system to achieve
multiprocessing.
• Other improved 64-bit processors are Celeron, Dual, Quad,
Octa Core processors.
117
 Typical microprocessors
• Most commonly used
– 68K
• Motorola
– x86
• Intel
– IA-64
• Intel
– MIPS
• Microprocessor without interlocked pipeline stages
– ARM
• Advanced RISC Machine
– PowerPC
• Apple-IBM-Motorola alliance
– Atmel AVR
• A brief summary will be given later

118
 8086 Microprocessor
• designed by Intel in 1976
• 16-bit Microprocessor having
• 20 address lines
• 16 data lines
• provides up to 1MB storage
• consists of powerful instruction set, which provides
operations like multiplication and division easily.
supports two modes of operation
Maximum mode :
suitable for system having multiple processors
Minimum mode :
suitable for system having a single processor.
119
 Features of 8086
• Has an instruction queue, which is capable of storing six instruction bytes
• First 16-bit processor having
– 16-bit ALU
– 16-bit registers
– internal data bus
– 16-bit external data bus
uses two stages of pipelining
1. Fetch Stage and
2. Execute Stage
which improves performance.
Fetch stage : can pre-fetch up to 6 bytes of instructions and stores
them in the queue.
Execute stage : executes these instructions.
120
Architecture of 8086

121
 Segments in 8086
memory is divided into various sections called segments

Code segment : where you store the program.

Data segment : where the data is stored.
Extra segment : mostly used for string operations.
Stack segment : used to push/pop

122
 General purpose registers
used to store temporary data within the microprocessor
AX – Accumulator
16 bit register
divided into two 8-bit registers AH and AL
to perform 8-bit instructions also
generally used for arithmetical and logical instructions
BX – Base register
16 bit register
divided into two 8-bit registers BH and BL
to perform 8-bit instructions also
Used to store the value of the offset.
123
CX – Counter register
16 bit register
divided into two 8-bit registers CH and CL
to perform 8-bit instructions also
Used in looping and rotation
DX – Data register
16 bit register
divided into two 8-bit registers DH and DL to
perform 8-bit instructions also
Used in multiplication an input/output port addressing

124
 Pointers and Index Registers
SP – Stack pointer
16 bit register
points to the topmost item of the stack
If the stack is empty the stack pointer will be (FFFE)H
It’s offset address relative to stack segment
BP –Base pointer
16 bit register
used in accessing parameters passed by the stack
It’s offset address relative to stack segment

125
SI – Source index register
16 bit register
used in the pointer addressing of data and
as a source in some string related operations
It’s offset is relative to data segment
DI – Destination index register
16 bit register
used in the pointer addressing of data and
as a destination in string related operations
It’s offset is relative to extra segment.

126
IP - Instruction Pointer
16 bit register
stores the address of the next instruction to be executed
also acts as an offset for CS register.

127
 Segment Registers
CS - Code Segment Register:
Contains the starting address of the code segment user cannot modify the
content of these registers
Only the microprocessor's compiler can do this
DS - Data Segment Register:
Contains the starting address of the data segment. The user can modify
the content of the data segment.
SS - Stack Segment Registers:
used to store the information about the stack memory segment.
operations of the SS are mainly Push and Pop.
ES - Extra Segment Register:
By default, the control of the compiler remains in the DS where the user
can add and modify the instructions
If there is less space in that segment, then ES is used
Also used for copying purpose. 128
 Flag or Status Register
• 16-bit register
• contains 9 flags
• remaining 7 bits are idle in this register
• These flags tell about the status of the processor after any
arithmetic or logical operation
• IF the flag value is 1, the flag is set, and if it is 0, it is said to
be reset.

129
 Microcomputer
• A digital computer with one
Block Diagram
microprocessor which acts
as a CPU
• A complete computer on a
small scale, designed for use
by one person at a time
• called a personal computer
(PC)
• a device based on a single-
chip microprocessor
• includes laptops and
desktops
130
Introduction to 8086 Assembly
Language

Assembly Language Programming

131
 Program Statements
• Program consist of statement, one per line.
• Each statement is either an instruction, which the assembler
translate into machine code, or assembler directive, which
instructs the assembler to perform some specific task, such as
allocating memory space for a variable or creating a
procedure.
• Both instructions and directives have up to four fields:
• At least one blank or tab character must separate the fields

name operation operand(s) comment

132
 Program Statements
• An example of an instruction is
START: MOV CX,5 ; initialize counter
name operation operand(s) comment
➢ The name field consists of the label START:
➢ The operation is MOV, the operands are CX and 5
➢ And the comment is ; initialize counter

of An example an assembler directive is

MAIN PROC
name operation operand(s) comment
➢ MAIN is the name, and the operation field contains PROC
➢ This particular directive creates a procedure called MAIN
133
 Program Statements
name operation operand(s) comment
• A Name field identifies a label, variable, or symbol.
It may contain any of the following character :
A,B…..Z ; a,b….9 ; ? ;
_ (underline) ; @ ; $ ; ,1e . (p….z ; 0riod)

➢ Only the first 31 characters are recognized

➢ There is no distinction between uppercase and lower case letters.
➢ The first character may not be a digit
➢ If it is used, the period ( . ) may be used only as the first
character.
➢ A programmer-chosen name may not be the same as an
assembler reserved word.
134
 Program Statements
name operation operand(s) comment
• Operation field is a predefined or reserved word
➢ mnemonic - symbolic operation code.
• The assembler translates a symbolic opcode into a
machine language opcode.
• Opcode symbols often discribe the operation’s function;
for example, MOV, ADD, SUB
➢ assemler directive - pseudo-operation code.
• In an assembler directive, the operation field contains a
pseudo-operation code (pseudo-op)
• Pseudo-op are not translated into machine code; for
example the PROC pseudo-op is used to create a
procedure
135
 Program Statements
name operation operand(s) comment

• An operand field specifies the data that are to be acted on by the

operation.
• An instruction may have zero, one, or two operands. For
example:
▪ NOP No operands; does nothing

▪ INC AX one operand; adds 1 to the

contents of AX

▪ ADD R1, 2 two operands; adds 2 to the

contents of register R1

136
 Program Statements
name operation operand(s) comment

• The comment field is used by the programmer to say something

about what the statement does.

• A semicolon marks the beginning of this field, and the

assembler ignores anything typed after semicolon.

• Comments are optional, but because assembly language is low

level, it is almost impossible to understand an assembly
language program without comments.

137
 Program Data and Storage
• Pseudo-ops to define • These directives require
data or reserve storage one or more operands
– DB - byte(s) – define memory contents
– DW - word(s) – specify amount of
– DD - doubleword(s) storage to reserve for
– DQ - quadword(s) run-time data
– DT - tenbyte(s)

138
 Defining Data
• Numeric data values • A list of values may be
– 100 - decimal used - the following
– 100B - binary creates 4 consecutive
– 100H - hexadecimal words
– '100' - ASCII DW 40CH,10B,-13,0
– "100" - ASCII • A ? represents an
• Use the appropriate uninitialized storage
DEFINE directive (byte, location
word, etc.) DB 255,?,-128,'X'

139
 Naming Storage Locations
• Names can be • ANum refers to a byte
associated with storage storage location,
locations initialized to -4
ANum DB -4 • The next word has no
DW 17 associated name
ONE
UNO DW 1
• ONE and UNO refer to
X DD ? the same word
• These names are called • X is an unitialized
variables doubleword

140
• Multiple definitions can be abbreviated
Example:
message DB ’B’
DB ’y’
DB ’e’
DB 0DH
DB 0AH
can be written as
message DB ’B’,’y’,’e’,0DH,0AH

• More compactly as
message DB ’Bye’,0DH,0AH
141
 Arrays
• Any consecutive storage locations of the same size can be
called an array
X DW 40CH,10B,-13,0
Y DB 'This is an array'
Z DD -109236, FFFFFFFFH, -1, 100B
• Components of X are at X, X+2, X+4, X+6
• Components of Y are at Y, Y+1, …, Y+15
• Components of Z are at Z, Z+4, Z+8, Z+12

142
 DUP
• Allows a sequence of storage locations to be defined or
reserved
• Only used as an operand of a define directive
DB 40 DUP (?) ; 40 words, uninitialized
DW 10h DUP (0) ; 10 words, initialized as 0

Table1 DW 10 DUP (?) ; 10 words, uninitialized

message DB 3 DUP (’Baby’) ; 12 bytes, initialized

; as BabyBabyBaby
Name1 DB 30 DUP (’?’) ; 30 bytes, each
; initialized to ? 143
 DUP
The DUP directive may also be nested
Example
stars DB 4 DUP(3 DUP (’*’),2 DUP (’?’),5 DUP (’!’))
Reserves 40-bytes space and initializes it as
***??!!!!!***??!!!!!***??!!!!!***??!!!!!

matrix DW 10 DUP (5 DUP (0))

defines a 10X5 matrix and initializes its elements to zero.

This declaration can also be done by

matrix DW 50 DUP (0)

144
Word Storage

145
 Named Constants
• Symbolic names associated with storage locations represent
addresses
• Named constants are symbols created to represent specific
values determined by an expression
• Named constants can be numeric or string
• Some named constants can be redefined
• No storage is allocated for these values

146
 Equal Sign Directive
• name = expression
– expression must be numeric
– these symbols may be redefined at any time
maxint = 7FFFh
count = 1
DW count
count = count * 2
DW count

147
 EQU Directive
• name EQU expression
– expression can be string or numeric
– Use < and > to specify a string EQU
– these symbols cannot be redefined later in the program
sample EQU 7Fh
aString EQU <1.234>
message EQU <This is a message>

148
 Data Transfer Instructions
• MOV target, source • reg can be any non-segment
– reg, reg register except IP cannot be
– mem, reg the target register
– reg, mem • MOV's between a segment
register and memory or a
– mem, immed
16-bit register are possible
– reg, immed
• Sizes of both operands must
be the same

149
 Sample MOV Instructions
b db 4Fh • When a variable is created with a
w dw 2048 define directive, it is assigned a
default size attribute (byte, word,
mov bl,dh etc)
mov ax,w • You can assign a size attribute using
mov ch,b LABEL
mov al,255 LoByte LABEL BYTE
mov w,-100 aWord DW 97F2h
mov b,0

150
 Program Segment Structure
• Data Segments • Stack Segment
– Storage for variables – used to set aside storage
– Variable addresses are for the stack
computed as offsets from – Stack addresses are
start of this segment computed as offsets into
• Code Segment this segment
– contains executable • Segment directives
instructions .data
.code
.stack size

151
 Instruction types
8086 instruction set Data transfer instructions
IN Input byte or word from port
LAHF Load AH from flags
LDS Load pointer using data segment
LEA Load effective address
LES Load pointer using extra segment
MOV Move to/from register/memory
OUT Output byte or word to port
POP Pop word off stack
POPF Pop flags off stack
PUSH Push word onto stack
PUSHF Push flags onto stack
SAHF Store AH into flags
XCHG Exchange byte or word
XLAT Translate byte

152
8086 instruction set
Arithmetic instructions
AAA ASCII adjust for addition
AAD ASCII adjust for division
AAM ASCII adjust for multiply Additional 80386 instructions
AAS ASCII adjust for subtraction CDQ Convert double-word to
ADC Add byte or word plus carry quad-word
ADD Add byte or word CWDE Convert word to double-word
CBW Convert byte to word
CMP Compare byte or word Additional 80486 instructions
CWD Convert word to double-word CMPXCHG Compare and exchange
DAA Decimal adjust for addition XADD Exchange and add
DAS Decimal adjust for subtraction
DEC Decrement byte or word by one
DIV Divide byte or word Additional Pentium instruction
IDIV Integer divide byte or word CMPXCHG8B Compare and
IMUL Integer multiply byte or word exchange 8 bytes
INC Increment byte or word by one
MUL Multiply byte or word (unsigned)
NEG Negate byte or word
SBB Subtract byte or word and carry (borrow) 153
 Bit manipulation instructions
8086 instruction set
AND Logical AND of byte or word Additional 80386 instructions
NOT Logical NOT of byte or word BSF Bit scan forward
OR Logical OR of byte or word BSR Bit scan reverse
RCL Rotate left trough carry byte or word BT Bit test
RCR Rotate right trough carry byte or word BTC Bit test and complement
ROL Rotate left byte or word BTR Bit test and reset
ROR Rotate right byte or word BTS Bit test and set
SAL Arithmetic shift left byte or word SETcc Set byte on condition
SAR Arithmetic shift right byte or word SHLD Shift left double precision
SHL Logical shift left byte or word SHRD Shift right double precision
SHR Logical shift right byte or word
TEST Test byte or word
XOR Logical exclusive-OR of byte or word

154
 String instructions
8086 instruction set
CMPS Compare byte or word string
LODS Load byte or word string
MOVS Move byte or word string
MOVSB(MOVSW) Move byte string (word string)
REP Repeat
REPE (REPZ) Repeat while equal (zero)
REPNE (REPNZ) Repeat while not equal (not zero)
SCAS Scan byte or word string
STOS Store byte or word string

155
 Program Skeleton
.model small • Select a memory model
.stack 100H • Define the stack size
.data • Declare variables
;declarations
.code
• Write code
main proc
– organize into procedures
;code
main endp • Mark the end of the source file
;other procs – optionally, define the entry
end main point

156
 EXAMPLE : Adding two 8 bit numbers
DATA SEGMENT ; Data Segment
N1 DB 12H
N2 DB 21H
RES DB ?
DATA ENDS
CODE SEGMENT ; Code segment
ASSUME CS: CODE, DS: DATA
START: MOV AX, DATA
MOV DS, AX
MOV AL, N1
MOV BL, N2
ADD AL, BL
MOV RES, AL
INT 21H
CODE ENDS
END START

157
The ARM Architecture

158
 ARM Ltd
The first ARM processor was developed in the year 1978 by
Cambridge University, and the first ARM RISC processor was
produced by the Acorn Group of Computers in the year 1985.
An ARM processor is one of a family of CPUs based on the RISC
(reduced instruction set computer) architecture developed by
Advanced RISC Machines (ARM).
ARM makes 32-bit and 64-bit RISC multi-core processors.
RISC processors are designed to perform a smaller number of
computer instructions so that they can operate at a higher speed,
performing more millions of instructions per second (MIPS).
By stripping out unneeded instructions and optimizing pathways,
RISC processors provide outstanding performance at a fraction of the
power demand of CISC (complex instruction set computing) devices.
159
 ARM Ltd
ARM processors are extensively used in consumer electronic devices
such as smartphones, tablets, multimedia players and other mobile
devices, such as wearables.
The ARM processor’s smaller size, reduced complexity and lower
power consumption makes them suitable for increasingly
miniaturized devices.
ARM processor features include:
Load/store architecture.
An orthogonal instruction set.
Mostly single-cycle execution.
Enhanced power-saving design.
64 and 32-bit execution states for scalable high performance.
Hardware virtualization support.
160
 RISC
• RISC is an abbreviation of Reduced Instruction Set Computer.
• RISC processor has ‘instruction sets’ that are simple and have
simple ‘addressing modes’.
• A RISC style instruction engages “one word” in memory.
• Execution of the RISC instructions are faster and take one clock
cycle per instruction.
• RISC architecture emphasizes on using the registers rather than
memory.
• The RISC instructions operate on the operands present in
processor’s registers.
• RISC is a type of microprocessor architecture that utilizes a small,
highly-optimized set of instructions, rather than a more specialized
set of instructions often found in other types of architectures.
161
 ARM Processor Architecture
• The ARM architecture processor is an advanced reduced instruction set
computing [RISC] machine and it’s a 32bit reduced instruction set
computer (RISC) microcontroller.
• It was introduced by the Acron computer organization in 1987.
• This ARM is a family of microcontroller developed by makers like ST
Microelectronics, Motorola, and so on.
• The ARM architecture comes with totally different versions like
ARMv1, ARMv2, etc., and, each one has its own advantage and
disadvantages.
• The ARM cortex is a complicated microcontroller within the ARM
family that has ARMv7 design.
• There are 3 subfamilies within the ARM cortex family :
– ARM Cortex Ax-series
– ARM-Cortex Rx-series
162
– ARM-Cortex Mx-series
 Data Sizes and Instruction Sets
• The ARM is a 32-bit architecture.

• When used in relation to the ARM:

– Byte means 8 bits
– Halfword means 16 bits (two bytes)
– Word means 32 bits (four bytes)

• Most ARM’s implement two instruction sets

– 32-bit ARM Instruction Set
– 16-bit Thumb Instruction Set

• Jazelle cores can also execute Java bytecode

163
 Processor Modes
• The ARM has seven basic operating modes:

– User : unprivileged mode under which most tasks run

– FIQ : entered when a high priority (fast) interrupt is raised

– IRQ : entered when a low priority (normal) interrupt is raised

– Supervisor : entered on reset and when a Software Interrupt

instruction is executed

– Abort : used to handle memory access violations

– Undef : used to handle undefined instructions

– System : privileged mode using the same registers as user mode

164
 The Registers
• ARM has 37 registers all of which are 32-bits long.
– 1 dedicated program counter
– 1 dedicated current program status register
– 5 dedicated saved program status registers
– 30 general purpose registers

• The current processor mode governs which of several banks is accessible.

Each mode can access
– a particular set of r0-r12 registers
– a particular r13 (the stack pointer, sp) and r14 (the link register, lr)
– the program counter, r15 (pc)
– the current program status register, cpsr

Privileged modes (except System) can also access

– a particular spsr (saved program status register)

165
 User
Register Organization Summary
FIQ IRQ SVC Undef Abort
r0
r1
User
r2 mode
r3 r0-r7,
r4 r15, User User User User
r5 and mode mode mode mode Thumb state
cpsr r0-r12, r0-r12, r0-r12, r0-r12,
r6
r15, r15, r15, r15,
Low registers
r7 and and and and
r8 r8 cpsr cpsr cpsr cpsr
r9 r9
r10 r10 Thumb state
r11 r11 High registers
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr

Note: System mode uses the User mode register set

166
 The ARM Register Set
Current Visible Registers
SVC Current
Undef
IRQ
FIQ Mode Visible
Mode
UserMode
r0 Registers
r1
r0
r2
Abort Mode
r1
r3
r2
Banked out Registers
r4
r3
r5 Banked out Registers
r4
r6 User FIQ IRQ SVC Undef Abort
r5
r7
r6
r8
User
r8
FIQ
r8
IRQ SVC Undef
r7
r9 r9 r9
r8 r8
r10 r10 r10
r9 r9
r11 r11 r11
r10 r10
r12 r12 r12
r11 r11
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r12 r12
r14 (lr)
r13 (sp) r14 (sp)
r13 (lr) r14 (lr)
r13 (sp) r14 (sp)
r13 (lr) r14 (sp)
r13 (lr) r14 (sp)
r13 (lr) r14 (lr)
r15
r14 (pc)
(lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)
cpsr
spsr
cpsr spsr spsr spsr spsr spsr
spsr spsr spsr spsr spsr
167
Mode Bits

168
 Program Counter (r15)
• When the processor is executing in ARM state:
– All instructions are 32 bits wide
– All instructions must be word aligned
– Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as
instruction cannot be halfword or byte aligned).

• When the processor is executing in Thumb state:

– All instructions are 16 bits wide
– All instructions must be halfword aligned
– Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as
instruction cannot be byte aligned).

• When the processor is executing in Jazelle state:

– All instructions are 8 bits wide
– Processor performs a word access to read 4 instructions at once

169
 Arithmetic Logic Unit (ALU)
• The ALU has two 32-bits inputs. The primary input comes
from the register file, whereas the other input comes from the
shifter.
• Status registers flags modified by the ALU outputs.

170
 Booth algorithm
• Booth algorithm is a noteworthy multiplication algorithmic
rule for 2’s complement numbers.
• This treats positive and negative numbers uniformly.
• Moreover, the runs of 0’s or 1’s within the multiplier factor are
skipped over without any addition or subtraction being
performed, thereby creating possible quicker multiplication.
• It’s clear that the multiplication finishes only in16 clock cycle.

171
 Control Unit
• For any microprocessor, control unit is the heart of the whole
process and it is responsible for the system operation, so the
control unit design is the most important part within the whole
design.
• The control unit is sometimes a pure combinational circuit
design.
• Here, the control unit is implemented by easy state machine.
• The processor timing is additionally included within the
control unit.
• Signals from the control unit are connected to each component
within the processor to supervise its operation.

172
 Program Status Registers
31 28 27 24 23 16 15 8 7 6 5 4 0

NZC V Q J U n de f i n e d I F T mode
f s x c
• Condition code flags
– N = Negative result from ALU • Interrupt Disable bits.
– Z = Zero result from ALU
– I = 1: Disables the
– C = ALU operation Carried out IRQ.
– V = ALU operation oVerflowed
– F = 1: Disables the
• Sticky Overflow flag - Q flag FIQ.
– Architecture 5TE/J only
– Indicates if saturation has occurred • T Bit
• Bit[27] of the CPSR is a sticky overflow flag, also known as the Q – Architecture xT only
flag. This flag is set to 1 if any of the following occurs:
• Saturation of the addition result in a QADD or QDADD instruction. – T = 0: Processor in
• Saturation of the subtraction result in a QSUB or QDSUB ARM state
instruction. – T = 1: Processor in
Thumb state
• J bit
– Architecture 5TEJ only
• Mode bits
– J = 1: Processor in Jazelle state
– Specify the processor
mode
173
 Exception Handling
• When an exception occurs, the ARM:
– Copies CPSR into SPSR_<mode>
– Sets appropriate CPSR bits
0x1C FIQ
• Change to ARM state
0x18 IRQ
• Change to exception mode
0x14 (Reserved)
• Disable interrupts (if appropriate)
0x10 Data Abort
– Stores the return address in 0x0C Prefetch Abort
LR_<mode> 0x08 Software Interrupt

– Sets PC to vector address 0x04 Undefined Instruction

• To return, exception handler needs to: 0x00 Reset

– Restore CPSR from SPSR_<mode> Vector Table

Vector table can be at
– Restore PC from LR_<mode> 0xFFFF0000 on ARM720T
This can only be done in ARM state. and on ARM9/10 family
devices
174
 link register (LR or R14)
• The link register (LR or R14) is a core register that
stores the return address, such as when making a
function call.
• In the case of an exception, the return address is
pushed onto the stack by hardware and the LR is set
to EXC_RETURN

175
 Conditional Execution and Flags
• ARM instructions can be made to execute conditionally by postfixing
them with the appropriate condition code field.
– This improves code density and performance by reducing the
number of forward branch instructions.
CMP r3,#0 CMP r3,#0
BEQ skip ADDNE r0,r1,r2
ADD r0,r1,r2
skip

176
 Condition Codes
• The possible condition codes are listed below:
• Note AL is the default and does not need to be specified
Suffix Description Flags tested
EQ Equal Z=1
NE Not equal Z=0
CS/HS Unsigned higher or same C=1
CC/LO Unsigned lower C=0
MI Minus N=1
PL Positive or Zero N=0
VS Overflow V=1
VC No overflow V=0
HI Unsigned higher C=1 & Z=0
LS Unsigned lower or same C=0 or Z=1
GE Greater or equal N=V
LT Less than N!=V
GT Greater than Z=0 & N=V
LE Less than or equal Z=1 or N=!V
AL Always
177
 Examples of conditional execution
• Use a sequence of several conditional instructions
if (a==0) func(1);

CMP r0,#0
MOVEQ r0,#1
BLEQ func

if (a==0) x=0;
if (a>0) x=1;
CMP r0,#0
MOVEQ r1,#0
MOVGT r1,#1

• Use conditional compare instructions

if (a==4 || a==10) x=0;
CMP r0,#4
CMPNE r0,#10
MOVEQ r1,#0

178
 Branch instructions
• Branch : B{<cond>} label
• Branch with Link : BL{<cond>} subroutine_label

31 28 27 25 24 23 0

Cond 1 0 1 L Offset

Link bit 0 = Branch

1 = Branch with link
Condition field

• Branch with link (BL) copies the address of the next instruction
(after the BL) into the link register. The branch instruction doesn't.
BL would be used for a subroutine call.

179
 Data processing Instructions
• Consist of :
– Arithmetic: ADD ADC SUB SBC RSB RSC
– Logical: AND ORR EOR BIC
– Comparisons: CMP CMN TST TEQ
– Data movement: MOV MVN
• The BIC (Bit Clear) instruction performs an AND operation on the bits in Rn with
the complements of the corresponding bits in the value of Operand2
• EOR: bit 0 of the <lhs> is EORed with bit 0 of the <rhs> and stored in bit 0 of the
<dest> , and so on. The EOR instruction is often used to invert the state of certain
bits of a register without affecting the rest.
• The TST instruction performs a bitwise AND operation on the value in Rn and the
value of Operand2
• The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn
and the value of Operand2
• The MVN instruction takes the value of Operand2 , performs a bitwise logical NOT
operation on the value, and places the result into Rd
• These instructions only work on registers, NOT memory. 180
• Second operand is sent to the ALU via barrel shifter.
EXAMPLE

181
EXAMPLE

182
Barrel Shifter & Memory
Instructions

183
 The Barrel Shifter
LSL : Logical Left Shift ASR: Arithmetic Right Shift

CF Destination 0 Destination CF

Multiplication by a power of 2 Division by a power of 2,

preserving the sign bit
LSR : Logical Shift Right ROR: Rotate Right

...0 Destination CF Destination CF

Division by a power of 2 Bit rotate with wrap around

from LSB to MSB
RRX: Rotate Right Extended

Destination CF

Single bit rotate with wrap around 184

from CF to MSB
Using the Barrel Shifter: The Second Operand

Operand Operand
1 2

Barrel
Shifter

ALU

Result 185
EXAMPLE

186
187
Single register data transfer

188
189
(LDM/STM)

190
(LDM/STM) Operations

191
 Software Interrupt (SWI) 0
31 28 27 24 23

Cond 1 1 1 1 SWI number (ignored by processor)

Condition Field

• Causes an exception trap to the SWI hardware vector

• The SWI handler can examine the SWI number to decide what
operation has been requested.
• By using the SWI mechanism, an operating system can
implement a set of privileged operations which applications
running in user mode can request.
• Syntax:
SWI{<cond>} <SWI number>
192
 Example ARM-based System

16 bit RAM 32 bit RAM

Interrupt
Controller
Peripherals I/O
nIRQ nFIQ

ARM
Core
8 bit ROM

193
Basics of Input - Output
Operations

194
 Input - Output Interface
Input Output Interface provides a method for
transferring information between internal storage and
external I/O devices. Peripherals connected to a
computer need special communication links for
interfacing them with the central processing unit.
 Input - Output Interface
The purpose of communication link is to resolve the
differences that exist between the central computer
and each peripheral.
 The Major Differences are:-
1. Peripherals are electro-mechanical and
electromagnetic devices and their manner of operation
of the CPU and memory, which are electronic devices.
Therefore, a conversion of signal values may be
needed.
2. The data transfer rate of peripherals is usually slower
than the transfer rate of CPU and consequently, a
synchronization mechanism may be needed.
 The Major Differences are:-
3. Data codes and formats in the peripherals differ
from the word format in the CPU and memory.
4. The operating modes of peripherals are different
from each other and must be controlled so as not to
disturb the operation of other peripherals connected
to the CPU.
 Input - Output Interface
To Resolve these differences, computer systems
include special hardware components between the
CPU and Peripherals to supervises and synchronizes
all input and out transfers. These components are
called Interface Units because they interface
between the processor bus and the peripheral devices.
I/O BUS and Interface Module
It defines the typical link between the processor and
several peripherals. The I/O Bus consists of data lines,
address lines and control lines.
The I/O bus from the processor is attached to all
peripherals interface. To communicate with a particular
device, the processor places a device address on address
lines.
 I/O BUS and Interface Module
Each Interface decodes the address and control received
from the I/O bus, interprets them for peripherals and
provides signals for the peripheral controller.
It is also synchronizes the data flow and supervises the transfer
between peripheral and processor. Each peripheral has its
own controller. For example, the printer controller
controls the paper motion, the print timing.
 I/O BUS and Interface Module

The control lines are referred as an I/O command. The

commands are as following:
Control command- A control command is issued to
activate the peripheral and to inform it what to do.
Status command- A status command is used to test
various status conditions in the interface and the
peripheral.
I/O BUS and Interface Module

Output data command-

A data output command causes the interface to respond
by transferring data from the bus into one of its
registers.
Input data command-
The data input command is the opposite of the data
output. In this case the interface receives on item
of data from the peripheral and places it in its
buffer register.
I/O BUS and Interface Module

Data
Processor Address

Control

Interface Interface Interface

Keyboard
and Printer Magnetic
display disk
terminal

Connection of I/O bus to input-output devices

 I/O Versus Memory Bus

There are 3 ways that computer buses can be used to communicate with
memory and I/O:

i. Use two Separate buses , one for memory and other for I/O.
ii. Use one common bus for both memory and I/O but separate
control lines for each.
iii. Use one common bus for memory and I/O with common control lines.