Unit 5 COA
Unit 5 COA
Control lines
( R / W, MFC, etc.)
Data transfer between CPU and MM takes place through the
use of two CPU registers, MAR (Memory Address Register)
and MDR (Memory Data Register)
•
•
•
FF FF
A0 W1
•
•
•
A1
Address Memory
• • • • • • cells
decoder • • • • • •
A2
• • • • • •
A3
W15
•
•
•
T1 T 2
X Y
Word line
Bit lines
Static RAMs (SRAMs):
▪ Consist of circuits that are capable of retaining their state as long as the power
is applied.
▪ Volatile memories, because their contents are lost when power is interrupted.
▪ Access times of static RAMs are in the range of few nanoseconds.
▪ However, the cost is usually high.
CAS D7 D0
Suppose if we want to access the consecutive bytes in
the selected row.
This can be done without having to reselect the row.
▪ Add a latch at the output of the sense circuits in each row.
▪ All the latches are loaded when the row is selected.
▪ Different column addresses can be applied to select and place different bytes on
the data lines.
Consecutive sequence of column addresses can be
applied under the control signal CAS, without
reselecting the row.
▪ Allows a block of data to be transferred at a much faster rate than random
accesses.
▪ A small collection/group of bytes is usually referred to as a block.
This transfer capability is referred to as the
fast page mode feature.
•Operation is directly synchronized
Refresh
counter with processor clock signal.
•The outputs of the sense circuits are
connected to a latch.
Row •During a Read operation, the
Ro w
address decoder Cell array contents of the cells in a row are
latch
Row/Column loaded onto the latches.
address •During a refresh operation, the
Column Co lumn Read/Write contents of the cells are refreshed
address
counter decoder circuits & latches without changing the contents of
the latches.
•Data held in the latches correspond
Clock
to the selected columns are transferred
RAS to the output.
Mode register
CA S and Data input Data output •For a burst mode of operation,
register register
R /W timing control successive columns are selected using
CS column address counter and clock.
CAS signal need not be generated
externally. A new data is placed during
Data
raising edge of the clock
Memory latency is the time it takes to
transfer a word of data to or from memory
Memory bandwidth is the number of bits or
bytes that can be transferred in one second.
DDRSDRAMs-Double-Data-Rate-SDRAM
Here , accessing the cell array is done in the same way
- - But data is transferred on both edges of the clock
- - Bandwidth is effectively doubled for large burst transfers
- - Such devices are called as DDR- SDRAM
▪
- To access data at the high rate , the cell array is
organized in two banks , called as even and
odd banks .
- each bank is accessed separately
- - Consecutive words of a given block are
stored in different banks
- - Such interleaving of words allow
simultaneous access to two words that are
transferred on successive edges of the clock
- - This interleaving approach improves the data
21-bi t
a ddresses 19-bit internal chip address Implement a memory unit of 2M
A0
A1 words of 32 bits each.
Use 512x8 static memory chips.
A 19 Each column consists of 4 chips.
A 20
Each chip implements one byte
position.
A chip is selected by setting its
chip select control line to 1.
Selected chip places its data on the
2-bi t
decoder data output line, outputs of other
chips are in high impedance state.
21 bits to address a 32-bit word.
High order 2 bits are needed to
512K 8
memory chi p
D 31-24 D 23-16 D 15-8 D 7-0
select the row, by activating the
four Chip Select signals.
512K 8 memory chi p
19 bits are used to access specific
byte locations inside the selected
19-bi t 8-bi t data
a ddress i nput/output chip.
Chi p s elect
Recall that in a dynamic memory chip, to reduce the
number of pins, multiplexed addresses are used.
Address is divided into two parts:
▪ High-order address bits select a row in the array.
▪ They are provided first, and latched using RAS signal.
▪ Low-order address bits select a column in the row.
▪ They are provided later, and latched using CAS signal.
However, a processor issues all address bits at the same
time.
In order to achieve the multiplexing, memory
controller circuit is inserted between the processor
and memory.
Row/Column
Address address
RAS
R/ W
C AS
Memory
Request controller R/ W
Processor Memory
CS
Clock
Clock
Data
22
Read-Only Memories (ROMs)
SRAM and SDRAM chips are volatile:
▪ Lose the contents when the power is turned off.
Many applications need memory devices to retain
contents after the power is turned off.
▪ For example, computer is turned on, the operating system must
be loaded from the disk into the memory.
▪ Store instructions which would load the OS from the disk.
▪ Need to store these instructions so that they will not be lost
after the power is turned off.
▪ We need to store the instructions into a non-volatile memory.
Non-volatile memory is read in the same manner as
volatile memory.
▪ Separate writing process is needed to place information in this
memory.
▪ Normal operation involves only reading of data, this type
of memory is called Read-Only memory (ROM).
Read-Only Memory:
▪ Data are written into a ROM when it is manufactured.
Programmable Read-Only Memory (PROM):
▪ Allow the data to be loaded by a user.
▪ Process of inserting the data is irreversible.
▪ Storing information specific to a user in a ROM is expensive.
Flash memory:
▪ Has similar approach to EEPROM.
▪ Read the contents of a single cell, but write the
contents of an entire block of cells.
A big challenge in the design of a computer system
is to provide a sufficiently large memory, with a
reasonable speed at an affordable cost.
Static RAM:
▪ Very fast, but expensive, because a basic SRAM cell has a complex circuit making it
impossible to pack a large number of cells onto a single chip.
Dynamic RAM:
▪ Simpler basic cell circuit, hence are much less expensive, but significantly slower than
SRAMs.
Magnetic disks:
▪ Storage provided by DRAMs is higher than SRAMs, but is still less than what is
necessary.
▪ Secondary storage such as magnetic disks provide a large amount
of storage, but is much slower than DRAMs.
Processor •Fastest access is to the data held in
processor registers. Registers are at
Registers the top of the memory hierarchy.
Increasing Increasing Increasing •Relatively small amount of memory that
size speed cost per bit can be implemented on the processor
Primary L1
cache chip. This is processor cache.
•Two levels of cache. Level 1 (L1) cache
is on the processor chip. Level 2 (L2)
cache is in between main memory and
Secondary L2 processor.
cache
•Next level is main memory, implemented
as SIMMs. Much larger, but much slower
than cache memory.
Main •Next level is magnetic disks. Huge amount
memory of inexepensive storage.
•Speed of memory access is critical, the
idea is to bring instructions and data
Magnetic disk that will be used in the near future as
secondary close to the processor as possible.
memory
Cache Memories
Processor is much faster than the main
memory.
Speed of the main memory cannot be
increased beyond a certain point.
Cache memory is an architectural
arrangement which makes the main memory
appear faster to the processor than it really is.
Cache memory is based on the property of
computer programs known as “locality of
reference”.
Analysis of programs indicates that many
instructions in localized areas of a program
are executed repeatedly during some period
of time, while the others are accessed
relatively less frequently.
Temporal locality of reference:
▪ Recently executed instruction is likely to be executed again very soon.
• Write hit:
▪ Cache has a replica of the contents of the main memory.
▪ Contents of the cache and the main memory may be updated simultaneously.
This is the write-through protocol.
▪ Update the contents of the cache, and mark it as updated by setting a bit known
as the dirty bit or modified bit. The contents of the main memory are updated
when this block is replaced. This is write-back or copy-back protocol.
• If the data is not present in the cache, then a Read miss or Write miss
occurs.
• Read miss:
▪ Block of words containing this requested word is transferred from the
memory.
▪ After the block is transferred, the desired word is forwarded to the processor.
▪ The desired word may also be forwarded to the processor as soon as it is
transferred without waiting for the entire block to be transferred. This is called
load-through or early-restart.
• Write-miss:
▪ Write-through protocol is used, then the contents of the main memory are
updated directly.
▪ If write-back protocol is used, the block containing the
addressed word is first brought into the cache. The desired word
is overwritten with new information.
• A bit called as “valid bit” is provided for each block.
• If the block contains valid data, then the bit is set to 1, else it is 0.
• Valid bits are set to 0, when the power is just turned on.
• When a block is loaded into the cache for the first time, the valid bit is set to 1.
• Data transfers between main memory and disk occur directly bypassing the cache.
• When the data on a disk changes, the main memory block is also updated.
• However, if the data is also resident in the cache, then the valid bit is set to 0.
• What happens if the data in the disk and main memory changes and the write-back
protocol is being used?
• In this case, the data in the cache may also have changed and is indicated by the
dirty bit.
• The copies of the data in the cache, and the main memory are different. This is
called the cache coherence problem.
• One option is to force a write-back before the main memory is updated from the
disk.
Mapping functions determine how memory
blocks are placed in the cache.
A simple processor example:
▪ Cache consisting of 128 blocks of 16 words each.
▪ Total size of cache is 2048 (2K) words.
▪ Main memory is addressable by a 16-bit address.
▪ Main memory has 64K words.
▪ Main memory has 4K blocks of 16 words each.
Three mapping functions:
▪ Direct mapping
▪ Associative mapping
▪ Set-associative mapping.
Main
memory Block 0 •Block j of the main memory maps to j modulo 128 of
Block 1
the cache. 0 maps to 0, 129 maps to 1.
Cache
tag
•More than one memory block is mapped onto the same
Block 0 position in the cache.
tag •May lead to contention for cache blocks even if the
Block 1
cache is not full.
Block 127
•Resolve the contention by allowing new block to
Block 128 replace the old block, leading to a trivial replacement
tag
Block 127 Block 129
algorithm.
•Memory address is divided into three fields:
- Low order 4 bits determine one of the 16
words in a block.
- When a new block is brought into the cache,
Block 255 the the next 7 bits determine which cache
Tag Block Word
5 7 4 Block 256 block this new block is placed in.
- High order 5 bits determine which of the possible
Main memory address Block 257
32 blocks is currently present in the cache. These
are tag bits.
•Simple to implement but not very flexible.
Block 4095
Main Block 0
memory
Block 1
•Main memory block can be placed into any cache
Cache
tag
position.
Block 0 •Memory address is divided into two fields:
tag - Low order 4 bits identify the word within a block.
Block 1
- High order 12 bits or tag bits identify a memory
Block 127
block when it is resident in the cache.
Block 128 •Flexible, and uses cache space efficiently.
tag
Block 129
•Replacement algorithms can be used to replace an
Block 127
existing block in the cache when the cache is full.
•Cost is higher than direct-mapped cache because of
the need to search all 128 patterns to determine
whether a given block is in the cache.
Block 255
Tag Word
12 4 Block 256
Block 4095
Blocks of cache are grouped into sets.
Mapping function allows a block of the main
memory to reside in any block of a specific set.
Divide the cache into 64 sets, with two blocks per set.
Memory block 0, 64, 128 etc. map to block 0, and they
can occupy either of the two positions.
Memory address is divided into three fields:
- 6 bit field determines the set number.
- High order 6 bit fields are compared to the tag
fields of the two blocks in a set.
Set-associative mapping combination of direct and
associative mapping.
Number of blocks per set is a design parameter.
- One extreme is to have all the blocks in one set,
requiring no set bits (fully associative mapping).
- Other extreme is to have one block per set, is
the same as direct mapping.
• For direct mapping where there is only one possible line for a block of memory,
no replacement algorithm is needed.
• For associative and set associative mapping, however, an algorithm is needed.
•For maximum speed, this algorithm is implemented in the hardware. Four of the
most common algorithms are:
1. Least Recently Used:- This replaces the candidate line in cache memory that
has been there the longest with no reference to it.
2. First In First Out:- This replaces the candidate line in the cache that has been
there the longest.
3. Least Frequently Used:- This replaces the candidate line in the cache that has
had the fewest references.
4. Random Replacement:- This algorithm randomly chooses a line to be
replaced from among the candidate lines. This yields only slightly inferior
performance than other algorithms.
Performance considerations
A key design objective of a computer system is to achieve
the best possible performance at the lowest possible cost.
▪ Price/performance ratio is a common measure of success.
Performance of a processor depends on:
▪ How fast machine instructions can be brought into the processor for
execution.
▪ How fast the instructions can be executed.
Divides the memory system into a number of
memory modules. Each module has its own address buffer register
(ABR) and data buffer register (DBR).
Arranges addressing so that successive words in
the address space are placed in different
modules.
When requests for memory access involve
consecutive addresses, the access will be to
different modules.
Since parallel access to these modules is
possible, the average rate of fetching words
from the Main Memory can be increased.
k bits m bits
mbits k bits
Module Address in module MM address
Address in module Module MM address
ABR DBR ABR DBR ABR DBR ABR DBR ABR DBR ABR DBR
51
Recall that the addressable memory space depends
on the number of address bits in a computer.
▪ For example, if a computer issues 32-bit addresses, the addressable memory space is 4G
bytes.
Physical main memory in a computer is generally not
as large as the entire possible addressable space.
▪ Physical memory typically ranges from a few hundred megabytes to 1G bytes.
Large programs that cannot fit completely into the
main memory have their parts stored on secondary
storage devices such as magnetic disks.
▪ Pieces of programs must be transferred to the main memory from secondary storage before
they can be executed.
52
When a new piece of a program is to be
transferred to the main memory, and the
main memory is full, then some other piece in
the main memory must be replaced.
▪ Recall this is very similar to what we studied in case of cache memories.
Operating system automatically transfers
data between the main memory and
secondary storage.
▪ Application programmer need not be concerned with this transfer.
▪ Also, application programmer does not need to be aware of the limitations
imposed by the available physical memory.
53
Techniques that automatically move program and
data between main memory and secondary storage
when they are required for execution are called
virtual-memory techniques.
Programs and processors reference an instruction or
data independent of the size of the main memory.
Processor issues binary addresses for instructions and
data called logical or virtual addresses.
Virtual addresses are translated into physical
addresses by a combination of hardware and software
subsystems.
▪ If virtual address refers to a part of the program that is currently in the main memory, it is
accessed immediately.
▪ If the address refers to a part of the program that is not currently in the main memory, it is
first transferred to the main memory before it can be used.
54
•Memory management unit (MMU)
Processor
translates
virtual addresses into physical addresses.
Virtual address •If the desired data or instructions are in
the
Data MMU main memory they are fetched as
described
Physical address previously.
•If the desired data or instructions are not
Cache in
the main memory, they must be
Data Physical address transferred
from secondary storage to the main
Main memory memory.
•MMU causes the operating system to
DMA transfer bring
the data from the secondary storage into
Disk storage the
55 main memory.
Assume that program and data are composed of
fixed-length units called pages.
A page consists of a block of words that occupy
contiguous locations in the main memory.
Page is a basic unit of information that is
transferred between secondary storage and
main memory.
Size of a page commonly ranges from 2K to 16K
bytes.
▪ Pages should not be too small, because the access time of a secondary storage
device is much larger than the main memory.
▪ Pages should not be too large, else a large portion of the page may not be used,
and it will occupy valuable space in the main memory.
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Concepts of virtual memory are similar to the
concepts of cache memory.
Cache memory:
▪ Introduced to bridge the speed gap between the processor and the main
memory.
▪ Implemented in hardware.
Virtual memory:
▪ Introduced to bridge the space gap between the main memory and secondary
storage.
▪ Implemented in part by software.
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Each virtual or logical address generated by a
processor is interpreted as a virtual page number
(high-order bits) plus an offset (low-order bits) that
specifies the location of a particular byte within that
page.
Information about the main memory location of each
page is kept in the page table.
▪ Main memory address where the page is stored.
▪ Current status of the page.
Area of the main memory that can hold a page is
called as page frame.
Starting address of the page table is kept in a page
table base register.
58
Virtual page number generated by the
processor is added to the contents of the
page table base register.
▪ This provides the address of the corresponding entry in the page table.
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PTBR holds Virtual address from processor
Page table base register
the address of
the page table. Page table address Virtual page number Offset
Virtual address is
interpreted as page
+ number and offset.
PAGE TABLE
PTBR + virtual
page number provide
the entry of the page This entry has the starting location
in the page table. of the page.
61
Other control bits for various other types of
restrictions that may be imposed.
▪ For example, a program may only have read permission for a page, but not
write or modify permissions.
62
Where should the page table be located?
Recall that the page table is used by the MMU for
every read and write access to the memory.
▪ Ideal location for the page table is within the MMU.
Page table is quite large.
MMU is implemented as part of the processor chip.
Impossible to include a complete page table on the
chip.
Page table is kept in the main memory.
A copy of a small portion of the page table can be
accommodated within the MMU.
▪ Portion consists of page table entries that correspond to the most recently
accessed pages.
63
A small cache called as Translation Lookaside
Buffer (TLB) is included in the MMU.
▪ TLB holds page table entries of the most recently accessed pages.
Recall that cache memory holds most recently
accessed blocks from the main memory.
▪ Operation of the TLB and page table in the main memory is similar to the
operation of the cache and main memory.
Page table entry for a page includes:
▪ Address of the page frame where the page resides in the main memory.
▪ Some control bits.
In addition to the above for each page, TLB must
hold the virtual page number for each page.
64
Virtual address from processor
Associative-mapped TLB
Virtual page number Offset High-order bits of the virtual address
generated by the processor select the
virtual page.
TLB
These bits are compared to the virtual
Virtual page
number
Control
bits
Page frame
in memory page numbers in the TLB.
If there is a match, a hit occurs and
the corresponding address of the page
frame is read.
No
If there is no match, a miss occurs
=?
and the page table within the main
Yes
memory must be consulted.
Miss
Set-associative mapped TLBs are
Hit
found in commercial processors.
66
What happens if a program generates an
access to a page that is not in the main
memory?
In this case, a page fault is said to occur.
▪ Whole page must be brought into the main memory from the disk, before the
execution can proceed.
Upon detecting a page fault by the MMU,
following actions occur:
▪ MMU asks the operating system to intervene by raising an exception.
▪ Processing of the active task which caused the page fault is interrupted.
▪ Control is transferred to the operating system.
▪ Operating system copies the requested page from secondary storage to the
main memory.
▪ Once the page is copied, control is returned to the task which was
interrupted.
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Servicing of a page fault requires transferring
the requested page from secondary storage
to the main memory.
This transfer may incur a long delay.
While the page is being transferred the
operating system may:
▪ Suspend the execution of the task that caused the page fault.
▪ Begin execution of another task whose pages are in the main memory.
68
How to ensure that the interrupted task can
continue correctly when it resumes
execution?
There are two possibilities:
▪ Execution of the interrupted task must continue from the point where it was
interrupted.
▪ The instruction must be restarted.
69
When a new page is to be brought into the main
memory from secondary storage, the main memory
may be full.
▪ Some page from the main memory must be replaced with this new page.
How to choose which page to replace?
▪ This is similar to the replacement that occurs when the cache is full.
▪ The principle of locality of reference (?) can also be applied here.
▪ A replacement strategy similar to LRU can be applied.
Since the size of the main memory is relatively larger
compared to cache, a relatively large amount of
programs and data can be held in the main memory.
▪ Minimizes the frequency of transfers between secondary storage and main memory.
70
A page may be modified during its residency in
the main memory.
When should the page be written back to the
secondary storage?
Recall that we encountered a similar problem in
the context of cache and main memory:
▪ Write-through protocol(?)
▪ Write-back protocol(?)
Write-through protocol cannot be used, since it
will incur a long delay each time a small amount
of data is written to the disk.
71
Memory Management
Operating system is concerned with transferring programs
and data between secondary storage and main memory.
Operating system needs memory routines in addition to the
other routines.
Operating system routines are assembled into a virtual
address space called system space.
System space is separate from the space in which user
application programs reside.
▪ This is user space.
Virtual address space is divided into one
system space + several user spaces.
Recall that the Memory Management Unit (MMU) translates
logical or virtual addresses into physical addresses.
MMU uses the contents of the page table base register to
determine the address of the page table to be used in the
translation.
▪ Changing the contents of the page table base register can enable us to
use a different page table, and switch from one space to another.
At any given time, the page table base register can point to
one page table.
▪ Thus, only one page table can be used in the translation process at a
given time.
▪ Pages belonging to only one space are accessible at any
given time.
When multiple, independent user programs coexist in the
main memory, how to ensure that one program does not
modify/destroy the contents of the other?
Processor usually has two states of operation:
▪ Supervisor state.
▪ User state.
Supervisor state:
▪ Operating system routines are executed.
User state:
▪ User programs are executed.
▪ Certain privileged instructions cannot be executed in user state.
▪ These privileged instructions include the ones which change page
table base register.
▪ Prevents one user from accessing the space of other users.
Secondary Storage
Disk
Disk drive
Disk controller
Sector 0, track 1
Sector 3, track n
Sector 0, track 0
System bus
Disk controller
Pit Land
Reflection Reflection
No reflection
0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0
CPU Address
I/O address
Data
Memory write