CS203: Digital Logic Design

Module 2: Boolean Logic and minimization

Neeraj Goel
IIT Ropar
 Boolean Algebra
• Boolean variable: Two values, true/false or 1/0

• Basic operations
– AND
– OR
– NOT

Digital Logic Design:Boolean Logic and

2
Minimization.
 Boolean algebra (contd)
• Boolean function
– F = f(a, b, c, ...)
– Boolean expression – boolean variables and
operations
• Truth table
– Value of boolean function for every possible
combination of input
– Two expressions are same, if same value for all
combinations
Digital Logic Design:Boolean Logic and
3
Minimization.
 Boolean Function example
• F=AB’ + C = (A + C) (B’ + C)

Digital Logic Design:Boolean Logic and

4
Minimization.
 Basic theorems
• Operations with 0 and 1
X+0=X X +1 = 1
X.1=X X. 0 = 0
• Idempotent law
X+X=X X.X = X
• Involution law
(X’)’ = X
• Law of complementarily
X + X’ = 1 X. X’ = 0
Digital Logic Design:Boolean Logic and
5
Minimization.
 Laws of Boolean algebra
• Commutative
XY = YX X+Y = Y+X
• Associative
(XY)Z = X(YZ) = XYZ
(X+Y)+Z = X + (Y+Z) = X+Y+Z
• Distributive
X(Y+Z) = XY + XZ X + YZ = (X+Y) (X+Z)
• DeMorgan’s law
(X+Y)’ = X’Y’ (XY)’ = X’ + Y’

Digital Logic Design:Boolean Logic and

6
Minimization.
 Duality principle
• Element 0 is identity element for + operator
• Element 1 is identity element for . Operator
• Duality principle:
– Law of Boolean algebra remain same if operators
and identity elements are interchanged
• DeMorgan’s duality
– A boolean expression remain same if all variable,
operators are replaced with its dual

Digital Logic Design:Boolean Logic and

7
Minimization.
 Simplification theorems
• Uniting
XY + XY’ = X (X+Y)(X+Y’) = X

Digital Logic Design:Boolean Logic and

8
Minimization.
 Simplification theorems
• Uniting
XY + XY’ = X (X+Y)(X+Y’) = X
• Absorption
X + XY = X X(X+Y) = X

Digital Logic Design:Boolean Logic and

9
Minimization.
 Simplification theorems
• Uniting
XY + XY’ = X (X+Y)(X+Y’) = X
• Absorption
X + XY = X X(X+Y) = X
• Elimination
X + X’Y = X+Y X(X’ +Y) = XY

Digital Logic Design:Boolean Logic and

10
Minimization.
 Simplification theorems
• Uniting
XY + XY’ = X (X+Y)(X+Y’) = X
• Absorption
X + XY = X X(X+Y) = X
• Elimination
X + X’Y = X+Y X(X’ +Y) = XY
• Consensus
XY + X’Z + YZ = XY + X’Z
(X+Y)(X’+Z)(Y+Z) = (X+Y)(X’+Z)
Digital Logic Design:Boolean Logic and
11
Minimization.
 Example
• Z = A’BC + A’

• Z = [A + B’C + D + EF] [A + B’C + (D + EF)’]

Digital Logic Design:Boolean Logic and

12
Minimization.
 Summary
• Learnt about basic mathematical rules of
Boolean algebra
• Learnt to simplify Boolean expressions

Digital Logic Design:Boolean Logic and

13
Minimization.
 M2.02
Boolean Expression simplification
using Boolean Algebra

Digital Logic Design:Boolean Logic and

14
Minimization.
Two standard Boolean expressions
• Sum of products
– Example:
(A + B) CD + DE
AB’ + BCD + A’C Neither SOP/POS
A’ + B + C’ + DE
• Products of sum
– Examples
• (A + B’) (B + C + D) (A’ + C)
• A’ B C’ (D + E)

Digital Logic Design:Boolean Logic and

15
Minimization.
 Creating SOP : Multiplying out
• Example: (A + BC) (A + D + E)

Digital Logic Design:Boolean Logic and

16
Minimization.
 Creating POS: Factoring
• Example: AB’ + BCD + A’C

Digital Logic Design:Boolean Logic and

17
Minimization.
 Algebraic simplification
1. Combining terms
abc’d + abcd
ab’c + abc + a’bc

2. Eliminating terms
a’b + a’bc
a’c’ + bcd + a’bd

Digital Logic Design:Boolean Logic and

18
Minimization.
 Algebraic simplification
3. Eliminating literals
3. a’b + a’b’c’d’ + abcd’

4. Adding redundant terms to eliminate

terms/literals

Digital Logic Design:Boolean Logic and

19
Minimization.
 More examples
a’b’c’ + ab’c’ + ab’c

a’b’c’ + ab’c’ + ab’c

Digital Logic Design:Boolean Logic and

20
Minimization.
 Summary
• Boolean algebra is an effective tool to simplify
Boolean expression
• Different steps can lead to different solutions

Digital Logic Design:Boolean Logic and

21
Minimization.
 M2.03
Canonical/standard form

Digital Logic Design:Boolean Logic and

22
Minimization.
 Minimizing Boolean function
• Why to minimize
– To reduce cost and improve performance (or both)
• How
– Using boolean equations and theorems
• No systematic procedure
• Difficult to ensure that solution is optimal
– A systematic and procedural approach is required
• Convert the Boolean function to canonical form
• Minimize the function
Digital Logic Design:Boolean Logic and
23
Minimization.
 Why Canonical form
• There can be several equivalent Boolean
expressions
• For example: A + B + C
= A + BC’ + BC + B’C
= AB + AB’ + A’B + C
= ABC + A + B + C
= ABC + ABC’ + AB’C + AB’C’ + A’BC + A’B’C + A’BC’

Digital Logic Design:Boolean Logic and

24
Minimization.
 Canonical/standard form
• SOP – Sum of product
– Each term should contain all the variables
• either in normal
• or in complimented form
– If number of input parameters is N – number of
literal in each term is N
– Each product term is minterm
– It represent one row of truth table of the
expression where output is 1
Digital Logic Design:Boolean Logic and
25
Minimization.
 SOP – Canonical form
• F(a,b,c) = ab + c
= ab(c+c’) + c (a + a’) (b + b’)
= a’b’c + ab’c + a’bc + abc’ + abc
ABC F
000 0 a’b’c’ m0 F = m1 + m3 + m5 + m6 + m7
001 1 a’b’c m1 F = ∑m(1,3,5,6,7)
010 0 a’bc’ m2
011 1 a’bc m3
100 0 ab’c’ m4
101 1 ab’c m5
110 1 abc’ m6
111 1 Abc m7
Digital Logic Design:Boolean Logic and
26
Minimization.
 POS – Canonical form
• Canonical POS: Product of sum
– Each sum term should contain all variables
• Normal or complimented form
– Each sum term has N literals
– Sum term is called maxterm
– Each maxterm represents one row in truth table
where output is ‘0’

Digital Logic Design:Boolean Logic and

27
Minimization.
 POS – Canonical form
• F(a,b,c) = (a + b) (c)
= (a + b + cc’)(aa’ + bb’ + c)
= (a + b + c)(a + b + c’)(a + b + c) (a + b’ + c) (a’ + b + c)
ABC F
(a’ + b’ + c)
000 0 a+b+c M0 F = M0. M1. M2. M4, M6
001 0 a + b + c’ M1 F = ∏ M(0, 1, 2, 4, 6)
010 0 a + b’ + c M2
011 1 a + b’ + c’ M3
100 0 a’ + b + c M4
101 1 a’ + b + c’ M5
110 0 a’ + b’ + c M6
111 1 a’ + b’ + c’ M7
Digital Logic Design:Boolean Logic and
28
Minimization.
 Canonical POS and SOP form
• Canonical POS and SOP forms are
complementary
• For example
F = ∏ M(0, 1, 2, 4, 6) = ∑m(3, 5, 7)
• Also, due to DeMorgen’s law
F = ∑m(3, 5, 7) = a’bc + ab’c + abc
F’ = ∏ M(3, 5, 7) = (a + b’ + c’)(a’ + b + c’)(a’ + b’ + c’)

Digital Logic Design:Boolean Logic and

29
Minimization.
 Incompletely specified functions
• Input combinations that will never occur?
– Result is not known for them
– Are don’t care
• Example
– F = ∑m(1,2,3,6) + ∑d(7)
– F = ∏M(4,5) + ∏d(7)

Digital Logic Design:Boolean Logic and

30
Minimization.
 Boolean Expression Simplification
• Given Boolean expression in canonical
SOP/POS form
• Expression simplification by using Uniting
theorem
 XY + XY’ = X or (X + Y)(X + Y’) = X
 Y + Y’ = 1
 XY + XY’ + X’Y + X’Y’ = 1
 XYZ + XY’Z + X’YZ + X’Y’Z = Z
 XYZ + XY’Z = XZ

Digital Logic Design:Boolean Logic and

31
Minimization.
 Karnaugh Map
• Karnaugh Map offers a visual solution
• Basic idea
– Arrange minterms/maxterms in 2D/3D map, one
cell -> one minterm/maxterm
– Adjacent cell – only one variable change
– Use of gray code

Digital Logic Design:Boolean Logic and

32
Minimization.
 Karnaugh Map for 3 and 4 variables
Three Variable K-Map for minterms Four Variable K-Map for minterms

a’ a a’b’ a’b ab ab’

b’c’ 0 4 c’d’ 0 4 12 8
b’c 1 5
c’d 1 5 13 9
bc 3 7
bc’ 2 6 cd 3 7 15 11

cd’ 2 6 14 10

Digital Logic Design:Boolean Logic and

33
Minimization.
 Karnaugh Map for 3 and 4 variables
Three Variable K-Map for minterms Four Variable K-Map for minterms

a’ a a’b’ a’b ab ab’

b’c’ 000 100 c’d’ 0000 0100 1100 1000
b’c 001 101
bc 011 111 c’d 0001 0101 1101 1001

bc’ 010 110 cd 0011 0111 1111 1011

cd’ 0010 0110 1110 1010

•Adjacent terms can be united

•Adjacencies are rotatory in nature
•Group of 2, 4, or 8 can be formed

Digital Logic Design:Boolean Logic and

34
Minimization.
 Example 1
• Minimize F = ∑m(1,3,7)

a’ a
b’c’ 0 4 F = bc + a’c
b’c 1 5
bc 1
3 1
7
bc’ 2 6

Digital Logic Design:Boolean Logic and

35
Minimization.
 Examples
• Minimize F = ∑m(1,3,7) or F = ∏M(0,2,4,5,6)
• Minimize F(a,b,c) = abc’ + b’c + a’
• Minimize F(a,b,c) = ∑m(1,3,6,7)
– Observe consensus term
• Minimize F(a,b,c,d) = acd + a’b + d’
• Minimize F = ∑m(1,3,5,7,9) + ∑d(6,12,13)

Digital Logic Design:Boolean Logic and

36
Minimization.
 Rules for minimum expression
• Few terms
– Implicant: Any group of 1’s
– Prime implicant: If a product term can not be
combined further with other terms
– Essential prime implicant: If a min term is covered
only one prime implicant, that become essential
• Rules
1. Find all prime implicants
2. Chose all essential prime implicants
3. Chose minimum number of prime implicants that
covers the remaining terms

Digital Logic Design:Boolean Logic and

37
Minimization.
 Examples
• F(a,b,c,d)=∑m(1,3,4,5,10,11,12,13,14,15)

• F(a,b,c,d)=∑m(2,3,5,7,10,11,13,14,15)

Digital Logic Design:Boolean Logic and

38
Minimization.
M2.06 QM Method

Digital Logic Design:Boolean Logic and

39
Minimization.
 Issues with K-Maps
• Gets more complex with more number of
variables

• Can not be automated

• Solution: Tabular method: Quine-McCluskey

Digital Logic Design:Boolean Logic and

40
Minimization.
 Quine-McCluskey Method
• Procedure
– Find all the prime implicants
– Find essential prime implicants
– Find minimum number of prime implicants
required to cover all the minterms

Digital Logic Design:Boolean Logic and

41
Minimization.
 QM Methods – basic idea
• Basic principle of minimization
– XY + XY’ = X
1. Finding prime implicants phase
– Compare every pair of min-terms
• Combine a pair if only one variable differ
• Reduce comparison by grouping
• Remove redundant pair, if any
– Repeat the process for the new stage till no more
stage can be created
2. Covering phase

Digital Logic Design:Boolean Logic and

42
Minimization.
 QM method (example)
• F(a,b,c,d) = ∑m(0,1,2,5,6,7,8,9,10,14)
– Group 0
• 0 0000
– Group 1
• 1 0001
• 2 0010
• 8 1000
– Group 2
• 5 0101
• 6 0110
• 9 1001
• 10 1010
– Group 3
• 7 0111
• 14 1110
Digital Logic Design:Boolean Logic and
43
Minimization.
 Prime implicant table
Stage 1 Stage 2 Stage 3
0 0000  0,1 000-  0,1,8,9 -00- b’c’
1 0001  0,2 00-0  0,2,8,10 -0-0 b’d’
2 0010  0,8 -000  0,8,1,9 -00-
8 1000  1,5 0-01 a’c’d 0,8,2,10 -0-0
5 0101  1,9 -001  2,6,10,14 - - 10 cd’
6 0110  2,6 0-10  2,10,6,14 - - 10
9 1001  2,10 -010 
10 1010  8,9 100- 
7 0111  8,10 10-0 
14 1110  5, 7 01-1 a’bd
6,7 011- a’bc
6,14 -110 
10,14 1-10 
Digital Logic Design:Boolean Logic and
44
Minimization.
 Prime implication chart
Prime implicant 0 1 2 5 6 7 8 9 10 14
0,1,8,9 b’c’ x x x x
0,2,8,10 b’d’ x x x x
2,6,10,14 cd’ x x x x
1,5 a’c’d x x
5,7 a’bd x x
6,7 a’bc x x

F = b’c’ + cd’ + a’bd

Digital Logic Design:Boolean Logic and

45
Minimization.
 Cyclic dependencies

F(a,b,c) = ∑m(0,1,2,5,6,7)

0 1 2 5 6 7
P1 (0,1) a’b’ x x
P2 (0,2) a’c’ x x
P3 (1,5) b’c x x
P4 (2,6) bc’ x x
P5 (5,7) ac x x
P6 (6,7) ab x x

F = a’b’ + bc’ + ac

Digital Logic Design:Boolean Logic and

46
Minimization.
 Cyclic dependencies – 2nd Solution

F(a,b,c) = ∑m(0,1,2,5,6,7)

0 1 2 5 6 7
P1 (0,1) a’b’ x x
P2 (0,2) a’c’ x x
P3 (1,5) b’c x x
P4 (2,6) bc’ x x
P5 (5,7) ac x x
P6 (6,7) ab x x

F = a’c’ + b’c + ab

Digital Logic Design:Boolean Logic and

47
Minimization.
 Incompletely specified function
• Don’t care terms are treated like regular terms
while finding prime implicants
• Don’t care terms are not included in prime
implication chart
– They dont contribute to essential prime implicant
• Example
– F(a,b,c,d) = ∑m(0,1,2,8,9,10,14) + ∑d(5,6,7)

Digital Logic Design:Boolean Logic and

48
Minimization.
 Prime implication chart
Prime implicant 0 1 2 8 9 10 14
0,1,8,9 b’c’ x x x x
0,2,8,10 b’d’ x x x x
2,6,10,14 cd’ x x x
1,5 a’c’d x
5,7 a’bd
6,7 a’bc

F = b’c’ + cd’

Digital Logic Design:Boolean Logic and

49
Minimization.
 Summary
• Observations
– QM method can use used in automation
– More systematic method for two level
minimizations
– Underline approach is same, can be used
interchangably digital minimization

Digital Logic Design:Boolean Logic and

50
Minimization.
 M2.04
Basic gates and HDL

Digital Logic Design:Boolean Logic and

51
Minimization.
 Basic gates
• 2 or more input GATES
– AND, OR, XOR
– NAND, NOR, and XNOR
• One input GATE
– Buffer and Inverter/NOT

Digital Logic Design:Boolean Logic and

52
Minimization.
 XOR Gate
• 2 input Exclusive OR – Output is 1 when only one
of the input is 1.

A B Z
0 0 0
0 1 1
1 0 1
1 1 0 XOR Symbol

• Multiple input XOR gate

– Output is 1 when odd number of inputs are 1

Digital Logic Design:Boolean Logic and

53
Minimization.
 XNOR Gate
• 2 input Exclusive NOR – Output is 1 when either
none input is 1 or both inputs are 1

A B Z
0 0 1
0 1 0
1 0 0
1 1 1 XNOR Symbol

• Multiple input XNOR gate

– Output is 1 when even number of inputs are 1

Digital Logic Design:Boolean Logic and

54
Minimization.
 NAND Gate
• NAND = NOT followed by output of AND
– For example : (A . B)’

A B Z
0 0 1
0 1 1
1 0 1 NAND GATE Symbol

1 1 0

• Behaviour is generic for N input GATE

Digital Logic Design:Boolean Logic and

55
Minimization.
 NOR Gate
• NOR = NOT followed by output of OR
– For example : (A + B)’

A B Z
0 0 1
0 1 0
1 0 0 NOR GATE Symbol

1 1 0

• Behaviour is generic for N input GATE

Digital Logic Design:Boolean Logic and

56
Minimization.
 More about NAND and NOR
• X = (A + B)’ = A’ . B’
• X = (A.B)’ = A’ + B’

Digital Logic Design:Boolean Logic and

57
Minimization.
NAND and NOR as universal GATE

Not
NOT

AND OR

AND
OR
Digital Logic Design:Boolean Logic and
58
Minimization.
 Application of NAND in SOP
• For example: F = AB + AC + BC
• F = ((AB + AC + BC)’ )’ = ((AB)’ . (AC)’ . (BC)’ )’
A
A
B
B

A F A F
C
C

B
B
C
C

Digital Logic Design:Boolean Logic and

59
Minimization.
 Application of NOR in POS
• Example: F = (A + B)(A + C)(B + C)
• F = ((((A + B)(A + C)(B + C))’ )’
• F = ((A+B)’ + (A + C)’ + (B + C)’ )’
A A
B B
A A
C F C F
B B
C C

Digital Logic Design:Boolean Logic and

60
Minimization.
 Hardware description language
• Describe hardware
– Functionality/behaviour
– Delays and concurrency
• Why to model
– Simulation and verification
• Before chip design : Functional & Timing
• After chip design : fault injection and diagnostic
– Synthesis

Digital System Design 61

Typical Design Flow with HDL
Design Specification

Behaviour description Functional Verification

RTL description (HDL) Functional Verification

Logic Synthesis Netlist Timing Verification

Physical Synthesis Layout Layout Verification

Digital System Design 62

 Hardware description language
• Can represents both behaviour and structure
domain of Y chart
• Behaviour
– Describe logic expressions, behaviour statements (if-
else, loops, etc), algorithms, different data-types
• Structure
– Describe nets, ports, connections, gates, modules,
Hierarchy
– Delay

Digital System Design 63

 HDL – options
• VHDL : Strongly typed, verbose, deterministic
• Verilog: Weakly typed, concise with efficient
notations, deterministic
• System Verilog: OOP, Verilog superset
• Other domain specific HDL
– Bluespec, Chisel, Handel-C, SystemC

Digital System Design 64

 Verilog
• Module – basic unit.
• Module definition
module module_name ( port_list );
port declarations;
…
variable declaration;
…
description of behavior
endmodule

Digital System Design 65

 Half adder example
• Two inputs : A and B

A B Carry Sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

• Sum = A XOR B
• Carry = A AND B
Digital Logic Design:Boolean Logic and
66
Minimization.
Verilog example – structural model
Module
Primitives that can be used
Name
and, or, xor,
nand, nor, xnor
module half_adder(A, B, Sum, Carry);
not

input A, B; Port List

output Sum, Carry;

xor U1(Sum, A, B);

A Sum
// Sum = A XOR B; Half Adder
and U2(Carry, A, B); B Carry
// Carry = A AND B

endmodule;

Digital System Design 67

 Verilog example – dataflow model
Module
Name

module half_adder(A, B, Sum, Carry);

input A, B; Port List

output Sum, Carry;

assign Sum = A ^ B;
A Sum
// Sum = A XOR B; Half Adder
assign Carry = A & B; B Carry
// Carry = A AND B

endmodule;

Digital System Design 68

 Verilog Testbench Example
module HA_TB(); Empty ports
reg ra, rb;
wire wsum, wcarry;
half_adder ha_inst(.A(ra), .B(rb), .Sum(wsum), .Carry(wcarry));

Port binding

HA_TB

ra Sum wsum
A
Half Adder
rb B wcarry
Carry

endmodule

Digital System Design 69

 Verilog Testbench Example
module HA_TB();
reg ra, rb;
wire wsum, wcarry;
half_adder ha_inst(.A(ra), .B(rb), .Sum(wsum), .Carry(wcarry));

initial
begin
ra = 1'b0; rb = 1'b0;
#10
$display("A: %b, B: %b, Sum: %b, Carry:%b", ra, rb, wsum, wcarry);
ra = 1'b1; rb = 1'b0;
Stimulus

#10
$display("A: %b, B: %b, Sum: %b, Carry:%b", ra, rb, wsum, wcarry);
ra = 1'b0; rb = 1'b1;
#10
$display("A: %b, B: %b, Sum: %b, Carry:%b", ra, rb, wsum, wcarry);
ra = 1'b1; rb = 1'b1;
#10
$display("A: %b, B: %b, Sum: %b, Carry:%b", ra, rb, wsum, wcarry);
end
endmodule

Digital System Design 70

 How to compile/run/simulate
• Commercial tools
– Mentor’s Modelsim/Questa
– Cadence Incisive
– Synopsys – VCS
– Xilinx Vivado
• Free
– icarus (both Verilog and VHDL)
– GHDL (only for VHDL)
• Online platform
– edaplayground

Digital System Design 71

 Viewing waveforms
• Free HDL simulator does not offer GUI and
waveform view
• Waveform need to explicitly dumped, see in
waveform viewer
initial
begin
$dumpfile("ha.vcd");
$dumpvars;

end This half-adder source code is available at:

https://www.edaplayground.com/x/3Vua#

Digital System Design 72

M2.07 Conclusions

Digital Logic Design:Boolean Logic and

73
Minimization.
• Logic minimization objective
– Cost (area and delay)
– Implementation options
• Optimality

Digital Logic Design:Boolean Logic and

74
Minimization.
 Logic optimization
• Input : Boolean expression
• Output: Optimal two level logic (either SOP or
POS)
• Optimality criteria
– Minimum number of product/sum terms
– Minimum number of literals in each product/sum
term

Digital Logic Design:Boolean Logic and

75
Minimization.
 Area and Delay
• Area depends on number of inputs
• Delay
– Input / Fan-in
– Output / Fan-out
Tp = a1Fin + a2 Fin2 + a3Fout
• Transistor size is usually modified for large fan-
in gates

Digital Logic Design:Boolean Logic and

76
Minimization.
 Propagation delay

Output
Input Delay of GATE depends on
•Type of GATE
Tp •Input transition type (0->1 or 1->0)
•Output transition type
Input •Fan in and Fan-out

Output
Maximum Gate delay can be used
Time
For analysis

Propagation Delay

Digital Logic Design:Boolean Logic and

77
Minimization.
 Delay of two level logic
• For example: F = AB + AC + BC
A Delay = Max Delay stage 1 + Max delay stage 2
T1
B
Assume all inputs change at same time
A T2 F Delay
C
Input

B T3
T
C

F
Variation in delay cause glitches at output
Digital Logic Design:Boolean Logic and
Minimization.
 Impact of large fan-in
Tp = a1Fin + a2 Fin2 + a3Fout

Tp = 4 a1 + 16 a2 + a3
Tp = 2( 2 a1 + 4 a2 + a3)

For large N, square term dominate =>

Conversion to Multi-level is required to minimise delays

Digital Logic Design:Boolean Logic and

79
Minimization.
 Delay in multiple level logic
• Longest path from input to output

Digital Logic Design:Boolean Logic and

80
Minimization.
 Delays in Verilog
• Structure modelling
– and #5 a1(out, i1, i2); //fixed delay
– and #(4, 6) a1(out, i1, i2);
• //(rise time, fall time)
– and #(4, 6, 8) a1(out, i1, i2);
• //(rise time, fall time, switch off time)
– No delay means zero delay
• Dataflow modeling
– assign #10 out = in1 & in2;
– wire #10 out;

Digital Logic Design:Boolean Logic and

81
Minimization.
 Multiple output Functions
• F1(a,b,c,d) = ∑m(0,1,2,5,6,7,10)
• F2(a,b,c,d) = ∑m(4,5,9,12)
• F3(a,b,c,d) = ∑m(0,1,4,5,11,12,15)
• F4(a,b,c,d) = ∑m(2,3,6,7,15)

Solve K-map of individual functions, realize using two level logic

Digital Logic Design:Boolean Logic and

82
Minimization.
 Complexity of QM method
• Number of variables N
• Possible of min-terms = 2N – 1
• Phase 1: Finding prime implicants
– Upper limit 3N/N
• Phase 2: Covering : iterative procedure
• Complexity: Non-polynomial
• Non-optimal/approximate solution for large
number of variables
Digital Logic Design:Boolean Logic and
83
Minimization.
 Two-Level vs Multi-Level
• Two-level minimizations
– Known methods to give optimal results
– Actual delay/area may not be optimal
• Multi-level optimization
– For large number of inputs – multi-level realization
is good
– Multiple output function – area can be reduced
– No known method for optimal results

Digital Logic Design:Boolean Logic and

84
Minimization.
 Summary
• Now we know
– What is a Boolean function – how to represent it
in various forms
– How to optimize (algebra, K-map, QM)
– How to implement Boolean functions using GATES
• Type of gates, some delay characteristics
– Writing basic Verilog program

Digital Logic Design:Boolean Logic and

85
Minimization.