80x86 Architecture

The x86 architecture is an instruction set architecture (ISA) series for computer processors. Developed
by Intel Corporation, x86 architecture defines how a processor handles and executes different
instructions passed from the operating system (OS) and software programs.
The “x” in x86 denotes ISA version.
A Microprocessor is an Integrated Circuit with all the functions of a CPU however, it cannot be used
stand alone since unlike a microcontroller it has no memory or peripherals.
8086 does not have a RAM or ROM inside it. However, it has internal registers for storing
intermediate and final results and interfaces with memory located outside it through the System Bus.
In case of 8086, it is a 16-bit Integer processor in a 40 pin, Dual Inline Packaged IC.
The size of the internal registers(present within the chip) indicate how much information the processor
can operate on at a time (in this case 16-bit registers) and how it moves data around internally within
the chip, sometimes also referred to as the internal data bus.
8086 provides the programmer with 14 internal registers, each 16 bits or 2 Bytes wide.
8086 Microprocessor is an enhanced version of 8085Microprocessor that was designed by Intel in
1976. It is a 16-bit Microprocessor having 20 address lines and16 data lines that provides up to 1MB
storage. It consists of powerful instruction set, which provides operations like multiplication and
division easily.
It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum mode is
suitable for system having multiple processors and Minimum mode is suitable for system having a
single processor.
Features of 8086
 The most prominent features of a 8086 microprocessor are as follows −
 It has an instruction queue, which is capable of storing six instruction bytes from the memory
resulting in faster processing.
 It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus, and 16-bit
external data bus resulting in faster processing.
 It is available in 3 versions based on the frequency of operation −
8086 → 5MHz
8086-2 → 8MHz
(c)8086-1 → 10 MHz
 It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves performance.
 Fetch stage can prefetch up to 6 bytes of instructions and stores them in the queue.
 Execute stage executes these instructions.
 It has 256 vectored interrupts.
 It consists of 29,000 transistors.
Comparison between 8085 & 8086 Microprocessor
Size − 8085 is 8-bit microprocessor, whereas 8086 is 16-bit microprocessor.
Address Bus − 8085 has 16-bit address bus while 8086 has 20-bit address bus.
Memory − 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb of memory.
Instruction − 8085 doesn’t have an instruction queue, whereas 8086 has an instruction queue.
Pipelining − 8085 doesn’t support a pipelined architecture while 8086 supports a pipelined
architecture.
I/O − 8085 can address 2^8 = 256 I/O's, whereas 8086 can access 2^16 = 65,536 I/O's.
Cost − The cost of 8085 is low whereas that of 8086 is high.
Architecture of 8086
The following diagram depicts the architecture of a 8086 Microprocessor –

IA – 32 and IA – 64
IA-32 Architecture refers to systems based on 32-bit processors generally compatible with the Intel
Pentium® II processor, (for example, Intel® Pentium® 4 processor or Intel® Xeon® processor), or
processors from other manufacturers supporting the same instruction set, running a 32-bit operating
system.
IA-32 is the abbreviation of Intel Architecture 32bit, that is, Intel 32-bit architecture, which was first
adopted in the 80386 microprocessor introduced by Intel in 1985.

Intel® 64 Architecture refers to systems based on IA-32 architecture processors which have 64-bit
architectural extensions, for example, Intel® CoreTM2 processor family), running a 64-bit operating
system such as Microsoft Windows XP* Professional x64 Edition or Microsoft Windows Vista* x64.
IA64 is a 64-bit architecture jointly launched by Intel and Hewlett-Packard later, but it is not
compatible with the original 32-bit architecture applications, resulting in a bleak market.
Programming model
In computing, a parallel programming model is an abstraction of parallel computer architecture, with
which it is convenient to express algorithms and their composition in programs. The value of a
programming model can be judged on its generality: how well a range of different problems can be
expressed for a variety of different architectures, and its performance: how efficiently the compiled
programs can execute.
The manual of a computer processor usually includes a description of something called programmer's
model. This section normally presents the core registers of the processor, operating modes,
endianness and the instruction set.
I think the term refers to an abstract model that describes how a programmer should use the core
components of the processor to program it. But I'm not sure whether I'm right or not, so I'm looking
for a formal definition.
Parallel processing has been developed as an effective technology in modern computers to meet the
demand for higher performance, lower cost and accurate results in real-life applications. Concurrent
events are common in today’s computers due to the practice of multiprogramming, multiprocessing,
or multicomputing.
Modern computers have powerful and extensive software packages. To analyze the development of
the performance of computers, first we have to understand the basic development of hardware and
software.
Computer Development Milestones − There is two major stages of development of computer -
mechanical or electromechanical parts. Modern computers evolved after the introduction of electronic
components. High mobility electrons in electronic computers replaced the operational parts in
mechanical computers. For information transmission, electric signal which travels almost at the speed
of a light replaced mechanical gears or levers.
Elements of Modern computers − A modern computer system consists of computer hardware,
instruction sets, application programs, system software and user interface.

The computing problems are categorized as numerical computing, logical reasoning, and transaction
processing. Some complex problems may need the combination of all the three processing modes.
Evolution of Computer Architecture − In last four decades, computer architecture has gone
through revolutionary changes. We started with Von Neumann architecture and now we have
multicomputers and multiprocessors.
Performance of a computer system − Performance of a computer system depends both on machine
capability and program behavior. Machine capability can be improved with better hardware
technology, advanced architectural features and efficient resource management. Program behavior is
unpredictable as it is dependent on application and run-time conditions
Concurrent operation of EU and BIU
8086 Microprocessor is divided into two functional units, i.e., EU (Execution Unit) and BIU (Bus
Interface Unit).
EU (Execution Unit)
Execution unit gives instructions to BIU stating from where to fetch the data and then decode and
execute those instructions. Its function is to control operations on data using the instruction decoder
& ALU. EU has no direct connection with system buses as shown in the above figure, it performs
operations over data through BIU.
Let us now discuss the functional parts of 8086 microprocessors.
ALU
It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.
Flag Register
It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status according to the result
stored in the accumulator. It has 9 flags and they are divided into 2 groups − Conditional Flags and
Control Flags.
Conditional Flags
It represents the result of the last arithmetic or logical instruction executed. Following is the list of
conditional flags −
Carry flag − This flag indicates an overflow condition for arithmetic operations.
Auxiliary flag − When an operation is performed at ALU, it results in a carry/barrow from lower
nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), then this flag is set, i.e. carry given by D3 bit to
D4 is AF flag. The processor uses this flag to perform binary to BCD conversion.
Parity flag − This flag is used to indicate the parity of the result, i.e. when the lower order 8-bits of
the result contains even number of 1’s, then the Parity Flag is set. For odd number of 1’s, the Parity
Flag is reset.
Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is zero else it is set
to 0.
Sign flag − This flag holds the sign of the result, i.e. when the result of the operation is negative, then
the sign flag is set to 1 else set to 0.
Overflow flag − This flag represents the result when the system capacity is exceeded.
Control Flags
Control flags controls the operations of the execution unit. Following is the list of control flags −
Trap flag − It is used for single step control and allows the user to execute one instruction at a time
for debugging. If it is set, then the program can be run in a single step mode.
Interrupt flag − It is an interrupt enable/disable flag, i.e. used to allow/prohibit the interruption of a
program. It is set to 1 for interrupt enabled condition and set to 0 for interrupt disabled condition.
Direction flag − It is used in string operation. As the name suggests when it is set then string bytes
are accessed from the higher memory address to the lower memory address and vice-a-versa.
General purpose register
There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These registers
can be used individually to store 8-bit data and can be used in pairs to store 16bit data. The valid
register pairs are AH and AL, BH and BL, CH and CL, and DH and DL. It is referred to the AX, BX,
CX, and DX respectively.
AX register − It is also known as accumulator register. It is used to store operands for arithmetic
operations.
BX register − It is used as a base register. It is used to store the starting base address of the memory
area within the data segment.
CX register − It is referred to as counter. It is used in loop instruction to store the loop counter.
DX register − This register is used to hold I/O port address for I/O instruction.
Stack pointer register
It is a 16-bit register, which holds the address from the start of the segment to the memory location,
where a word was most recently stored on the stack.
BIU (Bus Interface Unit)
BIU takes care of all data and addresses transfers on the buses for the EU like sending addresses,
fetching instructions from the memory, reading data from the ports and the memory as well as writing
data to the ports and the memory. EU has no direction connection with System Buses so this is
possible with the BIU. EU and BIU are connected with the Internal Bus.
It has the following functional parts −
Instruction queue − BIU contains the instruction queue. BIU gets upto 6 bytes of next instructions
and stores them in the instruction queue. When EU executes instructions and is ready for its next
instruction, then it simply reads the instruction from this instruction queue resulting in increased
execution speed.
Fetching the next instruction while the current instruction executes is called pipelining.
Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the addresses of
instructions and data in memory, which are used by the processor to access memory locations. It also
contains 1 pointer register IP, which holds the address of the next instruction to executed by the EU.
 CS − It stands for Code Segment. It is used for addressing a memory location in the code segment
of the memory, where the executable program is stored.
 DS − It stands for Data Segment. It consists of data used by the program andis accessed in the data
segment by an offset address or the content of other register that holds the offset address.
 SS − It stands for Stack Segment. It handles memory to store data and addresses during execution.
 ES − It stands for Extra Segment. ES is additional data segment, which is used by the string to hold
the extra destination data.
Instruction pointer − It is a 16-bit register used to hold the address of the next instruction to be
executed.
Real mode addressing
Real mode is characterized by a 20-bit segmented memory address space (giving exactly 1 MB of
addressable memory) and unlimited direct software access to all addressable memory, I/O addresses
and peripheral hardware. Real mode provides no support for memory protection, multitasking, or
code privilege levels.
Real mode is a memory-addressing scheme and operating state for computer microprocessors. In real
mode, the memory that can be accessed by a program — usually random access memory (RAM) —
is not managed or buffered in any way by the hardware, software or basic input and output services
(BIOS). This means a program is able to access all reachable memory addresses, regardless of what
the memory is being used for, and must manage all aspects of reading and writing to memory
locations by itself. Several restrictions come with using real mode, including the fact that the amount
of accessible memory is limited to 1 megabyte, because the processor in this mode allows addresses
to be only 20 bits in length. From a practical perspective, computer software no longer uses real-
mode, because it was replaced by a safer, expandable, more flexible addressing mode known as
protected mode.

The central processing unit (CPU) of a computer is where real mode can be activated, and most of the
aspects of the mode actually deal with issues usually seen in applications written in assembly
language, because they are fairly atomic in nature. Processor chips that are based on the original 8086
architecture begin in real mode when powered on to be able to run programs that were written for
earlier hardware, although this often would require emulation software to be successful. Protected
mode has almost completely replaced real addressing, as of 2011, to the point where there are very
few compilers available that can even compile a program that can use real addressing and even fewer
mainstream operating systems that could run it.
Memory in real mode basically is a single, linear sequence of bytes that can be accessed freely with
an address made up of a 16 bit segment address and a 4 bit offset within the segment, making a
complete 20 bit address when combined. A program can access any point in memory and read or
write anything, regardless of what is at the location. This means that, without proper management and
knowledge, a program using real addressing mode could easily overwrite the operating system and
the system BIOS, trigger a physical hardware interrupt, or accidentally send a signal to a peripheral
device. Not only could this cause a system to freeze or crash, but it also could cause data loss or
physical damage to hardware.
As processor architecture advanced, protected mode eventually replaced real mode in almost all
software. Over time, the use of real addressing mode became unnecessary, because it was incapable
of accessing more than 1 megabyte of RAM and unable to use more than 20 bits of the system bus,
meaning it could only use a fraction of the resources available on most computers. Real addressing
also poses a significant security risk. One of the few ways to write a program that uses real
addressing mode is to use assembly language and execute the program under a special disk operating
system (DOS) that does not automatically switch to protected mode on startup.
Segmentation
The process known as segmentation is a virtual process that creates address spaces of various sizes in
a computer system, called segments. Each segment is a different virtual address space that directly
corresponds to process objects.
When a process executes, segmentation assigns related data into segments for faster processing. The
segmentation function maintains a segment table that includes physical addresses of the segment,
size, and other data.

Segmentation speeds up a computer’s information retrieval by assigning related data into a “segment
table” between the CPU and the physical memory.

The Segmentation Process

Each segment stores the processes primary function, data structures, and utilities. The CPU keeps a
segment map table for every process and memory blocks, along with segment identification and
memory locations.
The CPU generates virtual addresses for running processes. Segmentation translates the CPU-
generated virtual addresses into physical addresses that refer to a unique physical memory location.
The translation is not strictly one-to-one: different virtual addresses can map to the same physical
address.

Segmented Paging
Some modern computers use a function called segmented paging. Main memory is divided into
variably-sized segments, which are then divided into smaller fixed-size pages on disk. Each segment
contains a page table, and there are multiple page tables per process.
Each of the tables contains information on every segment page, while the segment table has
information about every segment. Segment tables are mapped to page tables, and page tables are
mapped to individual pages within a segment.
Advantages include less memory usage, more flexibility on page sizes, simplified memory allocation,
and an additional level of data access security over paging. The process does not cause external
fragmentation.

Segmentation: Advantages and Disadvantages

Segmentation Advantages
 No internal fragmentation.
 Segment tables consumes less space compared to page tables.
 Average segment sizes are larger than most page sizes, which allows segments to store more
process data.
 Less processing overhead.
 Simpler to relocate segments than to relocate contiguous address spaces on disk.
 Segment tables are smaller than page tables, and takes up less memory.
Segmentation Disadvantages
 Uses legacy technology in x86-64 servers.
 Linux only supports segmentation in 80×86 microprocessors: states that paging simplifies memory
management by using the same set of linear addresses.
 Porting Linux to different architectures is problematic because of limited segmentation support.
 Requires programmer intervention.
 Subject to serious external fragmentation.
Addressing modes of 80x86
Addressing mode indicates a way of locating data or operands.
Depending upon the data types used in the instruction and the memory addressing modes, any
instruction may belong to one or more addressing modes, or some instruction may not belong to any
of the addressing modes
Thus addressing modes describe the types of operands and the way they are accessed for executing
an instruction.
According to the flow of instruction execution, the instructions may be categorized as
–Sequential control flow instructions
–Control transfer instructions
Sequential control flow instructions are the instructions which after execution, transfer control to
the next instruction appearing immediately after it in the program.
For example, the arithmetic, logical, data transfer and processor control instructions are sequential
control flow instructions.
The control transfer instructions, on the other hand , transfer control to some predefined
address or the address somehow specified in the instruction, after their execution.
For example INT, CALL, RET and JUMP instructions fall under this category
The addressing modes for sequential and control transfer instructions are explained as
follows.
1 Immediate:
•In this type of addressing, immediate data is a part of instruction, and appears in the
form of successive byte or bytes
•Eg: MOV AX, 0005H
2 Direct:
•In the direct addressing mode, a 16-bit memory address (offset) is directly specified in
the instruction as a part of it.
•Eg: MOV AX,[5000H],
–Effective address= 10H*DS +5000H
3 Register:
•In the register addressing mode, the data is stored in a register and it is referred using
the particular register
•All the registers, except IP, may be used in this mode.
•Eg: MOV AX, BX
4 Register Indirect:
•Sometimes, the address of the memory location which contains data or operand is
determined in an indirect way, using the offset registers.
•This mode of addressing is known as register indirect mode
•In this addressing mode, the offset address of data is in either BX or SI or DI register.
•The default segment is either DS or ES. The data is supposed to be available at the
address pointed to by the content of any of the above registers in the default data
segment.
•Eg: MOV AX,[BX]
–Effective address is 10H*DS+[BX]
5 Indexed:
•In this addressing mode, offset of the operand is stored in one of the Index registers.
•DS is the default segment for index registers SI and DI
•In the case of string instructions DS and ES are default segments for SI and DI
respectively.
•This mode is a special case of the above discussed register indirect addressing mode
•Eg: MOV AX,[SI]
–effective address is 10H*DS+[SI]
6 Register Relative:
•In this addressing mode, the data is available at an effective address formed by adding
an 8-bit or 16-bit displacement with the content of any one of the registers BX, BP, SI
and DI in the default (either DS or ES) segment.
•Eg: MOV AX,50H[BX]
–Effective address is 10H*DS+50H+[BX]
7 Based Indexed:
•The effective address of the data is formed, in this addressing mode, by adding the
content of a base register (any one of BX or BP) to the content of an index register (any
one of SI or DI)
•The default segment register may be DS or ES
–Eg: MOV AX,[BX][SI]
•effective address is 10H*DS +[BX]+[SI]
8 Relative Based Indexed:
•The effective address is formed by adding an 8-bit or 16-bit displacement with the sum
of contents of anyone of the base registers (BX or BP) and any one of the index registers
(SI or DI), in a default segment.
•Eg: MOV AX,50H[BX][SI]
–Effective address is 10H* DS+[BX]+[SI]+50H
•For the control transfer instructions, the addressing modes depend upon whether the
destination location is within the same segment or in a different one.
•It also depends upon the method of passing the destination address to the processor.
•Basically there are two addressing modes for the control transfer instructions, viz,
intersegment and intrasegment addressing modes.
•If the location to which the control is to be transferred lies in a different segment other
than the current one, the mode is called intersegment mode.
Instruction set of 80x86
The 8086 provides some instructions which handle string operations such as string movement,
comparison, scan, load and store.
The following instructions come under this category:
Instruction Description
MOVS/MOVSB/MOVSW Moves 8-bit or 16-bit data from the memory location(s) addressed
by SI register to the memory location addressed by DI register.
CMPS/CMPSB/CMPSW Compares the content of memory location addressed by DI
register with the content of memory location addressed by SI
register.
SCAS/SCASB/SCASW Compares the content of accumulator with the content of memory
location addressed by DI register in the extra segment ES.
LODS/LODSB/LODSW Loads 8-bit or 16-bit data from memory location addressed by SI
register into AL or AX register.
STOS/STOSB/STOSW Stores 8-bit or 16-bit data from AL or AX register in the memory
location addressed by DI register.
REP Repeats the given instruction until CX ≠ 0
REPE/ REPZ Repeats the given instruction till CX ≠ 0 and ZF = 1
REPNE/REPNZ Repeats the given instruction till CX ≠ 0 and ZF = 0