Government of Gujarat

L. D. College of Engineering

LABORATORY MANUAL
Information Technology Department

Semester IV

3140707 -Computer Organization and Architecture

Year 2024-25

Name : LATHIYA VED BIPINBHAI

Enrollment No. : 230280116064
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Government of Gujarat
L. D. College of Engineering

This is to certify that Mr. LATHIYA VED BIPINBHAI

Enrollment No. 230280116064 of Semester IV

Information Technology has successfully completed the

prescribed term work/laboratory work of Computer

Organization and Architecture (3140707) course within

the four walls of L. D. College of Engineering. This is

required as a partial fulfillment of the said course of

Gujarat Technological University.

Date:

Course In-Charge HOD

 230280116043

Government of Gujarat
L. D. College of Engineering

Exp. Page Initial of Course

Title Date
No. No. In-charge
1 Design the circuit of Half Adder and Half
Subtractor.

2 Design the circuit of Full Adder and Full

Subtractor.

3 Design the circuit of 4-bit Parallel Binary Adder.

4 Design the circuit of 4-bit adder-subtractor.

5 Design the circuit of 4-bit binary incrementer and

decrementer.

6 Design 4-bit Arithmetic circuit.

7 Design one stage of Logic circuit.

8 Design 4 bit combinational circuit shifter.

9 Design 4 bit Arithmetic Logic Shift Unit.

 230280116043

Government of Gujarat
L. D. College of Engineering

Exp. Page Initial of Course

Title Date
No. No. In-charge
10 Develop Assembly language program to find out
the 2’s complement of the number.

11 Develop Assembly language program to find out

the subtraction of two numbers using indirect
mode.

12 Develop Assembly language program for the

following pseudo code

SUM=0

SUM=SUM+A+B

DIF=DIF-C

SUM=SUM+DIF

13 Develop Assembly language program to add 100

numbers.

14 Develop Assembly language program to logically

OR two numbers.

15 Develop Assembly language program to multiply

two numbers by repeated addition method.
(5*4=5+5+5+5)

16 Develop Assembly language program to multiply

two positive numbers.
 230280116064

Experiment-1
AIM : Design the circuit of Half Adder and Half Subtractor.

Theory :

Half Adder :

➢ Half adder is a Combinational logic circuit with two inputs and two outputs.

➢ The half adder circuit is designed to add two single bit binary number A and B.

➢ This circuit has two outputs Sum and Carry.

Block Diagram

Truth Table

A B Sum Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1
Logical Expression

For Sum

Sum = A ⊕ B

For Carry

Carry = A · B

Circuit / Implimantation
 230280116064

Half Subtractor :

➢ Half Subtractor is a Combination circuit with two inputs and two outputs (Difference and
Borrow).

➢ It produces the difference between the two binary bits at the input and also produces an output
(Borrow) to indicate if a 1 has been borrowed.

Block Diagram

Truth Table

A B Diff Borrow

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0
Logical Expression

For Difference

Diff = A ⊕ B

For Borrow

Borrow = Ā · B
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Circuit / Implimantation
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Experiment-2
AIM : Design the circuit of Full Adder and Full Subtractor.

Theory :

Full Adder :

➢ The Full adder is a three input and two output combinational circuit.

➢ This circuit has two outputs Sum and Carry.

Block Diagram

Truth Table

A B Cin Sum Carry

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0

0 1 1 0 1
1 0 0 1 0

1 0 1 0 1
1 1 0 0 1

1 1 1 1 1
Logical Expression

For Sum

Sum = (A ⊕ B) ⊕ Cin

For Carry

Carry = A B + B Cin + A Cin

Circuit / Implimantation
 230280116064

Full Subtractor :

➢ The full subtractor is a combinational circuit with three inputs A, B, B, and two output D
and Bo.

➢ A is the 'minuend', B is 'subtrahend', B, is the 'Borrow in' produced by the previous stage, D
is the 'Difference' output and Bo is the 'Borrow output'.

Block Diagram

Truth Table

A B Bin Diff Bout

0 0 0 0 0
0 0 1 1 1

0 1 0 1 1
0 1 1 0 1

1 0 0 1 0
1 0 1 0 0

1 1 0 0 0
1 1 1 1 1
Logical Expression

For Difference

Diff = (A ⊕ B) ⊕ Bin

For Borrow

Bout = Ā Bin + Ā B + B Bin

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Circuit / Implimantation
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Experiment-3
AIM : Design the circuit of 4-bit Parallel Binary Adder.

Theory :

4-bit Parallel Binary Adder

➢ Two 4-bit binary numbers B4,B3,B2,B1 and A4, A3,A2, A1 are to be added with a carry
input C1. This can be done by cascading four full adder circuits as shown in Figure.

➢ The least significant bits A1, B1, and C1 are added to the produce sum output S1 and carry
output C2.

➢ Carry output C2 is then added to the next significant bits A2 and B2 producing sum output
S2 and carry output C3.

➢ C3 is then added to A3 and B3 and so on. Thus finally producing the four-bit sum output
S4,S3,S2,S1 and final carry output Cout.

Block Diagram
Circuit / Implimantation
 230280116064

Experiment-4
AIM : Design the circuit of 4-bit adder-subtractor.

Theory :

4-Bit Adder-Subtractor

➢ A "4-bit adder-subtractor" is a digital circuit that can perform either addition or subtraction
on two 4-bit binary numbers, using a control signal to select which operation to perform.

➢ A 4-bit Adder-Subtractor circuit performs both addition and subtraction using full adders
and XOR gates.

➢ The inputs X3, X2, X1, X0 and Y3, Y2, Y1, Y0 represents two 4-bit binary numbers, while
the control signal K determines the operation.

➢ The XOR gates modify Y based on K, making Y its complement when K=1 (for
subtraction).

➢ The full adders then compute the sum or difference, producing outputs S3,S2,S1,S0 with a
carry-out Cout.

Block Diagram
Circuit / Implimantation
 230280116064

Experiment-5
AIM : Design the circuit of 4-bit binary incrementer and decrementer.

Theory :

4-Bit Binary-Incrementer

➢ The increment micro-operation adds one binary value to the value of binary variables stored
in a register. For instance, a 4-bit register has a binary value 0110, when incremented by
one the value becomes 0111.

➢ The increment micro-operation is best implemented by a 4-bit combinational circuit

incrementer. A 4-bit combinational circuit incrementer can be represented by the following
block diagram.

➢ A logic-1 is applied to one of the inputs of least significant half-adder, and the other input is
connected to the least significant bit of the number to be incremented.

➢ The output carry from one half-adder is connected to one of the inputs of the next-higher-
order half-adder.

➢ The binary incrementer circuit receives the four bits from A0 through A3, adds one to it,
and generates the incremented output in S0 through S3.

➢ The output carry C4 will be 1 only after incrementing binary 1111.

Block Diagram

Circuit / Implimantation
 230280116064

4-Bit Binary-Decrementer

A 4-bit binary decrementer is a combinational circuit that subtracts 1 from a 4-bit input.

➢ Function: Takes a 4-bit input (A3 A2 A1 A0) and outputs (D3 D2 D1 D0) = Input - 1.

➢ Implementation: Can be designed using full subtractors, a 4-bit adder with two’s
complement (-1), or logic gates (XOR, AND, NOT).

➢ Borrow Propagation: The least significant bit (A0) flips, and borrow propagates until a '0'
is encountered.

➢ Usage: Used in counters, arithmetic circuits, and digital systems for decrement operations.

Block Diagram
Circuit / Implimantation
 230280116064

Experiment-6
AIM : Design 4-bit Arithmetic circuit.

Theory :

4-Bit Arithmetic Circuit

➢ The arithmetic micro-operations can be implemented in one composite arithmetic circuit.

➢ The basic component is the parallel adder.

➢ By controlling the data inputs to the adder, different types of arithmetic operations can be
obtained.

Block Diagram
 When S1S0 = 00

If Cin = 0 then D = A + B; Add

If Cin = 1 then D = A + B + 1; Add with carry

When S1S0 = 01

If Cin = 0 then D = A + B (with bar over B); Subtract with borrow

If Cin = 1 then D = A + B (with bar over B) + 1; A + 2's complement of B i.e. A – B

When S1S0 = 10

• Input B is neglected and all 0's are inserted to Y inputs D = A + 0 + Cin

If Cin = 0 then D = A; Transfer A
If Cin = 1 then D = A + 1; Increment A

When S1S0 = 11

• Input B is neglected and all 1's are inserted to Y inputs D = A - 1 + Cin

If Cin = 0 then D = A - 1; 2's complement 1
If Cin = 1 then D = A; Transfer A
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Circuit / Implimantation
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Experiment-7
AIM : Design one stage of Logic circuit.

Theory :

One Stage Of Logic Circuit

➢ A one-stage logic circuit, often used in arithmetic-logic units (ALUs), uses a multiplexer
and logic gates (like AND, OR, XOR) to perform basic logic operations on a single bit, with
selection inputs determining the operation.

Block Diagram
Circuit / Implimantation
 230280116064

Experiment-8
AIM : Design 4 bit combinational circuit shifter.

Theory :

4-Bit Combinational Circuit

➢ A 4-bit combinational circuit shifter is a digital circuit that shifts a 4-bit binary input by a
specified number of positions, producing a 4-bit output.

Inputs:
• A3, A2, A1, A0: These represent the 4 bits of the input data that will be shifted.
• Select (S): This is the control signal that determines the shift direction.
o S = 0: Shift Right.
o S = 1: Shift Left.
• IR (Input Right): This input provides the bit that will be shifted into the leftmost position during a
right shift.
• IL (Input Left): This input provides the bit that will be shifted into the rightmost position during a
left shift.

Outputs:

• H3, H2, H1, H0: These represent the 4 bits of the shifted output.

Operation:

• Shift Right (S = 0):

o The data bits are shifted one position to the right.
o The rightmost bit (A0) is lost.
o The leftmost bit (H3) is replaced by the value of IR.
o The other bits are shifted down: H2 = A3, H1 = A2, H0 = A1.
• Shift Left (S = 1):
o The data bits are shifted one position to the left.
o The leftmost bit (A3) is lost.
o The rightmost bit (H0) is replaced by the value of IL.
o The other bits are shifted up: H3 = A2, H2 = A1, H1 = A0.

MUX Implementation:
• Each MUX in the circuit is responsible for selecting the correct input to produce one bit of the
output.
• The "Select" signal (S) is connected to the select input of all the MUXes.
• The data inputs of each MUX are connected to the appropriate input bits to implement the shift
operation.
Block Diagram
 230280116064

Circuit / Implimantation
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Experiment-9
AIM : Design 4 bit Arithmetic Logic Shift Unit.

Theory :

4 bit Arithmetic Logic Shift Unit.

➢ Instead of having individual registers performing the micro operations directly, computer
systems employ a number of storage registers connected to a common operational unit
called an arithmetic logic unit, abbreviated ALU.

➢ To perform a microoperation, the contents of specified registers are placed in the inputs of
the common ALU.

➢ The ALU performs an operation and the result of the operation is then transferred to a
destination register.

➢ The arithmetic, logic, and shift circuits introduced in previous sections can be combined
into one ALU with common selection variables.

Block Diagram
Circuit / Implimantation
 230280116064

Experiment-10
AIM : Develop Assembly language program to find out the 2’s complement of the number.

Program :

ORG 100
CLA
LDA NUM
CMA
INC
STA RESULT
HLT

NUM, DEC 5
RESULT, DEC 0
END

Memory :

Input Data : 0005

Output Data : FFFB
 230280116064

Experiment-11
AIM : Develop Assembly language program to find out the subtraction of two numbers using
indirect mode.

Program :

ORG 100

LDA PTR1 I
CMA
INC
ADD PTR2 I
STA RESULT

HLT

PTR1, HEX 200

PTR2, HEX 300
RESULT, HEX 000

ORG 200
HEX 10

ORG 300
HEX 5

END
Memory :

Input Data : 000A, 0005

Output Data : FFF5
 230280116064

Experiment-12
AIM : Develop Assembly language program for the following pseudo code
SUM=0
SUM=SUM+A+B
DIF=DIF-C
SUM=SUM+DIF

Program :

ORG 100
CLA
STA SUM

LDA A
ADD B
ADD SUM
STA SUM

LDA DIF
CMA
INC
ADD C
STA DIF

LDA SUM
ADD DIF
STA SUM

HLT

A, DEC 10
B, DEC 5
C, DEC 3
DIF, DEC 8
SUM, HEX 0

END
Memory :

Input Data : 000A, 0005, 0003, 0008

Output Data : FFFB, 000A
 230280116064

Experiment-13
AIM : Develop Assembly language program to add 100 numbers.

Program :

ORG 100

LDA ADS
STA PTR
LDA NBR
STA CTR
CLA

LOP, ADD PTR I

ISZ PTR
ISZ CTR
BUN LOP
STA SUM

HLT

ADS, HEX 150

PTR, HEX 0
NBR, DEC -100
CTR, HEX 0
SUM, HEX 0

ORG 150

DEC 2
DEC 4
DEC 6
DEC 8
DEC 10
DEC 12
DEC 14
DEC 16
DEC 18
DEC 20
DEC 22
DEC 24
DEC 26
DEC 28
DEC 30
DEC 32
DEC 34
DEC 36
DEC 38
DEC 40
DEC 42
DEC 44
DEC 46
DEC 48
DEC 50
DEC 52
DEC 54
DEC 56
DEC 58
DEC 60
DEC 62
DEC 64
DEC 66
DEC 68
DEC 70
DEC 72
DEC 74
DEC 76
DEC 78
DEC 80
DEC 82
DEC 84
DEC 86
DEC 88
DEC 90
DEC 92
DEC 94
DEC 96
DEC 98
DEC 100
DEC 102
DEC 104
DEC 106
DEC 108
DEC 110
DEC 112
DEC 114
DEC 116
DEC 118
DEC 120
DEC 122
DEC 124
DEC 126
 230280116064

DEC 128
DEC 130
DEC 132
DEC 134
DEC 136
DEC 138
DEC 140
DEC 142
DEC 144
DEC 146
DEC 148
DEC 150
DEC 152
DEC 154
DEC 156
DEC 158
DEC 160
DEC 162
DEC 164
DEC 166
DEC 168
DEC 170
DEC 172
DEC 174
DEC 176
DEC 178
DEC 180
DEC 182
DEC 184
DEC 186
DEC 188
DEC 190
DEC 192
DEC 194
DEC 196
DEC 198
DEC 200

END
Memory :

Input Data : 0150, 0000, FF9C

Output Data : 2774
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Experiment-14
AIM : Develop Assembly language program to logically OR two numbers.
Program :

ORG 100

LDA NUM1
CMA
STA NNUM1

LDA NUM2
CMA
STA NNUM2

LDA NNUM1
AND NNUM2
STA RESULT

LDA RESULT
CMA
STA RESULT

HLT

NUM1, DEC 5
NUM2, DEC 3
NNUM1, DEC 0
NNUM2, DEC 0
RESULT, DEC 0

END

Memory :

Input Data : 0005, 0003

Output Data : 0007
 230280116064

Experiment-15
AIM : Develop Assembly language program to multiply two numbers by repeated addition method.
(5*4=5+5+5+5)

Program :

ORG 100

LOP, LDA X
ADD P
STA P
ISZ CTR
BUN LOP
HLT

CTR, DEC -4
X, HEX 5
P, HEX 0

END

Memory :

Input Data : 0005, 0004

Output Data : 0014
 230280116064

Experiment-16
AIM : Develop Assembly language program to multiply two numbers by repeated addition method.
(5*4=5+5+5+5)

Program :

ORG 100

LDA A
CMA
INC
STA CTR

LOP, LDA B
ADD RESULT
STA RESULT
ISZ CTR
BUN LOP
HLT

CTR, HEX 0
A, HEX 5
B, HEX 3
RESULT, HEX 0

END

Memory :

Input Data : 0005, 0003

Output Data : 000F