COMSATS University Islamabad (CUI), Lahore Campus

Department of Electrical & Computer Engineering

CPE/EEE241 – Digital Logic Design

Lab Manual for Spring 2022

Lab Resource Persons

Mr. Modassir Ishfaq

Mr. Abubakar Talha/Ms. Sidra Saleem

Theory Resource Persons

Mr.Ahmad Mudassir
Mr.Ali Mansoor Pasha
Mr.Nesrum Inallah

Supervised By
Dr. Abbas Javed

Name: __________________________ Registration Number: CIIT/ - - /LHR

Program: _______________________ Batch: _____________________________________

Semester ___________________________
Revision History

Sr. # Update Date Performed by

1 Lab Manual Updating Sep-12 Engr. M. Bilawal Rehman

Dr. Naveed Bin Rais, Dr. Umer

2 Lab Manual Review Sep-12
Farooq

3 Layout modifications Aug-14 Engr. Asif Ali

4 Lab Manual Review Aug-14 Dr. Naeem Shahzad, Dr. Naeem

Awais
5 Layout modifications Jan-15 Engr. Muzamil Ahmad

6 Lab Manual Review Jan-15 Dr. Naeem Shehzad

7 Layout modifications Sep-15 Engr. Asif Ali

Engr. Muzamil Ahmad
8 Lab Manual Review Sep-15 Dr. Kashif Imran

9 Lab Manual Update Sep-17 Engr. Arslan Khalid, Engr.

Nesruminallah
Lab Manual Update & Layout
10 Feb-20 Sarmad Hassan & Arfa Tariq
modifications

11 Lab Manual Review Feb-20 Dr. Abbas Javed

12 Lab Manual Update March-22 Abubakar Talha

|CPE/EEE 241 | Digital Logic Design Lab Manual i

Preface
Digital Logic Design is among the core courses of Electrical Engineering presenting basic tools for the design
of digital circuits. It serves as a building block in many disciplines that utilize and manipulate digital information
such as microprocessor-based systems, computer organizations and architecture, digital systems design, digital
control and digital communications etc.
This document has been prepared to serve as a laboratory manual for EEE 241 Digital Logic Design course for
electrical engineering students at CIIT Lahore. The manual consists of a set of experiments designed to allow
students to build, and verify digital circuits and systems. This set of experiments cover relevant topics prescribed
in the syllabus and are designed to reinforce the theoretical concepts taught in the classroom with practical
experience in the lab. By the end of the course, students are expected to have a good understanding of digital
logic design and its implementation using ICs for basic logic gates and simple circuits.

Acknowledgement
Contribution of the following faculty members is highly appreciated:
 Engr. Syed Junaid Akhtar
 Engr. Wajeeha Khan
 Engr. Sara Sajid
 Engr. Abdul Moeed
 Engr. Hasnain Kashif
 Engr. Arslan Khalid
 Engr. Nesruminallah

 Engr. Arfa Tariq

 Engr. Sarmad Hassan

Books
Text Books

1. Digital Design, 5th Edition by Morris Mano & Michael D. Ciletti

Reference Books

1. Introduction to Logic Design, 2nd Edition by Alan B. Marcovitz

2. Thomas L. Floyd, Digital Fundamentals (7th Edition)

|CPE/EEE 241 | Digital Logic Design Lab Manual ii

Learning Outcomes
 To get hands on experience of implementation of logic circuits using logic ICs, trainer and breadboards.
 To get familiar with the process of digital logic design (Combinational & Sequential logic)
 To be able to design digital logic circuit in application software.
 To be able to analyze the experimental results and to compare them with the theoretical
knowledge.
 Ability to implement the Boolean functions using basic as well as universal gates.
 Ability to translate real-world problem into logic equations and logic diagrams.

Theory CLOs:

1. CLO1: Comprehend the working with different number systems, Boolean algebra and mapping methods
using standard mathematical rules. (PLO1-C2)
2. CLO2: Analyze the working of combinational and sequential logic circuits using digital logic principles
and Boolean algebra. (PLO2-C4)
3. CLO3: Plan and design the combinational and sequential logic circuits using digital logic principles,
Boolean algebra and mapping methods. (PLO3-C5)

Lab CLOs:

4. CLO4: To analyze and design the combinational and sequential logic circuits using software and
hardware platforms. (PLO3-C5)
5. CLO5: Follow the software and hardware tools to reproduce the response of the digital logic circuits
using software and hardware platforms. (PLO5-P3)
6. CLO6: To explain and write effective lab report of experiment performed during open ended lab. (PLO10-A3)
7. CLO7: To demonstrate the working of a digital logic circuit designed individually and by the
teamwork using software and hardware platforms. (PLO9-A3)

|CPE/EEE 241 | Digital Logic Design Lab Manual iii

 CLOs – PLOs Mapping
PLO Cognitive Affective Psychomotor Domain
Domain Domain

PLO10
PLO11
PLO12
PLO1
PLO2
PLO3
PLO4
PLO5
PLO6
PLO7
PLO8
PLO9

A1
A2
A3
A4
A5
C1
C2
C3
C4
C5
C6

P1
P2
P3
P4
P5
P6
P7
CLOs

CLO1 X X X

CLO2 X X X X X

CLO3 X X X X X X

CLO4 (LAB) X X X X X X

CLO5 (LAB) X X X X

CLO6(LAB) X X X X
CLO7(LAB) X X X X

Lab CLOs – Lab Experiment Mapping

Lab Lab 10

Lab 11

Lab 12
Lab 1

Lab 2

Lab 3

Lab 4

Lab 5

Lab 6

Lab 7

Lab 8

Lab 9

CLO

CLO5 P1 P2 P2 P3 P3 P3 P3 P3 P3 P1 P3 P3

Grading Policy
The final marks for lab would comprise of Lab Assignments(25%),Mid-Term (25%) and Lab Terminal (50%).

Mid-Term Lab Mid Term = 0.5*(Lab Mid Term) + 0.5*(average of lab evaluation of Lab 1-7)

Terminal 0.1*[(OEP marks out of 25)*2] +0.4*(Terminal Exam result out of 50) +0.25*[(average of
lab evaluation of Lab 9-12) *5] + 0.10*[(average of lab evaluation of Lab 5-8) *5] + 0.15*[(average
of lab evaluation of Lab 1-4) *5]

Lab Assignment Marks:

 Lab Assignment 1 marks = Lab evaluation marks from experiment 1-3.
 Lab Assignment 2 marks = Lab evaluation marks from experiment 4-6.
 Lab Assignment 3 marks = Lab evaluation marks from experiment 7-9.
 Lab Assignment 4 marks = Lab evaluation marks from experiment 10-12.

The minimum pass marks for both lab and theory shall be 50%. Students obtaining less than 50%
marks (in either theory or lab, or both) shall be deemed to have failed in the course. The final marks
would be computed with 75% weight to theory and 25% to lab final marks.

|CPE/EEE 241 | Digital Logic Design Lab Manual iv

List of Equipment
IC 7400 (NAND Gate), IC 7402 (NOR Gate), IC 7404 (NOT Gate), IC 7408 (AND Gate), IC 7432 (OR Gate),
IC 7447 (BCD to 7seg), IC 7486 (X-OR Gate), IC 74138 (De-multiplexer), IC 74148 (Encoder), IC 7420 (4
Input NAND GATE), IC 7474 (D Flip Flop), IC 7476 (J-K Flip Flop), IC 74147 (10 to 4 Line Encoder), IC
74139 (2 Line to 4 Decoder), IC 74153 (Dual Multiplexer 1 of 4), IC 74157 (quadruple 1 of 2 Data selector),
IC 7485 (4-Bit Comparator), IC 7495 (4-Bit Shift Register), 7483 (4-Bit Adder), Trainer Board

Software Resources
Proteus Professional 6.9

Lab Instructions
• This lab activity comprises of three parts: Pre-lab, Lab Tasks, Post Lab Tasks, Lab Report and
Conclusion and Viva session.
• The students should perform and demonstrate each lab task separately for step-wise evaluation.
• Only those tasks that are completed during the allocated lab time will be credited to the students.
• Students are however encouraged to practice on their own in spare time for enhancing their skills.

Lab Report Instructions

All questions should be answered precisely to get maximum credit. Lab report must ensure following items:
• Lab Objectives
• Methodology
• Conclusion

Laboratory Regulations and Safety Rules

The following Regulations and Safety Rules must be observed in all concerned laboratory location.
1) It is the duty of all concerned who use any electrical laboratory to take all reasonable steps to safeguard
the HEALTH and SAFETY of themselves and all other users and visitors.
2) Be sure that all equipment is properly working before using them for laboratory exercises. Any defective
equipment must be reported immediately to the Lab. Instructors or Lab. Technical Staff.
3) Students are allowed to use only the equipment provided in the experiment manual.
4) Power supply terminals connected to any circuit are only energized with the presence of the Instructor
Lab. Staff.
5) Avoid any part of your body to be connected to the energized circuit and ground.
6) Switch off the equipment and disconnect the power supplies from the circuit before leaving the
laboratory.
7) Observe cleanliness and proper laboratory housekeeping of the equipment and other related accessories.

|CPE/EEE 241 | Digital Logic Design Lab Manual v

 8) Make sure that the last connection to be made in your circuit is the power supply and first thing to be
disconnected is also the power supply.
9) Equipment should not be removed, transferred to any location without permission from the laboratory
staff.
10) Students are not allowed to use any equipment without proper orientation and actual hands on
equipment operation.
11) Smoking and drinking in the laboratory are not permitted.
All these rules and regulations are necessary precaution in Electronic Laboratory to safeguard the students,
laboratory staff, the equipment and other laboratory users.

|CPE/EEE 241 | Digital Logic Design Lab Manual vi

 Table of Contents
Revision History i

Preface ii

Acknowledgement ii

Books ii

Learning Outcomes iii

CLOs – PLOs Mapping iv

Lab CLOs – Lab Experiment Mapping iv

Grading Policy iv

List of Equipment v

Software Resources v

Lab Instructions v

Lab Report Instructions v

Laboratory Regulations and Safety Rules v

Table of Contents vii

LAB # 1: To Identify the Responses of Different Logic Gates using Hardware and Software Platforms 10

Objectives 10

Pre Lab 10
Part A -Familiarize yourself with Logic Gates 10

In- Lab 11

Post LAB: 19

LAB # 2: To Explain the Universality of NAND and NOR GATES in Order to Design Other Logic Gates 22

Objectives 22

Pre-Lab: 22

In-Lab 22

Post-Lab: 27

LAB # 3: To Show the Behaviour of Binary Adder/Subtractor and reproduce its circuit using Universal Gates 29

Objectives 29

Pre-Lab 29

Part 1 -Familiarize yourself with Half Adder & Full Adder 29

In-Lab 30
|CPE/EEE 241 | Digital Logic Design Lab Manual i
 Post-Lab: 36

LAB # 4: To Follow the Steps of BCD to Excess 3 Code Conversion and Reproduce the Results using Dedicated IC
38

Objectives 38

Pre Lab 38

Part 1 -Familiarize yourself with BDC to Excess-3 38

Part 2 -Familiarize yourself with Excess-3 to BCD 38

In Lab 38

Post Lab 40

LAB # 5: To Follow the Steps of Binary to Gray Code Conversion and Reproduce the Results using Logic Gates 42
Objectives 42

Pre Lab 42

In-Lab 43

Post Lab: 46

LAB# 6: To Show the Response of a Multiplexer/Demultiplexer and to Reproduce Adder/Subtractor using

Multiplexer 48

Objectives 48

Pre Lab 48

Part 1 -Familiarize yourself with Multiplexers 48

Part 2 -Familiarize yourself with Demultiplexers 48

In lab 48

Post Lab: 55

LAB # 7: To Show the response of Binary Comparator(s) using hardware and software tools and to Reproduce
the Comparator using dedicated IC 57

Objectives 57

Pre Lab 57

Part 1 -Familiarize yourself with Comparators 57

|CPE/EEE 241 | Digital Logic Design Lab Manual ii

 In Lab: 57

Post Lab: 60

LAB # 8: To Show the response of an Encoder/Decoder and to Reproduce the binary converters using basic logic
gates 62

Objectives 62

Pre Lab 62

Part 1 - To realize a decoder circuit using basic gates and to verify IC 74LS139 62
Part 2 - To set up and test a 7-segment static display system to display numbers 0 to 9 64

In Lab 64
Post Lab: 69

LAB # 9: Introduction to VHDL and Altera Quartus 71

Objectives 71

Pre Lab 71

In Lab 74

LAB # 10: To Identify the Response of Sequential Circuit(s) using Hardware and Software Platforms 84

Objectives 84

Pre Lab 84

In Lab 84

LAB # 11: To show the Response of Shift Registers using 7495 IC and Reproduce the shift registers using D-Flip-
Flops 92

Objectives 92

Pre Lab 92

In Lab 92

Post Lab 94

LAB # 12: To Reproduce a Synchronous Sequence Detector using hardware and software tools 96

Objectives 96
Pre Lab 96

In Lab 96

Post Lab 99

|CPE/EEE 241 | Digital Logic Design Lab Manual iii

 LAB # 1: To Identify the Responses of Different Logic Gates using
Hardware and Software Platforms
Objectives

 To identify the basic Boolean functions of logic gates

 To identify various ICs used in proteus software and to perform basic

functionality of logic gates

Pre Lab

Part A -Familiarize yourself with Logic Gates

The basic logic gates are the building blocks of more complex logic circuits. These logic gates
perform the basic Boolean functions, such as AND, OR, NAND, NOR, Inversion, Exclusive-OR,
Exclusive-NOR. The circuit symbols are shown below with their Boolean functions, and truth
Tables. It can be depicted from the given symbols that each gate has one or two binary inputs, A
and B, and one binary output, C. The small circle on the output of the circuit symbols designates
the logic complement. The AND, OR, NAND, and NOR gates can be extended to have more
than two inputs. A gate can be extended to have multiple inputs if the binary operation it
represents is commutative and associative.

These basic logic gates are implemented as small-scale integrated circuits (SSICs) or as part of
more complex medium scale (MSI) or very large-scale (VLSI) integrated circuits. Digital IC
gates are classified not only by their logic operation, but also the specific logic-circuit family to
which they belong. Each logic family has its own basic electronic circuit upon which more
complex digital circuits and functions are developed. The following logic families are the most
frequently used.

 TTL Transistor-transistor logic

 ECL Emitter-coupled logic
 MOS Metal-oxide semiconductor
 CMOS Complementary metal-oxide semiconductor

TTL and ECL are based upon bipolar transistors. TTL has a well-established popularity among
logic families. ECL is used only in systems requiring high-speed operation. MOS and CMOS,
are based on field effect transistors. They are widely used in large scale integrated circuits
because of their high component density and relatively low power consumption. CMOS logic
consumes far less power than MOS logic. There are various commercial integrated circuit chips

|CPE/EEE 241 | Digital Logic Design Lab Manual 10

available. TTL ICs are usually distinguished by numerical designation as the 5400 and 7400
series.

Read and understand pin configuration and list the truth tables of AND, OR, NOT, NAND, NOR
and XOR gates.

In- Lab

Lab Tasks-Part-A

Study and verify the truth table of logic gates

Lab Task 1:

IC 7400 NAND gate

Inputs
Output
A B

0 0

0 1

Fig: 1.1 1 0

1 1

Table: 1.1

Lab Task 2:
Inputs
IC 7408 AND gate Output
A B

0 0

0 1

1 0

Fig: 1.2
1 1

Table: 1.2

|CPE/EEE 241 | Digital Logic Design Lab Manual 11

Lab Task 3:

IC 7404 NOT gate Input

Output
A

Fig: 1.3

Table: 1.3

Lab Task 4:

Inputs
IC 7402 NOR gate Output
A B

0 0

0 1

1 0

1 1
Fig: 1.4

Table: 1.4

Lab Task 5: Inputs

Output
IC 7432 OR gate A B

0 0

0 1

1 0
1 1

Fig: 1.5

Table: 1.5

|CPE/EEE 241 | Digital Logic Design Lab Manual 12

Lab Task 6:

IC 7486 XOR gate

Inputs
Output
A B

0 0
Fig: 1.6
0 1

1 0

1 1

Table: 1.6

Part B -Familiarize yourself with PROTEUS

Proteus is a software for microprocessor simulation, schematic capture, and printed circuit
board (PCB) design. It is developed by Labcenter Electronics.

ISIS Schematic Capture - a tool for entering designs.

PROSPICE Mixed mode SPICE simulation - industry standard SPICE3F5 simulator combined
with a digital simulator.

ARES PCB Layout - PCB design system with automatic component placer, rip-up and retry
auto-router and interactive design rule checking.

VSM - Virtual System Modelling lets co-simulate embedded software for popular micro-
controllers alongside hardware design.

System Benefits

Integrated package with common user interface and fully context sensitive help. But we only use
the ISIS Schematic Capture

In Lab:

Lab Tasks-Part-B

Right click on the ISIS icon present on desktop and then open it.

|CPE/EEE 241 | Digital Logic Design Lab Manual 13

 Fig: 1.7

The window below will be shown

Fig: 1.8

Lab Task 1:

Implementation of AND gate on Proteus

Inputs
Output
A B
0 0
0 1
1 0
1 1
Fig: 1.9

Table: 1.7

Take the components From Library by pressing the tab “Library”

|CPE/EEE 241 | Digital Logic Design Lab Manual 14

 Fig: 1.10

Search the Components by names and then click OK to adding them in Devices Panel

Fig: 1.11

Connect the components and save the design by specific name

Fig: 1.12

|CPE/EEE 241 | Digital Logic Design Lab Manual 15

Press the “start” button to execute the design and verify the results

Fig: 1.13

Repeat the same procedure for the followings Gates.

Lab Task 2:

Implementation of OR gate on Proteus

Inputs
Output
A B

0 0

Fig: 1.14 0 1

1 0

1 1

Table: 1.8

|CPE/EEE 241 | Digital Logic Design Lab Manual 16

 Fig: 1.15

Lab Task 3:

Implementation of NOT gate on Proteus

Input
Output
A

1
Fig: 1.16

Table: 1.9

Fig: 1.17

|CPE/EEE 241 | Digital Logic Design Lab Manual 17

Lab Task 4:

Implementation of NAND gate on Proteus

Inputs

A B Output

0 0

0 1

Fig: 1.18
1 0

1 1

Table: 1.10

Fig: 1.19

Lab Task 5:

Inputs

A B Output

0 0

0 1

|CPE/EEE 241 | Digital Logic Design Lab Manual 18

Implementation of XOR gate on Proteus
1 0

1 1

Fig: 1.20 Table: 1.11

Fig: 1.21

Post Lab:

Draw the schematic for following logic circuit in Proteus and fill in the table. Answer the
questions at the end.

Fig: 1.22

|CPE/EEE 241 | Digital Logic Design Lab Manual 19

 A B C D F1 F2

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Table: 1.12

Post LAB:

Design XOR and XNOR circuits using AND, NOT and OR gates.

|CPE/EEE 241 | Digital Logic Design Lab Manual 20

 Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: _______________________ Date: ____________________

|CPE/EEE 241 | Digital Logic Design Lab Manual 21

 LAB # 2: To Explain the Universality of NAND and NOR GATES in
Order to Design Other Logic Gates
Objectives

 To construct various logic gates using NAND gates

 To construct various logic gates using NOR gates

Pre-Lab:

Background theory:

Digital circuits are more frequently constructed with NAND or NOR gates than with AND and
OR gates. NAND and NOR gates are easier to fabricate with electronic components and are the
basic gates used in all IC digital logic families. Because of the prominence of NAND and NOR
gates in the design of digital circuits, rules and procedures have been developed for conversion
from Boolean function given in terms of AND, OR, and NOT into equivalent NAND and NOR
logic diagram.

Read and understand the universal gates also list the truth tables of AND, OR, NOT, NAND,
NOR and XOR gates.

In-Lab

Part 1 - Implementing any logic expression by using only NAND gates

If we can show that the logical operations AND, OR, and NOT can be implemented with NAND
gates, then it can be safely assumed that any Boolean function can be implemented with NAND
gates. Figure-1 below shows such implementation: -

Procedure

 Insert the IC on the trainer’s breadboard.

 Use any one or more of the NAND gates of the IC for this experiment.

 Any one or more Logic Switches of the trainer (S1 to S9) can be used for input to the
NAND gate.

 For output indication, connect the output pin of the circuit to any one of the LEDs of the
trainer (L0 to L15).

|CPE/EEE 241 | Digital Logic Design Lab Manual 22

Lab Tasks-Part-1

Lab Task 1:

Verification of AND function

 Connect the circuit as per figure 1(a) above.

 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.

 By setting the switches to 1 and 0, verify that the output of the circuit conforms to that
of an AND gate. Record your observation in the table below

Fig: 2.1

Table: 2.1

Lab Task 2

Verification of OR function

 Connect the circuit as per Figure 1(b).

 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.

 By setting the switches to 1 and 0, verify that the output of the circuit conforms to that
of an OR gate. Record your observation in the table below

|CPE/EEE 241 | Digital Logic Design Lab Manual 23

 Fig: 2.2

Table: 2.2

Lab task 3

Verification of NOT function

 Connect the circuit as per Figure 1 (c)

 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.

 By setting the switch to 1 and 0, verify that the output of the circuit conforms to
that of a NOT gate. Record your observation in the table below

Fig: 2.3

Table: 2.3

|CPE/EEE 241 | Digital Logic Design Lab Manual 24

Part 2 - Implementing any logic expression by using only NOR gates

NOR function is the dual of the NAND function, hence all procedure and rules for NOR logic
form a dual of the corresponding procedures and rules developed for the NAND logic. Figure 2.1
below shows how NOR gates can be used to create AND, OR, and INVERTER gates.

Procedure

 Insert IC on the trainer’s bread board.

 Use any one or more of the NOR gates of the IC for this experiment.

 Any one or more Logic Switches of the trainer (S2 to S9) can be used for input to the
NOR gate.

 For output indication, connect the output pin of the circuit to any one of the LEDs of the
trainer (L0 to L15).

Lab Tasks-Part-2

Lab Task 1:

Verification of AND function

 Connect the circuit as per Figure 1 (a)

 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.

 By setting the switches to 1 and 0, verify that the output of the circuit conforms to that
of an AND gate. Record your observation in the table below

Fig: 2.4

|CPE/EEE 241 | Digital Logic Design Lab Manual 25

 Table: 2.4

Lab task 2:

Verification of OR function

 Connect the circuit as per Figure 1 (b)

 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.

 By setting the switches to 1 and 0, verify that the output of the circuit conforms to
that of an OR gate. Record your observation in the table below

Fig: 2.5

Table: 2.5

Lab task 3

Verification of NOT function

 Connect the circuit as per Figure 1 (c)

 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.

|CPE/EEE 241 | Digital Logic Design Lab Manual 26

  By setting the switch to 1 and 0, verify that the output of the circuit conforms to that of
an NOT gate. Record your observation in the table below

Fig: 2.6

Table: 2.6

Post-Lab:

1- Design NOR, XOR and XNOR gate Using NAND gate only.

2- Design NAND, XOR and XNOR gate Using NOR gate only.

|CPE/EEE 241 | Digital Logic Design Lab Manual 27

 Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: _______________________ Date: ____________________

|CPE/EEE 241 | Digital Logic Design Lab Manual 28

 LAB # 3: To Show the Behaviour of Binary Adder/Subtractor and
reproduce its circuit using Universal Gates
Objectives
 To identify basic functionality of a Binary Adder using logic gates
 To identify basic functionality of a Binary Subtractor using logic gates
 To design a binary adder using universal gates (NAND, NOR)
 To design a binary subtractor using universal gates (NAND, NOR)

Pre-Lab

Part 1 -Familiarize yourself with Half Adder & Full Adder

Half Adder

A combinational logic circuit that performs the addition of two data bits, A and B, is called a
half-adder. Addition will result in two output bits; one of which is the sum bit, S, and the other
is the carry bit, C. The Boolean functions describing the half-adder are:

S =A ⊕ B

C=AB

Full Adder

The half-adder does not take the carry bit from its previous stage into account. This carry bit
from its previous stage is called carry-in bit. A combinational logic circuit that adds two data
bits, A and B, and a carry-in bit, Cin, is called a full-adder. The Boolean functions describing the
full-adder are:

S = (x ⊕ y) ⊕ Cin

C = xy + Cin (x ⊕ y)

Half Subtractor

Subtracting a single-bit binary value B from another A (i.e. A-B) produces a difference bit D and
a borrow out bit B-out. This operation is called half subtraction and the circuit to realize it is
called a half subtractor. The Boolean functions describing the half-Subtractor are:

S =A ⊕ B

C = A’ B

|CPE/EEE 241 | Digital Logic Design Lab Manual 29

Full Subtractor

Subtracting two single-bit binary values, B, Cin from a single-bit value A produces a difference
bit D and a borrow out Br bit. This is called full subtraction. The Boolean functions describing
the full-subtractor are:

D = (x ⊕ y) ⊕ Cin

Br= A’B + A’(Cin) + B(Cin)

In-Lab

Lab Tasks-Part-1

Lab Task 1

Implement half adder by using basic gates and verify the results

Fig: 3.1

Truth Table

OUTPUTS
INPUTS
Observed Values

A B S C

0 0

0 1

1 0

1 1

Table: 3.1

|CPE/EEE 241 | Digital Logic Design Lab Manual 30

Lab Task 2:

Implement half adder by using NAND gates and verify the results

Fig: 3.2

Truth Table

OUTPUTS
INPUTS
Observed Values

A B S C

0 0

0 1

1 0

1 1

Table: 3.2

|CPE/EEE 241 | Digital Logic Design Lab Manual 31

Lab Task 3

Implement full adder by using basic gates and verify the results

Fig: 3.3

Truth Table

Table: 3.3

Lab Task 4

Implement full adder by using NAND gates and verify the results

Fig: 3.4

|CPE/EEE 241 | Digital Logic Design Lab Manual 32

Truth Table

Table: 3.4

Lab Tasks-Part-2

Lab Task 1

Implement half subtractor by using basic gates and verify the results

Fig: 3.5

Truth Table

OUTPUTS
INPUTS
Observed Values

A B D Br

|CPE/EEE 241 | Digital Logic Design Lab Manual 33

 0 0

0 1

1 0

1 1

Table: 3.5

Lab Task 2:

Implement half subtractor by using NAND gates and verify the results

Fig: 3.6

Truth Table :

Table: 3.6

Lab Task 3:

Implement full subtractor by using basic gates and verify the results

|CPE/EEE 241 | Digital Logic Design Lab Manual 34

 Fig. 3.7

Truth Table:

Table: 3.7

Lab Task 4

Implement full subtractor by using NAND gates and verify the results

|CPE/EEE 241 | Digital Logic Design Lab Manual 35

 Fig: 3.8

Truth Table

Table: 3.8

Post-Lab:

Design half adder, full adder, half subtractor and full subtractor using NOR gates.

|CPE/EEE 241 | Digital Logic Design Lab Manual 36

 Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: _______________________ Date: ____________________

|CPE/EEE 241 | Digital Logic Design Lab Manual 37

 LAB # 4: To Follow the Steps of BCD to Excess 3 Code Conversion
and Reproduce the Results using Dedicated IC
Objectives
 To understand and respond to the steps required to transform a four bit BCD to
Excess 3 code conversion.
 To reproduce the steps required to transform Excess 3 code to BCD using IC 7483

Pre Lab

Part 1 -Familiarize yourself with BDC to Excess-3

Code converter is a combinational circuit that translates the input code word into a new
corresponding word. The excess-3 code digit is obtained by adding three to the corresponding
BCD digit. To Construct a BCD-to-excess-3-code converter with a 4-bit adder feed BCD-code
to the 4-bit adder as the first operand and then feed constant 3 as the second operand.

Part 2 -Familiarize yourself with Excess-3 to BCD

To make the above mention circuit work as a excess-3 to BCD converter, we feed excess-3 code
as the first operand and then feed 2's complement of 3 as the second operand. The output is the
BCD code.

In Lab

Lab Tasks-Part-1

Lab Task 1

Use the following circuit to verify the result

Fig. 4.1

|CPE/EEE 241 | Digital Logic Design Lab Manual 38

Truth Table

Table: 4.1

Lab Tasks-Part-2

Lab Task 2:

Using the following circuit and verify the result

Fig: 4.2

|CPE/EEE 241 | Digital Logic Design Lab Manual 39

Truth Table

Table: 4.2

Post Lab

Design Excess-3 to BCD converter using NAND Gates.

|CPE/EEE 241 | Digital Logic Design Lab Manual 40

 Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: _______________________ Date: ____________________

|CPE/EEE 241 | Digital Logic Design Lab Manual 41

LAB # 5: To Follow the Steps of Binary to Gray Code Conversion and
Reproduce the Results using Logic Gates
Objectives
 To understand and respond to the steps required to transform a four bit BCD to
Gray code conversion
 To reproduce the steps required to transform Gray code to BCD using IC 7483

Pre Lab

Lab Tasks-Part-1
Binary Code to Gray Code Conversion

Boolean Expressions:

G3=B3; G2=B3 ⊕ B2
G1=B1 ⊕ B2; G0=B1 ⊕ B0

|CPE/EEE 241 | Digital Logic Design Lab Manual 42

Lab Tasks-Part-2
Gray Code to Binary Code Conversion

Boolean Expressions:

B3=G3; B2=G3 ⊕ G2
B1=G3 ⊕ G2 ⊕ G1; B0=G3 ⊕ G2 ⊕ G1 ⊕ G0

In Lab:

Lab Task 1:

Use following circuit to verify the results

Realization using XOR gates

Fig: 5.1

|CPE/EEE 241 | Digital Logic Design Lab Manual 43

Truth Table

Binary Gray
Inputs Observed Output
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Table: 5.1
Lab Task 2:

Realization using NAND gates

Fig: 5.2

|CPE/EEE 241 | Digital Logic Design Lab Manual 44

Lab Task 3:

Use following circuit to verify the results

Realization using XOR gates

Fig: 5.3
Truth Table

Gray Binary
Inputs Observed Output
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0
0 0 0 1
0 0 1 1
0 0 1 0
0 1 1 0
0 1 1 1
0 1 0 1
0 1 0 0
1 1 0 0
1 1 0 1
1 1 1 1
1 1 1 0
1 0 1 0
1 0 1 1
1 0 0 1
1 0 0 0
Table: 5.2

|CPE/EEE 241 | Digital Logic Design Lab Manual 45

Lab Task 4:
Realization using NAND gates

Fig: 5.4

Post Lab:

1. Design grey code to binary code converter using NOR gates.

2. Design binary code to grey code converter using NOR gates.

|CPE/EEE 241 | Digital Logic Design Lab Manual 46

 Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: _______________________ Date: ____________________

|CPE/EEE 241 | Digital Logic Design Lab Manual 47

 LAB: 6 To Show the Response of a Multiplexer/Demultiplexer and to
Reproduce Adder/Subtractor using Multiplexer
Objectives
 To explain the basic functionality and working of multiplexer using logic gates
 To explain the basic functionality and working of demultiplexer using logic gates
 To display the results of various applications of multiplexer using hardware and
software platforms

Pre Lab

Part 1 -Familiarize yourself with Multiplexers

Multiplexers are very useful components in digital systems. They transfer a large number of
information units over a smaller number of channels, (usually one channel) under the control of
selection signals. Multiplexer means many to one. A multiplexer is a circuit with many inputs
but only one output. By using control signals (select lines) we can select any input to the output.
Multiplexer is also called as data selector because the output bit depends on the input data bit that
is selected. The general multiplexer circuit has 2n input signals, n control/select signals and 1
output signal.

Part 2 -Familiarize yourself with Demultiplexers

De-multiplexers perform the opposite function of multiplexers. They transfer a small number of
information units over a larger number of channels under the control of selection signals. The
general de-multiplexer circuit has 1 input signal, n control/select signals and 2n output signals.
De-multiplexer circuit can also be realized using a decoder circuit with enable.

In lab

Lab Tasks-Part-1
Lab Task 1:

4:1 Multiplexer

|CPE/EEE 241 | Digital Logic Design Lab Manual 48

 Output Y= E’S1’S0’I0 + E’S1’S0I1 + E’S1S0’I2 + E’S1S0I3

Realization using NAND Gates

Fig: 6.1
Lab Task 2:

Truth Table

Enable
Select Inputs Inputs Outputs
Input
S1 S0 E I0 I1 I2 I3 Y
X X 1 X X X X
0 0 0 0 X X X
0 0 0 1 X X X
0 1 0 X 0 X X
0 1 0 X 1 X X
1 0 0 X X 0 X
1 0 0 X X 1 X
1 1 0 X X X 0
1 1 0 X X X 1

Table: 6.1
Lab Task 3:

Verify IC 74153 MUX (Dual 4:1 Multiplexer)

|CPE/EEE 241 | Digital Logic Design Lab Manual 49

 Fig: 6.2 Table: 6.2

Tasks-Part-2
Lab Task 1:

Realization using NAND Gates

Fig: 6.3
Lab Task 2:

Truth Table

Enable Data
Select Inputs Outputs
Input Input

E D S1 S0 Y3 Y2 Y1 Y0

|CPE/EEE 241 | Digital Logic Design Lab Manual 50

 1 0 X X

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1
Table: 6.3
Lab Task 3:

Verify IC 74139 DEMUX

Fig: 6.4
Truth Table

Inputs Outputs

Ea S1 S0 Y3 Y2 Y1 Y0

1 X X

0 0 0

0 0 1

0 1 0

0 1 1
Table: 6.4

|CPE/EEE 241 | Digital Logic Design Lab Manual 51

Part 3 – Applications of Multiplexers:
To set up a Half/Full Adder and Half/Full Subtractor using IC 74153.

Lab Tasks-Part-3
Lab Task 1: Half Adder using MUX:

Design:

SUM CARRY
I0 I1 I0 I1
0 1 0 1
2 3 2 3
A A’ 0 A
Circuit Diagram:

Fig: 6.5
Truth Table:

Table: 6.5

|CPE/EEE 241 | Digital Logic Design Lab Manual 52

Lab Task 2: Full Adder using MUX:

Design:

SUM

I0 I1 I2 I3
0 1 2 3
4 5 6 7
A A’ A’ A
CARRY

I0 I1 I2 I3
0 1 2 3
4 5 6 7
0 A A 1
Circuit Diagram:

Fig: 6.6
.6
Truth Table:

Table: 6.6

|CPE/EEE 241 | Digital Logic Design Lab Manual 53

Lab Task 3: Half Subtractor using MUX:

Design:

DIFFERENCE BORROW
I0 I1 I0 I1
0 1 0 1
2 3 2 3
A A’ 0 A’

Circuit Diagram:

Fig: 6.7
Truth Table:

Table: 6.7

|CPE/EEE 241 | Digital Logic Design Lab Manual 54

Lab Task 4: Full Subtractor using MUX:

Design:

Circuit Diagram:

Fig: 6.8
Truth Table:

Table: 6.8
Post Lab:
Design Half Adder and full Adder using MUX without using IC74153 (using basic gates only).

|CPE/EEE 241 | Digital Logic Design Lab Manual 55

 Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: _______________________ Date: ____________________

|CPE/EEE 241 | Digital Logic Design Lab Manual 56

 LAB # 7: To Show the response of Binary Comparator(s) using
hardware and software tools and to Reproduce the Comparator using
dedicated IC
Objectives
 To compare two input signals using logic gates
 To analyze the working of 4-bit magnitude comparator’s IC 7485

Pre Lab

Part 1 -Familiarize yourself with Comparators

Magnitude Comparator is a logical circuit, which compares two signals A and B and
generates three logical outputs, whether A > B, A = B, or A < B. IC 7485 is a high speed
4-bit magnitude comparator, which compares two 4-bit words. The A = B Input must be
held high for proper compare operation.

In Lab:

Lab Tasks-Part-1

Lab Task 1: 1-Bit Comparator

Design:

Circuit Diagram:

Fig: 7.1

|CPE/EEE 241 | Digital Logic Design Lab Manual 57

Truth Table:

Table: 7.1

Lab Task 2: 2-Bit Comparator

Design:

Circuit Diagram:

Fig: 7.2

|CPE/EEE 241 | Digital Logic Design Lab Manual 58

Truth Table:

Table: 7.2

Lab Tasks-Part-2
Lab Task 1: 4-Bit Comparator
Circuit Diagram:

Fig: 7.3

|CPE/EEE 241 | Digital Logic Design Lab Manual 59

Truth Table:

Table: 7.3

Post Lab:

Design 4-Bit comparator using basic gates.

|CPE/EEE 241 | Digital Logic Design Lab Manual 60

 Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: _______________________ Date: ____________________

|CPE/EEE 241 | Digital Logic Design Lab Manual 61

 LAB # 8: To Show the response of an Encoder/Decoder and to
Reproduce the binary converters using basic logic gates
Objectives
Part 1

 To explain the basic functionality and working of Encoder using logic gates
 To explain the basic functionality and working of decoder using logic gates
 To display the results of various applications of encoder using hardware and
software platforms
 To display the results of various applications of decoder using hardware and
software platforms

Pre Lab

Part 1 - To realize a decoder circuit using basic gates and to verify IC

74LS139
Decoder

A decoder is a combinational circuit that connects the binary information from ‘n’ input lines to
a maximum of 2n unique output lines. Decoder is also called a min-term generator/max-term
generator. A min-term generator is constructed using AND and NOT gates. The appropriate
output is indicated by logic 1 (positive logic). Max-term generator is constructed using NAND
gates. The appropriate output is indicated by logic 0 (Negative logic).

The IC 74139 accepts two binary inputs and when enable provides 4 individual active low
outputs. The device has 2 enable inputs (Two active low).

Part 2 - To set up and test a 7-segment static display system to display

numbers 0 to 9
The Light Emitting Diode (LED) finds its place in many applications in these modern electronic
fields. One of them is the Seven Segment Display. Seven-segment displays contain the
arrangement of the LEDs in “Eight” (8) passion, and a Dot (.) with a common electrode, lead
(Anode or Cathode). The purpose of arranging it in that passion is that we can make any number
out of that by switching ON and OFF the particular LED's. Here is the block diagram of the Seven
Segment LED arrangement.

The Light Emitting Diode (LED), finds its place in many applications in this modern electronic
fields. One of them is the Seven Segment Display. Seven-segment displays contain the

|CPE/EEE 241 | Digital Logic Design Lab Manual 62

arrangement of the LEDs in “Eight” (8) passion, and a Dot (.) with a common electrode, lead
(Anode or Cathode). The purpose of arranging it in that passion is that we can make any number
out of that by switching ON and OFF the particular LED's. Here is the block diagram of the Seven
Segment LED arrangement.

LED’s are basically of two types- Common Cathode (CC) -All the 8 anode legs uses only one
cathode, which is common. Common Anode (CA)-The common leg for the entire cathode is of
Anode type.

A decoder is a combinational circuit that connects the binary information from ‘n’ input lines to
a maximum of 2n unique output lines. The IC7447 is a BCD to 7-segment pattern converter. The
IC7447 takes the Binary Coded Decimal (BCD) as the input and outputs the relevant 7 segment
code.

Part 3 - To set up a circuit of Decimal-to-BCD Encoder using IC 74147 and

to design and set up a circuit of Hexadecimal-to-Binary Encoder
Encoder

An encoder performs a function that is the opposite of decoder. It receives one or more signals
in an encoded format and output a code that can be processed by another logic circuit. One of
the advantages of encoding data, or more often data addresses in computers, is that it reduces
the number of required bits to represent data or addresses. For example, if a memory has 16
different locations, in order to access these 16 different locations, 16 lines (bits) are required if
the addressing signals are in 1 out of n format. However, if we code the 16 different addresses
into a binary format, then only 4 lines (bits) are required. Such a reduction improves the speed
of information processing in digital systems.

|CPE/EEE 241 | Digital Logic Design Lab Manual 63

In Lab:

Lab Tasks-Part-1
2:4 DECODER (MIN TERM GENERATOR):
Truth Table:

Table: 8.1

Boolean Expressions:

Circuit Diagram:

Fig: 8.1

2:4 DECODER (MAX TERM GENERATOR):

TRUTH TABLE:

Table: 8.2

|CPE/EEE 241 | Digital Logic Design Lab Manual 64

CIRCUIT DIAGRAM:

Fig: 8.2

Lab Tasks-Part-2:
CIRCUIT DIAGRAM:

Fig: 9.3

|CPE/EEE 241 | Digital Logic Design Lab Manual 65

TRUTH TABLE:

Decimal
Output Logic Levels from IC 7447 to 7-
BCD Inputs segments number
display
D C B A a b c d e f g
0 0 0 0 0 0 0 0 0 0 1
0 0 0 1 1 0 0 1 1 1 1
0 0 1 0 0 0 1 0 0 1 0
0 0 1 1 0 0 0 0 1 1 0
0 1 0 0 1 0 0 1 1 0 0
0 1 0 1 0 1 0 0 1 0 0
0 1 1 0 1 1 0 0 0 0 0
0 1 1 1 0 0 0 1 1 1 1
1 0 0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 0 1 1 0 0
Table: 8.3

Lab Tasks-Part-3:

DECIMAL-TO BCD ENCODER USING IC 74147.

TRUTH TABLE

Table: 8.4

|CPE/EEE 241 | Digital Logic Design Lab Manual 66

CIRCUIT DIAGRAM:

Fig: 8.4

Octal to Binary Converter:

Fig: 8.5

|CPE/EEE 241 | Digital Logic Design Lab Manual 67

Truth Table:

Table: 8.5

HEXADECIMAL TO BINARY ENCODER

Fig: 8.6

|CPE/EEE 241 | Digital Logic Design Lab Manual 68

TRUTH TABLE

Table: 8.6

Post Lab:
Design the encoders and decoders used in Lab task-1 and Lab task-3 using NAND and NOR
Gates.

|CPE/EEE 241 | Digital Logic Design Lab Manual 69

 Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: _______________________ Date: ____________________

|CPE/EEE 241 | Digital Logic Design Lab Manual 70

 LAB # 9:
Introduction to VHDL and Altera Quartus tool with the design of
combinational circuit
Objectives

● How to program in hardware descriptive languages in general and VHDL in particular.

● How the software tool Quartus works and its interface

Pre-Lab
Part 1 -Familiarize yourself with VHDL and Quartus:
Introduction to VHDL
VHDL is a hardware description language. It described the behavior of an electronic circuit or
system, from which the physical circuit or system can then be attained (implemented). VHDL
stands for VHSIC Hardware Description Language. VHSIC is itself an abbreviation for Very
High Speed Integrated Circuits, an initiative funded by US DOD in the 1980s that led to the
creation of VHDL. VHDL is intended for circuit synthesis as well as circuit simulation. However,
though VHDL is fully simulated, not all constructs are synthesizable.

Figure 9-1 Summary of VHDL design flow

A fundamental motivation to use VHDL (or its competitor, Verilog) is that VHDL is a standard,
technology/vendor independent language, and is therefore portable and reusable. The two main
immediate applications of VHDL are in the field of Programmable Logic Devices (including
CPLDs and FPGAs) and ASICs. A final note regarding VHDL is that, contrary to regular

|CPE/EEE 241 | Digital Logic Design Lab Manual 71

 Lab Experiment | 9
computer programs which are sequential, its statements are inherently concurrent (parallel). In
VHDL, only statements placed inside a Process, Function or Procedure are executed
sequentially.

Fundamental VHDL Units:

A standalone piece of VHDL code is composed of at least three fundamental sections:

● LIBRARY declarations: Contains a list of all libraries to be used in the design. For
example: ieee, std, work, etc.
● ENTITY: Specifies the I/O pins of the circuit.
● ARCHITECTURE: Contains the proper VHDL code , which describes how the circuit
should behave (function)

A LIBRARY is a collection of commonly used pieces of code. Placing such pieces inside a library
allows them to be reused or shared by other design.
The typical structure of a library is illustrated in figure 1.2. The code is usually written in the
form of FUNCTIONS, PROCEDURES, or COMPONENTS, which are placed inside PACKAGES, and
then compiled into the destination library.

Figure 9-2 Fundamental sections of a basic VHDL code

|CPE/EEE 241 | Digital Logic Design Lab Manual 72

 Lab Experiment | 9
Entity declaration:

VHDL files are basically divided into two parts, the entity and the architecture. The entity is
basically where the circuits (in & out) ports are defined. There is a multitude of I/O ports
available, but this lab will only deal with the two most usual ones, the INput and OUTput ports.
(Other types of ports are for example the INOUT and BUFFER ports.) The entity of the circuit in
figure 1.3 should look something like below.
Please notice that comments in the code are made with a double-dash (--)

Syntax:
Figure 9-3 NAND gate using AND & NOT gate

entity entity_name is
Port declaration;
end entity_name;

For Example:
ENTITY nandgate IS
PORT(
A: IN BIT;
B: IN BIT;
Q: OUT BIT -- Note! No ‘;’ here!
);
END nandgate;

Now that we have defined the I/O interface to the rest of the world for the NAND gate, we should
move on to the architecture of the circuit.

Architecture:

The entity told us nothing about how the circuit was implemented, this is taken care of by the
architecture part of the VHDL code. The architecture of the NAND gate matching the entity
above could then be written as something like this...

Syntax:
architecture architecture_name of entity_name
architecture_declarative_part;
begin
Statements;
end architecture_name;

|CPE/EEE 241 | Digital Logic Design Lab Manual 73

 Lab Experiment | 9
For Example:

ARCHITECTURE dataflow OF nandgate IS

SIGNAL Q_prim: BIT;
BEGIN
Q_prim <= A AND B; -- The AND-operation.
Q <= NOT Q_prim; -- The inverter.
END dataflow;

Lab Tasks
Lab Task 1:

Library IEEE;
Use IEEE.STD_LOGIC_1164.all;

Entity circuit is
Port ( A, B , C: IN bit; ( IEEE standard which defines a nine-value logic type)
Y : OUT bit);
End circuit;

Architecture behavior of circuit is

Begin
Y<= (A AND B) OR (NOT C);
End behavior;

Part 2 – Familiarize yourself with Quartus Tool

Introduction to Quartus ISE:

Altera Quartus II is design software produced by Altera. Quartus II enables analysis and synthesis
of HDL designs, which enables the developer to compile their designs, perform timing analysis,
examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target
device with the programmer. Quartus includes an implementation of VHDL and Verilog for
hardware description, visual editing of logic circuits, and vector waveform simulation.

Lab Task 2: Create a New Project

1. Start the Quartus II software.

From the Windows Start Menu, select:

|CPE/EEE 241 | Digital Logic Design Lab Manual 74

 Lab Experiment | 9
All Programs → Other Apps →Altera → Quartus II 13.1 → Quartus II 13.1 (32-Bit)
2. Start the New Project Wizard.
If the opening splash screen is displayed, select: Create a New Project (New Project
Wizard), otherwise from the Quartus II Menu Bar select: File → New Project Wizard.
3. Select the Working Directory and Project Name.

Working Directory H:\Altera_Training\Lab1

Project Name Lab1

Top-Level Design Entity Lab1

Click Next to advance to page 2 of the New Project Wizard.

Note: A window may pop up stating that the chosen working directory does not exist.

Click Yes to create it

4. Click Next again as we will not be adding any preexisting design files at this time.

5. Select the family and Device Settings.

From the pull-down menu labeled Family, select Cyclone IV.

In the list of available devices, select EP4CE115F29C7N.

Click Next.

|CPE/EEE 241 | Digital Logic Design Lab Manual 75

 Lab Experiment | 9

6. Click Next again as we will not be using any third party EDA tools

7. Click Finish to complete the New Project Wizard

Task 2: Create, Add, and Compile Design Files

1. Create a new Design File.
Select: File→ New from the Menu Bar.

|CPE/EEE 241 | Digital Logic Design Lab Manual 76

 Lab Experiment | 9
Select: VHDL File from the Design Files list and click OK.

2. Copy and paste the following code into your new VHDL file, then save it by selecting
File →Save.
Name the file nandgate and click Save in the Save As dialog box.

library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

entity nandgate is
port
(
A: in std_logic;
B: in std_logic;
cout : out std_logic
);
end nandgate;

architecture behavorial of nandgate is

begin

|CPE/EEE 241 | Digital Logic Design Lab Manual 77

 Lab Experiment | 9

cout<= not (A and B);

end behavorial;

3. Now Click on Compile Design to look for errors in code

|CPE/EEE 241 | Digital Logic Design Lab Manual 78

4. Now Repeat the above whole procedure for a 4 bit adder. VHDL code is given below.
.

library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adder4a is
port (A: in std_logic_vector(3 downto 0);
B: in std_logic_vector(3 downto 0);
C: in std_logic;
sum: out std_logic_vector(3 downto 0);
cout : out std_logic);
end adder4a;
architecture behavorial of adder4a is
component bitadder is
port (A: in std_logic;
B: in std_logic;
C: in std_logic;
sum: out std_logic;
cout : out std_logic);
end component;
signal w1, w2, w3:std_logic;
begin
unit1: bitadder port map (A(0), B(0),'0',sum(0),w1);
unit2: bitadder port map (A(1), B(1), w1, sum(1), w2);
unit3: bitadder port map (A(2), B(2), w2, sum(2), w3);
unit4: bitadder port map (A(3), B(3), w3, sum(3), cout);
end behavorial;

Task 3: Simulate Design using Quartus II

1. Create a Vector Waveform File (vwf)

Click the New File icon on the Menu Bar

Select Vector Waveform File under the Verification/Debugging Files heading.

|CPE/EEE 241 | Digital Logic Design Lab Manual 79

 Lab Experiment | 9

2. Add Signals to the Waveform

Select Edit → Insert → Insert Node or Bus…to open the Insert Node or Bus window.

3. Click the Node Finder…button in the Insert Node or Bus window to open the Node
Finder window.
From the Filter drop-down menu, select Pins: all and click the List button. This will
display all the inputs and outputs to the circuit.

|CPE/EEE 241 | Digital Logic Design Lab Manual 80

 Lab Experiment | 9
Highlight all the Input Groups A, B, and Output Group Sum in the Nodes

Found window and click the right arrow to select them. Then click OK to close
the Node Finder window.

4. In the Insert Node or Bus window, change Radix to Binary. This will make it easier for
us to enter values and interpret the results.

5. Input waveforms can be drawn in different ways. The most straightforward way is to
indicate a specific time range and specify the value of a signal. To illustrate this
approach, click the mouse on the A waveform near the 0-ns point and then drag the
mouse to the 400-ns point. The selected time interval will be highlighted in blue. Press

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 Lab Experiment | 9
Ctrl + Alt + B to open the Arbitrary Value window to enter the values manually. We will
use this approach to create the waveform for B, which should change from 0 to 400 ns.

6. Leave Sum with a value of undefined (X), as values for this will be generated when the

simulation runs. Click the Save icon on the Menu bar and save the vwf file with
the filename nandgate.vwf.
7. In the Main window, select Simulation | Options and then select Quartus II Simulator.
Select OK.
8. In the Main window, select Simulation and then select Run Functional Simulation.
9. Now you should see your simulation output with the outputs defined.
Note: The file will indicate "read-only" meaning you can't edit it.

|CPE/EEE 241 | Digital Logic Design Lab Manual 82

 Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: _______________________ Date: ____________________

|CPE/EEE 241 | Digital Logic Design Lab Manual 83

 LAB # 10: To Identify the Response of Sequential Circuit(s) using
Hardware and Software Platforms
Objectives
 To describe the basic functions of sequential circuits
 To differentiate between various types of Flip Flops
 To identify various ICs used to perform basic functionality of various Flip Flops

Pre Lab

Truth Table verification of FF and conversion of one FF to another

Logic circuits that incorporate memory cells are called sequential logic circuits; their output
depends not only upon the present value of the input but also upon the previous values.
Sequential logic circuits often require a timing generator (a clock) for their operation. The latch
(flip-flop) is a basic bi-stable memory element widely used in sequential logic circuits. Usually
there are two outputs, Q and its complementary value. Some of the most widely used latches
are listed below.

SR LATCH
S-R latch consists of two cross-coupled NOR gates. An S-R flip-flop can also be design using
cross-coupled NAND gates as shown. The truth tables of the circuits are shown below. A
clocked S-R flip-flop has an additional clock input so that the S and R inputs are active only
when the clock is high. When the clock goes low, the state of flip-flop is latched and cannot
change until the clock goes high again. Therefore, the clocked S-R flip-flop is also called
“enabled” S-R flip-flop. A D latch combines the S and R inputs of an S-R latch into one input
by adding an inverter. When the clock is high, the output follows the D input, and when the
clock goes low, the state is latched.

In Lab
Lab Task 1:
S-R LATCH:

LOGIC DIAGRAM SYMBOL

Fig: 10.1

|CPE/EEE 241 | Digital Logic Design Lab Manual 84

TRUTH TABLE

Table: 10.1

Lab Task 2:
SR FLIP FLOP:

Fig: 10.2
TRUTH TABLE

Table: 10.2

Lab Task 3:
CONVERSION OF SR-FLIP FLOP TO T-FLIP FLOP (Toggle)

LOGIC DIAGRAM SYMBOL

Fig: 10.3

|CPE/EEE 241 | Digital Logic Design Lab Manual 85

 T FLIP FLOP USING IC 7476 TRUTH TABLE

Table: 10.3
Lab Task 4:

CONVERSION OF SR-FLIP FLOP TO D-FLIP FLOP

LOGIC DIAGRAM SYMBOL

Fig:10.4

D FLIP FLOP USING IC 7476 TRUTH TABLE

CLOCK D Q+ Q’
0 X
1 0
1 1

Table: 10.4

|CPE/EEE 241 | Digital Logic Design Lab Manual 86

Lab Task 5:

CONVERSION OF SR-FLIP FLOP TO JK-FLIP FLOP

Logic Diagram Truth Table

Fig: 10.5 Table: 10.5

Logic Diagram Truth Table

Table: 10.6

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Lab Task 6:

JK Master Slave FLIP FLOP

Fig: 10.6

Truth Table

Table: 10.7

|CPE/EEE 241 | Digital Logic Design Lab Manual 88

Lab Task #7 :Implementation of a Latch in VHDL

A latch is transparent when the control signal is high. The latch is simply controlled by enable bit but has
nothing to do with clock signal. However, control signal can also be clock.
Code:
--------------------------------------------
-- Simple D Latch

-- notice this difference from flip-flops

--------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
--------------------------------------------
entity D_latch is
port( data_in: in std_logic;
enable: in std_logic;
data_out: out std_logic
);
end D_latch;
--------------------------------------------

architecture behv of D_latch is

begin
-- compare this to D flipflop
process(data_in, enable)
begin
if (enable='1') then
-- no clock signal here
data_out <= data_in;
end if;
end process;
end behv;

Lab Task# 8: Implementation of D Flip-Flop in VHDL

Flip-flop is the basic component in sequential logic design. The flip-flop is unique in that it stores the
input on the clock event. The logic symbol for this flip-flop is given in fig 2.3

Figure 2.3 D-Flip Flop

|CPE/EEE 241 | Digital Logic Design Lab Manual 89

---------------------------------------------
-- we assign input signal to the output
-- at the clock rising edge
---------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use work.all;
---------------------------------------------
entity dff is
port( data_in: in std_logic;
clock: in std_logic;
data_out:out std_logic
);
end dff;
----------------------------------------------
architecture behv of dff is
begin
process(data_in, clock)
begin
-- clock rising edge
if (clock='1' and clock'event) then
data_out <= data_in;
end if;
end process;
end behv;

|CPE/EEE 241 | Digital Logic Design Lab Manual 90

 Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: _______________________ Date: ____________________

|CPE/EEE 241 | Digital Logic Design Lab Manual 91

LAB # 11: To show the Response of Shift Registers using 7495 IC and
Reproduce the shift registers using D-Flip-Flops

Objectives

1. To explain the working of a shift register using 7495 IC

2. To differentiate between the different types of shift register

Pre Lab
In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, in which the
output of each flip-flop is connected to the "data" input of the next flip-flop in the chain, resulting
in a circuit that shifts by one position the "bit array" stored in it, shifting in the data present at its
input and shifting out the last bit in the array, at each transition of the clock input.

More generally, a shift register may be multidimensional, such that it’s "data in" and stage outputs
are themselves bit arrays: this is implemented simply by running several shift registers of the
same bit-length in parallel.

Shift registers can have both parallel and serial inputs and outputs. These are often configured as
'serial-in, parallel-out' (SIPO) or as 'parallel-in, serial-out' (PISO). There are also types that have
both serial and parallel input and types with serial and parallel output. There are also
'bidirectional' shift registers which allow shifting in both directions: L→R or R→L. The serial
input and last output of a shift register can also be connected to create a 'circular shift register'.

In Lab
1. Check all the components for their working
2. Insert the appropriate IC into the IC base
3. Make connections as shown in the circuit diagram
4. Verify the Truth Table and observe the outputs

Fig: 11.1

|CPE/EEE 241 | Digital Logic Design Lab Manual 92

Lab Task 1:
SERIAL IN SERIAL OUT (SISO) (Right Shift)

Serial
Shift
i/p Pulses QA QB QC QD
Data
- -
0 t1
1 t2
0 t3
1 t4
X t5
X t6
X t7
X t8

Table: 11.1
Lab Task 2:
SERIAL IN PARALLEL OUT (SIPO)

Serial Shift
QA QB QC QD
i/p data Pulses
- -
0 t1
1 t2
0 t3
1 t4
Table: 11.2

Lab Task 3:
PARALLEL IN PARALLEL OUT (PIPO)

Clock
Shift
Input Pulses QA QB QC QD
Terminal
- -
CLK2 t1

Table: 11.3

|CPE/EEE 241 | Digital Logic Design Lab Manual 93

Lab Task 4
PARALLEL IN SERIAL OUT (PISO)

Clock
Shift
Input Pulses QA QB QC QD
Terminal
- -
CLK2 t1
CLK2 t2
0 t3
1 t4
X t5
Table: 11.4
Post Lab:

1. Design shift registers using basic gates.

2. Differentiate between different types of shift registers.

|CPE/EEE 241 | Digital Logic Design Lab Manual 94

 Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: _______________________ Date: ____________________

|CPE/EEE 241 | Digital Logic Design Lab Manual 95

 LAB # 12: To Reproduce a Synchronous Sequence Detector using
hardware and software tools
Objectives
To analyze working principle of a sequence detector

Pre Lab
A sequence detector is a sequential logic circuit that can be used to detect whether a given
sequence of bits has been received or not by a receiver. Consider, for example, a single-input
single-output sequence detector. Let the sequence to be detected be 101. Repetition is allowed in
this sequence. This means that, the circuit will give an output of I when it detects first the
sequence 101 in a series of incoming bits. Let the next two bits after the first 101 be 01. We find
that the circuit will read this as 101 and output another 1. This is because we have given
permission for repetition, and the circuit will consider the last 1 in the first 101 as a valid first 1
in the next sequence of 101.

In Lab
Procedure
1. Draw the state diagram of the state machine below and show it to the lab instructor.

2. Fill the state table.

3. Assign State numbers

4. Find simplified Expressions (State Equations) for the flip-flops

5. Draw the circuit diagram using UNIVERSAL GATES for the state machine.

State Diagram

|CPE/EEE 241 | Digital Logic Design Lab Manual 96

State Table

Present State Next State

QA QB QC Y DA DB DC
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15
Table: 12.1
For __________ For _____________

Q CY Q CY
Q AQ B 00 01 11 10 Q AQ B 00 01 11 10

00 00

01 01

11 11

10 10

For __________

|CPE/EEE 241 | Digital Logic Design Lab Manual 97

 Q CY
Q AQ B 00 01 11 10

00

01

11

10

Table: 12.2
State Equations
DA = DB =
DC =
Circuit Diagram

D Q

CLK

D Q

CLK

D Q

CLK

Fig: 12.1

|CPE/EEE 241 | Digital Logic Design Lab Manual 98

Implementation
Connect the circuit according to your design and check for the following input sequence.

Table: 12.3

Post Lab:
Design a sequence detector which to detect 110101.

|CPE/EEE 241 | Digital Logic Design Lab Manual 99

 Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: _______________________ Date: ____________________

|CPE/EEE 241 | Digital Logic Design Lab Manual 100