UNIT 4

INTERFACING
Basic Description of the 8255
 The 8255 provides 24 I/O lines which may
be individually programmed in 2 groups of
12 I/O lines and used in 3 major modes of
operation.
 These 24 I/O lines organized as three 8-bit
I/O ports labeled A, B, and C.
 The chip interfaces directly to the data bus
of the processor, allowing its function to be
programmed;
 That is, in one application a port may appear
as an output, but in another, by
reprogramming it, as an input.
Basic Description of the 8255
 Each of the ports, A or B, can be
programmed as an 8-bit input or
output port.
 Port C can be divided in half, with the
topmost or bottommost four bits
programmed as inputs or outputs.
 Individual bits of a particular port cannot
be programmed.
Pin Configuration of the 8255
 The pin configuration of the 8255 is shown in Figure 1.
◦ GND: System ground
◦ VCC: System power
◦ RESET: A high on this input clears the control register and all ports are set to
the input mode.
◦ PA7-0: Port A bits
◦ PB7-0: Port B bits
◦ PC7-0: Port C bits
◦ D7-0: A bi-directional, tri-state data bus lines, connected to the system data bus.
◦ RD’: A read input control, that is low during CPU read operations.
◦ WR’: A write input control, that is low during CPU write operations.
◦ CS’: A chip select control. A low on this input enables the 8255 to respond to
RD’ and WR’ signals. RD’ and WR’ are ignored otherwise.
◦ A1-0: Address lines which in conjunction with RD’ and WR’, control the selection
of one of the three ports or the control word registers as shown in Table 1.
Figure 1: Pin configuration of the 8255
Table 1: Selection of 8255 ports using address lines.
Block Diagram of the 8255
 The block diagram of the 8255 is shown in Figure 2.
 Data Bus Buffer:
◦ This 3-state bidirectional 8-bit buffer is used to
interface the 8255 to the system data bus.
◦ Data is transmitted or received by the buffer upon
execution of input or output instructions by the CPU.
◦ Control words and status information are also transferred
through the data bus buffer.
 Read/Write and Control Logic:
◦ The function of this block is to manage all of the internal
and external transfers of both Data and Control or Status
words.
◦ It accepts inputs from the CPU Address and Control
busses and in turn, issues commands to both of the
Control Groups.
Block Diagram of the 8255
 Group A and Group B Controls:
◦ The functional configuration of each port is programmed by
the systems software.
◦ The CPU outputs a control word to the 8255.
◦ The control word contains information such as mode, bit
set, bit reset, etc., that initializes the functional
configuration of the 82C55A.
◦ Each of the Control blocks (Group A and Group B)
accepts commands from the read/write control logic,
receives control words from the internal data bus and
issues the proper commands to its associated ports.
 Control Group A - Port A and Port C upper (C7-C4)
 Control Group B - Port B and Port C lower (C3-C0)
◦ The control word register can be both written and read as
shown in Table 1.
Block Diagram of the 8255
 Ports A, B, and C:
◦ The 8255 contains three 8-bit ports (A, B,
and C).
◦ All can be configured in a wide variety of
functional characteristics by the system
software.
Figure 2: Block diagram of the 8255
Interfacing the 8255 to the 8086 Processor
 Example 1:Show how to interface an 8255
chip to the low byte of the 8086 (D0-D7).
Assume the following I/O address ports are
used.
Step (1): Design the address decoding Port Name Port Address
A15-A12 A11-A8 A7-A4 A3 A2 A1 A0
Port A 00H
0000 0000 0000 0 0 0 0
0000 0000 0000 0 0 1 0 Port B 02H
0000 0000 0000 0 1 0 0 Port C 04H
0000 0000 0000 0 1 1 0 Control 06H
Chip Select (CS’) Port Enable
Select Even Byte
(A1 A0) (D0-D7)
Step(2): Design control logic (IOW’ & IOR’)
Figure 3: Interface of the 8255 in Example 1
Programming the 8255
 There are three basic modes of
operation that can be selected by the
system software:
◦ Mode 0: Basic input/output
◦ Mode 1: Strobed Input/output
◦ Mode 2: Bi-directional Bus
Programming the 8255
 When the reset input of the 8255 goes
"high" all ports will be set to the input
mode with all 24 port lines held at a logic
"one" level.
 After the reset is removed the 8255 can
remain in the input mode with no additional
initialization required.
 During the execution of the system
program, any of the other modes may be
selected by using a single output instruction.
 The modes for Port A and Port B can be
separately defined, while Port C is divided
into two portions.
Programming the 8255
 Figure 4 shows the format of the control
byte used to program the 8255.
 There are two types of control bytes:
◦ (a) When bit 7 = 0, a bit set/reset operation is
indicated;
◦ (b) When bit 7 = 1, any of the modes 0, 1, or 2
can be programmed.
 The ports in Group A can be programmed
for any of modes 0, 1, or 2.
 The ports in Group B can only be
programmed for modes 0 or 1.
Figure 4: The format of the control byte of the 8255.
Programming the 8255
 Example 2: Write the 80x86
initialization routine required to program
the 8255 in Figure 5 for mode 0, with
port A as an output and ports B and C
inputs
◦ The control word is formed as:
 1 00 0 1 0 1 1 = 8BH
◦ The program is as follows:
 MOV AL,8BH ;Control byte to AL
 OUT 6,AL ;Write to control port
Figure 5: Circuit design of Example 2.
Programming the 8255
 Example 3: Write an 80x86 program to
input a byte from port B of the PPI chip in
pervious example and output this byte to
port A of the same chip. Assume the chip
has been programmed as in the previous
example.

◦ The program requires two instructions.

 IN AL, 2 ; Get data from port B
 OUT 0,AL ; Output the data to port A
Operating Modes of the 8255
 The 8255A can be programmed in three modes (0, 1, 2) as
shown in Figure 6:
◦ Mode 0 (Basic I/O): three simple I/O ports.
 Ports A and B operate as either inputs or outputs.
 Port C is divided into two 4-bit groups either of which can be operated
as inputs or outputs.
◦ Mode 1 (Strobed I/O): two hand shaking I/O ports.
 Ports A and B operate as either inputs or outputs as in mode 0
 Port C is used for handshaking and control.
◦ Mode 2 (Strobed Bidirectional I/O): a bidirectional I/O
port with five hand shaking signals.
 Port A is bidirectional (both input and output).
 Port C is used for handshaking.
 Port B is not used.
 These modes can also be intermixed. For example, port A
can be programmed to operate in mode 2, while port B
operates in mode 0.
Figure 6: The three basic modes of the 8255.
Operating Modes of the 8255
Mode 0 (Basic Input / Output)
 This mode provides simple input and output
operations for each of the three ports.
 No handshaking is required, data is simply
written to or read from a specific port.
 The basic features of this mode are:
◦ Two 8-bit ports and two 4-bit ports
◦ Any Port can be input or output
◦ Outputs are latched
◦ Input are not latched
◦ 16 different input / output configurations possible
as shown in Table 2.
Table 2: Mode 0 port definition.
Operating Modes of the 8255
Mode 1 (Strobed Input / Output)
 This mode provides a means for transferring I/O data
to or from a specified port in conjunction with
strobes or “hand shaking” signals.
 In this mode, port A and port B use the lines on port
C to generate or accept these “hand shaking” signals.
 The basic features of this mode are:
◦ Two Groups (Group A and Group B).
◦ Each group contains one 8-bit port and one 4-bit
control/data port.
◦ The 8-bit data port can be either input or output.
◦ Both inputs and outputs are latched.
◦ The 4-bit port is used for control and status of the 8-bit
port.
Operating Modes of the 8255
Mode 1 (Strobed Input / Output)
 Figure 7 shows the control signals for input configuration.
 STB (Strobe Input)
◦ A “low” on this input loads data into the input latch.
 IBF (Input Buffer Full F/F)
◦ A “high” on this output indicates that the data has been loaded into
the input latch.
◦ IBF is set by STB’ input being low and is reset by the rising edge of the
RD’ input.
 INTR (Interrupt Request)
◦ A “high” on this output can be used to interrupt the CPU when and
input device is requesting service.
◦ INTR is set by the condition: STB is a “one”, IBF is a “one” and INTE is
a “one”.
◦ It is reset by the falling edge of RD.
◦ This procedure allows an input device to request service from the
CPU by simply strobing its data into the port.
 INTE A: Controlled by bit set/reset of PC4.
 INTE B: Controlled by bit set/reset of PC2.
Figure 7: Mode 1 input.
Operating Modes of the 8255
Mode 1 (Strobed Input / Output)
 Figure 8 shows the control signals for output configuration.
 OBF - Output Buffer Full F/F:
◦ The OBF’ output will go “low” to indicate that the CPU has written
data out to be specified port.
◦ The OBF’ F/F will be set by the rising edge of the WR input and reset
by ACK input being low.
 ACK - Acknowledge Input):
◦ A “low” on this input informs the 82C55A that the data from Port A
or Port B is ready to be accepted.
◦ A response from the peripheral device indicating that it is ready to
accept data
 INTR - (Interrupt Request):
◦ A “high” on this output can be used to interrupt the CPU when an
output device has accepted data transmitted by the CPU.
◦ INTR is set when ACK is a “one”, OBF is a “one” and INTE is a “one”.
◦ It is reset by the falling edge of WR.
 INTE A: Controlled by bit set/reset of PC6.
 INTE B: Controlled by bit set/reset of PC2.
Figure 8: Mode 1 output.
Operating Modes of the 8255
Mode 2 (Strobed Bidirectional Input / Output)
 This mode provides a means for communicating
with a peripheral device or structure on a single
8-bit bus for both transmitting and receiving data
(bidirectional bus I/O).
 In this mode, port A uses the lines on port C to
generate or accept these “hand shaking” signals.
 The basic features of this mode are:
◦ Used in Group A only.
◦ One 8-bit, bi-directional bus Port (Port A) and a 5-bit
control Port (Port C)
◦ Both inputs and outputs are latched.
◦ The 5-bit control port (Port C) is used for control
and status for the 8-bit, bi-directional bus port (Port
A)
Operating Modes of the 8255
Mode 2 (Strobed Bidirectional Input / Output)
 Figure 9 shows the control signals for mode
2 configurations.
 Input Operations:
◦ STB’ - (Strobe Input): A “low” on this input
loads data into the input latch.
◦ IBF - (Input Buffer Full F/F): A “high” on this
output indicates that data has been loaded into
the input latch.
◦ INTE 2 - (The INTE flip-flop associated with
IBF): Controlled by bit set/reset of PC4.
◦ INTR - (Interrupt Request): A high on this
output can be used to interrupt the CPU for
both input or output operations.
Figure 9: Mode 2 control signals.
Operating Modes of the 8255
Mode 2 (Strobed Bidirectional Input / Output)

 Input Operations:
◦ STB’ - (Strobe Input): A “low” on this input loads data into
the input latch.
◦ IBF - (Input Buffer Full F/F): A “high” on this output indicates
that data has been loaded into the input latch.
◦ INTE 2 - (The INTE flip-flop associated with IBF): Controlled
by bit set/reset of PC4.
◦ INTR - (Interrupt Request): A high on this output can be used
to interrupt the CPU for both input or output operations.
 Output Operations:
◦ OBF’ - (Output Buffer Full): The OBF output will go “low” to indicate
that the CPU has written data out to port A.
◦ ACK’ - (Acknowledge): A “low” on this input enables the three-state
output buffer of port A to send out the data. Otherwise, the
output buffer will be in the high impedance state.
◦ INTE 1 - (The INTE flip-flop associated with OBF): Controlled by bit
set/reset of PC4.
 Basic DMA concept
Direct memory access (DMA) is a feature of
modern computer systems that allows
certain hardware subsystems to read/write
data to/from memory without
microprocessor intervention, allowing the
processor to do other work.
Used in disk controllers, video/sound cards
etc, or between memory locations.
Typically, the CPU initiates DMA transfer,
does other operations while the transfer is in
progress, and receives an interrupt from the
DMA controller once the operation is
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 BASIC DMA
TERMINOLOGY
 DMA channel: system pathway used by a
device to transfer information directly to
and from memory. There are usually 8 in
a computer system
 DMA controller: dedicated hardware used
for controlling the DMA operation
 Single-cycle mode: DMA data transfer is
done one byte at a time
 Burst-mode: DMA transfer is finished when
all data has been moved 34
DMA pins and timing
 x86 Interrupt Pins
◦ HOLD: DMA request.
 Sampled in the middle of any clocking cycle
◦ HLDA: DMA acknowledge signal.
 The address, data and control buses are set to high-Z, so
the I/O devices can control the system bus

1 2 3 4 5 6 7 8 9
CLK

HOLD

HLDA

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 DMA on the 8086
Microprocessor
 The I/O device asserts the appropriate DRQ signal for the channel.
 The DMA controller will enable appropriate channel, and ask the
CPU to release the bus so that the DMA may use the bus. The DMA
requests the bus by asserting the HOLD signal which goes to the
CPU.
 The CPU detects the HOLD signal, and will complete executing the
current instruction. Now all of the signals normally generated by
the CPU are placed in a tri-stated condition (neither high or low)
and then the CPU asserts the HLDA signal which tells the DMA
controller that it is now in charge of the bus.
 The CPU may have to wait (hold cycles).
 DMA activates its -MEMR, -MEMW, -IOR, -IOW output signals,
and the address outputs from the DMA are set to the target address,
which will be used to direct the byte that is about to transferred to a
specific memory location.

36
 DMA on the 8086
Microprocessor
 The DMA will then let the device that requested the DMA transfer know
that the transfer is commencing by asserting the -DACK signal.
 The peripheral places the byte to be transferred on the bus Data lines.
 Once the data has been transferred, The DMA will de-assert the -DACK2
signal, so that the FDC knows it must stop placing data on the bus.
 The DMA will now check to see if any of the other DMA channels have
any work to do. If none of the channels have their DRQ lines asserted, the
DMA controller has completed its work and will now tri-state the -
MEMR, -MEMW, -IOR, -IOW and address signals.
 Finally, the DMA will de-assert the HOLD signal. The CPU sees this, and
de-asserts the HOLDA signal. Now the CPU resumes control of the buses
and address lines, and it resumes executing instructions and accessing
main memory and the peripherals.

37
 EXAMPLE
 Assuming that a DMA initialization has an
overhead of 10 cycles, while a CPU
transfer to/from memory requires 4
cycles (no wait states required), compare
a DMA and a CPU transfer from one
memory location to another of
◦ One byte of data
◦ A block of 1Kbytes in burst mode
◦ A block of 64Kbytes in burst mode

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 The 8237 DMA controller
Supplies memory and I/O with control
signals and addresses during DMA transfer
4-channels (expandable)
 0: DRAM refresh
 1: Free
 2: Floppy disk controller
 3: Free
1.6MByte/sec transfer rate
64 KByte section of memory address
capability with single programming
“fly-by” controller (data does not pass
through the DMA-only memory to I/O
transfer capability) 39
8237 pins
 CLK: System clock
 CS΄: Chip select (decoder output)
 RESET: Clears registers, sets mask register
 READY: 0 for inserting wait states
 HLDA: Signals that the μp has relinquished buses
 DREQ3 – DREQ0: DMA request input for each channel
 DB7-DB0: Data bus pins
 IOR΄: Bidirectional pin used during programming
and during a DMA write cycle
 IOW΄: Bidirectional pin used during programming
and during a DMA read cycle
 EOP΄: End of process is a bidirectional signal used as input to terminate a
DMA process or as output to signal the end of the DMA transfer
 A3-A0:Address pins for selecting internal registers
 A7-A4: Outputs that provide part of the DMA transfer address
 HRQ: DMA request output
 DACK3-DACK0: DMA acknowledge for each channel.
 AEN:Address enable signal
 ADSTB:Address strobe
 MEMR΄: Memory read output used in DMA read cycle
 MEMW΄: Memory write output used in DMA write cycle

40
8237 pin
Diagram

41
A 8237 DMA application

DMA ARCHITECTURE
42
 8237 registers
 CAR (Current Address Register): holds
the 16-bit memory address used for the
DMA transfer (one for each channel),
either incremented or decremented
during the operation
 CWCR (Current Word Count Register):
Programs a channel for the number of
bytes (up to 64K) transferred during a
DMA operation
 BA (Base Address) and WC (Word
43
 MR (Mode Register):

 Programs the mode of

operation for a channel (one
for each channel).

44
 MR (Mask Register):

 SR (Status Register):
Shows the status of
each DMA channel
45
8237 Software commands

46
 8237 Software commands
 Clear First/Last Flip-Flop - This command is executed prior
to writing or reading new address or word count information
to the 82C37. This command initializes the flipflop to a
known state (low byte first) so that subsequent accesses to
register contents by the microprocessor will address upper
and lower bytes in the correct sequence.
 Set First/Last Flip-Flop - This command will set the flip-flop
to select the high byte first on read and write operations to
address and word count registers.
 Master Clear - This software instruction has the same effect
as the hardware Reset. The Command, Status, Request, and
Temporary registers, and Internal First/Last Flip-Flop and
mode register counter are cleared and the Mask register is
set. The 82C37A will enter the idle cycle.
 Clear Mask Register - This command clears the mask bits of
all four channels, enabling them to accept DMA requests.
 Clear Mode Register Counter - Since only one address
location is available for reading the Mode 47 registers, an
8237 block diagram

48