shown in table.

In the chart all the specified implicants form columns a

cross is put in the row of eachprime implicant under the columns of the
implicants which it covers.

A tick mark is placed against every essential prime implicant

(which column contains a singlecross(X). the sum of essential prime
implicantsF = b’c’ + cd’

The prime implicants which covers the minterms 0,1,8,9 and

2,10,6,14 therefore in order to coverthe remaining minterms, the reduced
prime implicants chart is formed as follows.

To cover the minterms the prime implicants (6,7) and (0,2,8,10)

can be selected in additionto theessential prime implicants for obtaining the
minimal Boolean expression is given

F = b’c’+cd’+a’bc+b’d’

Reduced prime implicant table

Minterms
Prime implicants
0 1 2 5 6 7 8 9 10 14
1,5 a’c’d X X
5,7 a’bd X X
6,7 a’bc X X
0,2,8,10* b’d’ X X X X
√ √ √ √ √

QUESTIONS

Part :A
1. Empirical formula to find the number of parity bits in the Hamming code generation.
2. Point out the gray code for given Binary Numbers i. (10101101) 2 ii. (1010111000)2
3. Perform the operation 9 – 3 using 2’s complement.
4. Convert the given non-canonical SOP into canonical form. F = AB’+AC+B’C
5. Brief the redundant literal rule.

Part :B
1. Assess the following conversions
a. (12AEF)16 to (?)10 and (?)2
b. (11011.0101)2 to (?)8 and (?)16
c. (358.255)10 to (?)8 and (?)16.
2. Suppose that an incoming message 11110101111 is received. Detect the error bit and
Correct it with even parity scheme at the receiver end.
3. Point out the Canonical form for the given SOP and POS functions.
a. F(A,B,C,D)=AB + A’BD + A’CD’
b. F(A,B,C)=(A + B’ ) (A + C’)
c. F(A,B,C)=A (A + C’) (A + B)

92
 AND → invert-AND symbol
OR → NOR gate

Step 3:Check each line has even number of bubbles. If any line does not have even number of bubbles
the insert bubble (i.e. input A, B’,A’, Bhas odd number of bubbles. Therefore apply the inverted inputs to
make even numbers of bubbles)

10. QUINE-MC CLUSKEY (OR) TABULATION METHOD

11.

Definition: It is used to simplify the Boolean expression for more variables.

The map methodf implication is convenient method as long as the numbers of variables do not
exceed fivevariables. If the number of variable increases, it is difficult to make the simplification of
expression. F the number of variables increases it is difficult to make the simplification of expression. To
avoid this complex and to meet this need W.V. Quine and E.J. McCluskey developed an exact tabulation
method to simplify the Boolean expression. This method is called as tabulation method or Quine
McCluskey method.

The summary steps are as follows to simplify the Boolean expression.

Step 1. List all minterms in the binary form.

Step 2. Separate the number of groups according to the number of 1’s.
Step 3. Compare each binary number with every group in the adjacent next highest category
group and they differ only one bit position. Put check mark if comparison is possible (-) and copy
9.3 NOR IMPLEMENTATION

The NOR operation is the dual of the AND operation. Therefore all procedures and rules for NOR
logic are the dual for the corresponding procedures and rules developed for NAND logic. The NOR gate
is another universal gate that can be used to implement any Boolean function. The alternative
representation of NOR gate according to demorgan’s theorem is shown below.

Steps to be followed

1. Simply the given logic expression and convert it into product of sum (POS) form.
2. Draw the AND – OR-NOT realization.
3. Replace every OR gate by NOR, every AND gate by a bubbled AND gate and ever inerter by a
NOR inverter.
4. Draw the final circuit using only the NOR gates.

Example Problem:

Implement the following function by using NOR gates Y=(A’+B+C)(A+B)D

Solution:

Step 1: Implement the given Boolean function by usingAND, ORandNOTgate as shown below.

Step 2:
Replace OR → NOR
AND → invert AND
NOT → NOR invert
 Digital circuits are frequently constructed with NAND and NOR gates rather than with AND and
OR gates. NAND and NOR gates are easier to fabricate. So rules and procedures have been developed for
the conversion from Boolean functions given in terms of AND, OR and NOT into equivalent NAND and
NOR logic diagrams.

Two level NAND- NAND implementation

To facilitate the conversion to NAND logic, it is convenient to define an alternative graphic

symbol for the gate. The alternate representation of NAND gate is shown in fig. according to De
Morgan’s theorem

Steps to be followed
1. Simplify the given logic expression and convert it in the SOP form
2. Draw the logic circuit using AND,OR and NOT gate
3. Replace every AND gate by a NAND gate, Every OR gate by a bubbled OR gate and NOT gate
by a NAND inverter.
4. Replace bubbled-OR gate by NAND gate.

Example Problem:

Implement the following Boolean equation using only NAND gatesY=AB+CDE+F

Solution
Step 1: realization using basic gates

Step 2: replace
AND →NAND
OR →bubbled – OR
NOT →NAND inverter
 ’ ’
Y=B C +BC

9. DON’T CARE CONDITIONS

 An output condition that can be regarded as either high or low

The logical sum of the minterms associated with a Boolean function specifies the conditions under
which the function is equal to 1. The function is equal to 0 for the rest of the minterms. This pair of
conditions assumes that all the combinations of the values for the variables of the function are valid. In
practice, in some applications the function is not specified for certain combinations of the variables. As an
example, the four-bit binary code for the decimal digits has six combinations that are not used and
consequently are considered to be unspecified. Functions that have unspecified outputs for some input
combinations are called incompletely specified functions. In most applications, we simply don’t care what
value is assumed by the function for the unspecified minterms. For this reason, it is customary to call the
unspecified minterm of a function don’t care conditions. These don’t care conditions can be used on a
map to provide further simplification of the Boolean expression.

A don’t care minterm is a combination of variables whose logical value is not specified. Such a
minterm cannot be marked with a 1 in the map, because it would require that the function always be a 1
for such a combination. Likewise putting a 0 on the square requires the function to be 0. To distinguish
don’t care condition from 1’s or the 0’s an X is used. Thus an X inside a square in the map indicates that
we don’t care whether the value of 0 or 1 is assigned to F for the particular minterm.
2. Grouping Eight adjacent ones (Octet)
Representation standard SOP on K-map
Example 1:
’ ’ ’
Plot Boolean expression Y=ABC +ABC+A B C on the Karnaugh map

Example 2:
’ ’ ’ ’ ’ ’ ’ ’
Plot Boolean expression Y=A BC D + AB’CD +A BCD +AB CD+ABC D on the karnaugh map.
 The labelling of the rows and columns of a 1, 2, 3 and 4 variable K-map using Gray code and the
sum terms(maxterm) corresponding to each cell is shown in the figure(a) (b) (c) and (d)

8.1 Plotting a Karnaugh Map

Representation of truth table on K-map

 Karnaugh map method gives us a systematic approach for simplifying a Boolean expression.
Karnaugh map method was first proposed by Veitch and modified by Karnaugh, hence it is known as
Karnaugh Map or K-map.
n
K-map contains boxes called cells. Each of the cell represents one of the 2 possible products that
2 3
can be formed from n variables. A two variable mzp contains 2 =4 cells, a three variable contains 2 =8
4
cells and four variable contains 2 =16 cells. The following figure shows the outline of 1, 2, 3 and 4
variable
maps.

The product term(minterm) assigned to the cells of K-map by labelling each row and column is
shown in 1, 2, 3 and 4 variable map and the product term(minterm) corresponding to each cell is shown
in the below figure (a),(b),(c) and (d).

The labelling of the rows and columns of a 1, 2, 3 and 4 variable K-map using Gray code and the
 = (A’ + B’ + C + D’)(A + B’ + C + D’)

The third term, A + B’ + C’ + D, is already in standard form. The standardPOS form of the original
expression is as follows:
(A’ + B + C)(B’ + C + D’)(A + B’ + C’ + D) = (A’ + B + C + D’)(A’ + B + C +D) (A’ + B’ + C + D’)(A + B’ + C + D’) (A + B’ +
C’ + D)

7.2 CANONICAL FORMS OF BOOLEAN EXPRESSIONS

With one variable x & x.
With two variables x y, x y, x y and x y.
With three variables x’ y’ z’, x’ y’ z, x’ y z’, x’ y z, x y’ z’, x y’ z, x y z’ & x y z.

These eight AND terms are called Minterms.

X Y Z MINTERM DESIGNATION
0 0 0 X’Y’Z’ m0
0 0 1 X’Y’Z m1
0 1 0 X’YZ’ m2
0 1 1 X’YZ m3
1 0 0 XY’Z’ m4
1 0 1 XY’Z m5
1 1 0 XYZ’ m6
1 1 1 XYZ m7

Maxterm is the complement of its corresponding minterm and vice versa

X Y Z MAXTERMS DESIGNATION
0 0 0 X+Y+Z M0
0 0 1 X+Y+Z’ M1
0 1 0 X+Y’+Z M2
0 1 1 X+Y’+Z’ M3
1 0 0 X’+Y+Z M4
1 0 1 X’+Y+Z’ M5
1 1 0 X’+Y’+Z M6
1 1 1 X’+Y’+Z’ M7

For example the function F (for minterms)

x y z F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

F = x’ y’ z + x y’ z’ + x y z F = m1 + m4 + m7
Any Boolean function can be expressed as a sum of minterms (sum of products SOP) or product of maxterms
(product of sums POS).
For example the function F (for maxterms)

F’ = x’ y’ z’ + x’ y z’ + x’ y z + x y’ z + x y z’
The complement of F’ = (F’)’= F
Convert each of the following Boolean expressions to SOP form:
(a) AB + B(CD + EF)
(b) (A + B)(B + C + D)
(c) [(A + B)’ + C+’

The Standard SOP Form

So far, you have seen SOP expressions in which some of the product terms do not contain all of the
variables in the domain of the expression.
For example, the expression A’BC’ + AB’D + ABC’D’ has a domain made up of the variables A, B, C. and D.
However, notice that the complete set of variables in the domain is not represented in the first two terms of the
expression; that is, D or D’ is missing from the first term and C or C’ is missing from the second term.
A standard SOP expression is one in which all the variables in the domain appear in each product term in
the expression. For example, A’BCD’ + ABC’D+ AB’CD are a standard SOP expression.

Converting Product Terms to Standard SOP:

Each product term in an SOP expression that does not contain all the variables in the domain can be
expanded to standard SOP to include all variables in the domain and their complements. As stated in the

following steps, a nonstandard SOP expression is converted into standard form using Boolean algebra rule (A +
A’ = 1) i.e., A variable added to its complement equals 1.

Step 1: Multiply each nonstandard product term by a term made up of the sum of a missing variable and
its complement. This results in two product terms. As you know, you can multiply anything by 1 without changing
its Value.

Step 2: Repeat Step 1 until all resulting product terms contain all variables in the domain in either
complemented or uncomplemented form. In converting a product term to standard form, the number of product
terms is doubled for each missing variable.

Example
Convert the following Boolean expression into standard SOP form: AB’C + A’B’ + ABC’D

Solution

The domain of this SOP expression A, B, C, D. Take one term at a time.

The first term, ABC, is missing variable D or D’, so multiply the first term by(D + D) as follows: AB’C =
AB’C(D + D’) = AB’CD + AB’CD’
In this case, two standard product terms are the result.

The second term, A’B’; is missing variables C or C’ and D or D’, so first multiply the second term by C + C’ as
follows:
A’B’ = A’B’(C + C’) = A’B’C + A’B’C’

The two resulting terms are missing variable D or D’, so multiply both terms by (D + D) as follows
A’B’C(D + D’) + A’B’C’(D + D’)= A’B’CD + A’B’CD’ + A’B’C’D + A’B’C’D’

In this case, four standard product terms are the result.

The third term, ABC’D, is already in standard form. The complete standard SOP form of the original expression is
as follows:
AB’C + A’B’ + ABC’D = AB’CD + AB’CD ‘+ A’ B’CD + A’B’CD’ + A’B’C’D +A’B’C’D’ + ABC’D

7.1.2 The Product-of-Sums (POS) Form

A sum term was defined before as a term consisting of the sum (Boolean addition) of literals (variables or
 The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A dot (.) is
used to show the AND operation i.e. A.B. Bear in mind that this dot is sometimes omitted i.e. AB.

OR gate:

The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high. A
plus (+) is used to show the OR operation.

NOT gate:

7. Simplification of Boolean Expressions

Minimization of Boolean functions is an approach where a given Boolean expression can be transformed
from one form to another equivalent form by applying Boolean Theorems. By minimizing the expressions the
individual components used in electrical circuits can be minimized or reduced. This allows designers to make use
of fewer components, thus reducing the cost of a particular system. It should be noted that there are no fixed
rules that can be used to minimize a given expression. It is left to an individual’s ability to apply Boolean
Theorems in order to minimize a function.

Examples:

Example 1:

Using Boolean algebra techniques, simplify the expression X . Y + X (Y + Z) + Y (Y + Z)

Solution:

Given: X . Y + X (Y + Z) + Y (Y + Z).
Applying distributive property, we get

X . Y + X (Y + Z) + Y (Y + Z) = X . Y + X . Y + X . Z + Y . Y + Y . Z

We know B . B = B
=X.Y+X.Y+X.Z+Y+Y.Z

We know A . B + A . B = A . B
=X.Y+X.Z+Y+Y.Z
= X . Y + X . Z + Y [We know (B + BC = B)]
= Y + XZ
 A B C Maxterm
0 0 0 A+B+C
0 0 1 A+B+C’
0 1 0 A+B’+C
0 1 1 A+B’+C’
1 0 0 A’+B+C
1 0 1 A’+B+C’
1 1 0 A’+B’+C
1 1 1 A’+B’+C’

So, if the number of variables is n, then the possible number of maxterms is 2n. The main
property of a maxterm is that it possesses the value of 0 for only one combination of n input
variables and the rest of the 2n –1 combinations have the logic value of 1. This means, for the
above three variables example, if A = 1, B = 1, C = 0 i.e., for input combination of 110, there is
only one combination A′ + B′ + C that has the value 0, the rest of the seven combinations have
the value 1.

Canonical Product of Sum Expression:

When a Boolean function is expressed as the logical product of all the maxterms from the rows of
a truth table, for which the value of the function is 0, it is referred to as the canonical product of
sum expression. The same can be expressed in a compact form by listing the corresponding
decimal equivalent codes of the maxterms containing a function value of 0. For example, if the
canonical product of sums form of a three-variable logic function F has the maxterms A + B + C,
A + B′ + C, and A′ + B + C′, this can be expressed as the product of the decimal codes
corresponding to thesemaxterms as below,

F (A,B,C) = Π (0,2,5)

= M0 M2 M5

= (A + B + C) (A + B′ + C) (A′ + B + C′)

where Π (0,2,5) represents the product of maxterms corresponding to decimal codes 0, 2, and 5.
The canonical product of sums form of a logic function can be obtained by using the following
procedure.

1. Check each term in the given logic function. Retain it if it is a maxterm, continue to examine
the next term in the same manner.

2. Examine for the variables that are missing in each sum term that is not a maxterm. If the
missing variable in the maxterm is X, add that maxterm with (X.X′).

3. Expand the expression using the properties and postulates as described earlier and discard the
redundant terms. Some examples are given here to explain the above procedure.

5. Boolean Function
 In Boolean algebra, the logical product of several variables on which a function depends is
considered to be a product term. In other words, the AND function is referred to as a product term
or standard product. The variables in a product term can be either in true form or in
complemented form. For example, ABC′ is a product term.

Sum Term:

An OR function is referred to as a sum term. The logical sum of several variables on which
a function depends is considered to be a sum term. Variables in a sum term can also be either in
true form or in complemented form. For example, A + B + C′ is a sum term.

Sum of Products (SOP):

The logical sum of two or more logical product terms is referred to as a sum of products
expression. It is basically an OR operation on AND operated variables. For example, Y = AB +
BC + AC or Y = A′B + BC + AC′ are sum of products expressions.

Product of Sums (POS):

Similarly, the logical product of two or more logical sum terms is called a product of sums
expression. It is an AND operation on OR operated variables. For example, Y = (A + B + C)(A +
B′ + C)(A + B + C′) or Y = (A + B + C)(A′ + B′ + C′) are product of sums expressions.

Standard form:

The standard form of the Boolean function is when it is expressed in sum of the products
or product of the sums fashion. The examples stated above, like Y =AB + BC + AC or Y = (A +
B + C)(A + B′ + C)(A + B + C′) are the standard forms. However, Boolean functions are also
sometimes expressed in nonstandard forms like F = (AB + CD)(A′B′ + C′D′), which is neither a
sum of products form nor a product of sums form. However, the same expression can be
converted to a standard form with help of various Boolean properties, as:
F = (AB + CD)(A′B′ + C′D′) = A′B′CD + ABC′D′

4.1 Minterm

A product term containing all n variables of the function in either true or complemented
form is called the minterm. Each minterm is obtained by an AND operation of the variables in
their true form or complemented form. For a two-variable function, four different combinations
are possible, such as, A′B′, A′B, AB′, and AB. These product terms are called the fundamental
products or standard products or minterms. In the minterm, a variable will possess the value 1 if it
is in true or uncomplemented form, whereas, it contains the value 0 if it is in complemented form.
For three variables function, eight minterms are possible as listed in the following table

A B C Minterm
0 0 0 A’B’C’
0 0 1 A’B’C
Involution law:

 ( X' ) ' = X

Laws of complementarity:

 X + X' = 1
 X • X' = 0

Commutative laws:

 X+Y=Y+X
 X•Y=Y•X

Associative laws:

 (X + Y) + Z = X + (Y + Z) = X + Y + Z
 (XY)Z = X(YZ) = XYZ

Distributive laws:

 X( Y + Z ) = XY + XZ
 X + YZ = ( X + Y ) ( X + Z )

Simplification theorems:

 X Y + X Y' = X
 ( X + Y ) ( X + Y' ) = X
 X + XY = X
 X(X+Y)=X
 ( X + Y' ) Y = XY
 XY' + Y = X + Y

DeMorgan’s laws:

There are two “de Morgan´s” rules or theorems,

 Two separate terms NOR´ed together is the same as the two terms inverted (Complement)
and AND´ed for example, (X+Y)’ = X’.Y’.
 Two separate terms NAND´ed together is the same as the two terms inverted (Complement)
and OR´ed for example, (X.Y)’ =X’ +Y’.

Duality:

“Every algebraic expression deducible from the postulates of Boolean Algebra remains valid if the
operations and identity elements are interchanged.”
 (X+Y+Z+…)D=XYZ…
 (X Y Z…) D = X + Y + Z + …
 [ f ( X1, X2, … XN, 0, 1, +, • ) ] D = f ( X1, X2, … XN, 1, 0, •, + )
Moris Mano, “Digital Computer Fundamentals” TMH 3rd Edition

HAMMING, R. →. “Error Detecting and Error Correcting Codes.” Bell System Tech. Jour., 29
–
A.P GODSE,D.A.GODSE .”Digital Systems”.Technical

D.A.Godse A.P.Godse
 ‐

‐ ‐

‐
‐
• A code is said to be self complementary if the code for 9’s complement of N i.e. 9

• Decimal 9 is the complement of code for 0, 8 for 1, 7 for 2 and so on.

• For a code to be

• In general, a code is self

which is same as 9’s complement of the number.












• Single

• Burst Error: two versa. (Here doesn’t

• Simple Parity check

• Two
• Checksum
• Cyclic redundancy check

–
 



√11011.1









 So, to subtract two signed numbers, take the 2’s complement of the subtrahend and add. Discard
 1’s Complement



the weight of the sign bit, summing all the weights where there are 1’s and adding 1 to

xpressed in 1’s complement

 Summing the weights where there are 1’s

2’s Complement


 –

mbers expressed in 2’s complement

 Summing weights where there are 1’s



Steps for ’s o ple e t BCD su tra tio
1. Fi d the ’s o ple e t of a egative u er.
2. Add two numbers using BCD addition
3. If arry is ot ge erated fi d the ’s o ple e t of the result.





– –
1’s Complement Form
2’s Complement Form –





1’s Complement Form


 f obtaining 10’s complement

A decimal number 456, find 9's complement and 10’s complement of this number

In 9’s complement subtraction when 9’s complement of smaller number number is added to the

carry).when larger number is subtracted from the smaller number, there is no carry, and the result is in 9’s

Subtraction using 9’s complements:

Steps for 9’s complement BCD subtraction

Find the 9’s complement of a negative number.

If carry is generated add carry to the result otherwise find the 9’s com
1’s complement Subtraction of larger number from smaller number

the 1’s complement of the larger number.

Add the 1’s complement to the smaller number.
Answer is in 1’s complement form. To get the answer in true form take the 1’s complement and

Advantages of 1’s complement subtrac

The 1’s complement subtraction can be accomplished with an binary adder. Therefore , this method

The 1’s complement of a number is easily obtained by inverting each bit in the number.
2’s complement Subt
Like 1’s complement subtraction, in 2’s complement subtraction, the subtraction is accomplished

2’s complement Subtraction of smaller number from larger number

Determine the 2’s complement of the smaller number.

2’s complement to the larger number.

2’s complement Subtraction of larger number from smaller number

Determine the 2’s complement of the larger number.

Add the 2’s complement to the smaller number.
 1)’s Complement

1)’s complement of N is defined as r

Subtraction with r’s complement




Add the minuend M to the r’s complement of the subtrahend N.


 carry does not occurs, take the r’s complement of the nu

1)’s Complement

 1)’s complement is same as r’s complement except for

1)’s complement of the subtrahend N.


 1)’s complement of the number

It is classified into four types they are 1’s complement , 2’s complement , 9’s complement and
10’s complement.
1’s complement representation: The 1’s complement of a binary number is the number that
results when we change all 1’s to zeros and the zeros to ones.
2’s complement representation:
The 2’s complement is the binary number that results when we add 1 to the 1’s complement.
Problems related to 1’s complement and 2’s complement :
+……. +………
MSB
 UNIT V- DIGITAL ELECTRONICS

Number systems – Binary arithmetic - Boolean algebra, laws & theorems – Boolean Functions - Simplification of
Boolean functions - Logic gates - Implementation of Boolean expressions using logic gate - Standard forms of
Boolean expression.

Number System
A number system relates quantities and symbols. In digital system how information is represented is key
and there are different radices, i.e. number bases, which a numbering system can use.
Digital computer
Any class of devices capable of solving problems by processing information in discrete form. It operates on
data, including letters and symbols, which are expressed in binary form i.e using only two digits 0 and 1.
The block diagram of digital computer is given below:

Processor (or)
Control Unit Arithmetic unit

Storage (or)
Memory Unit

Input Output
Devices and Devices and
Control Control
The memory unit stores programs as well as input, output and intermediate data. The processor unit
performs arithmetic and other data processing tasks as specified by the program.The control unit
supervises the flow of information between various units. The program and data prepared by the user
are transferred into the memory unit by means of an input device such as punch card reader (or) tele
typewriter. An output device, such as printer, receives the result of the computations and the printed
results are presented to the user.
Number Representation:
It can have different base values like: binary (base-2), octal (base-8), decimal (base 10) and
hexadecimal (base 16),here the base number represents the number of digits used in that numbering
system. As an example, in decimal numbering system the digits used are: 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9.
Therefore the digits for binary are: 0 and 1, the digits for octal are: 0, 1, 2, 3, 4, 5, 6 and 7. For the
hexadecimal numbering system, base 16, the digits are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F.

2
 A few selected applications of the UJT are as follows:
It is used to trigger SCRs and TRIACs It is used in non-sinusoidal oscillators
It is used in phase control and timing circuits It is used in saw tooth
generatorsIt is used in oscillator circuit design.

QUESTIONS
PART A
1. What is a semiconductor?
2. Mention the application of PN junction diode.
3. What is a Zener diode?
4. List the three configuration of transistor.
5. Define α and β.
6. What is a FET?
7. List two applications of JFET and SCR.
8. What is a SCR? Give two applications of it.

PART B
1. Explain the V-I characteristics of PN junction diode.
2. Draw the circuit symbol for MOSFET and explain its characteristics.
3. Explain the application of the following devices,
(a) UJT
(b) FET
4. Explain the working principle and V-I characteristics of Zener diode.
5. What is a SCR? Explain its characteristics.
6. Draw the circuit diagram of a transistor. Explain in detail the transistor configuration.

TEXT / REFERENCE BOOKS

1. Dr.Sanjay Sharma, Electronic Devices and Circuits, 2nd edition, S.K.Kataria &
Sons, 2012.
2.G.K.Mithal, Basic Electronic Devices and circuits, 2nd Edition,
G.K.Publishers Pvt,2008
3.Smarajit Ghosh, Fundamentals of Electrical and Electronics Engineering, 2nd
Edition, PHI Learning Private Ltd, 2010.

UNIT – V
RECTIFIERS, AMPLIFIERS AND OSCILLATORS

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